| blob | 6f480827b94d36fe47dd3c0c09dd9c8c9e1363ec |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
4 */
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "marvell,mmp3-smp";
18 cpu@0 {
19 compatible = "marvell,pj4b";
20 device_type = "cpu";
21 next-level-cache = <&l2>;
22 reg = <0>;
23 };
25 cpu@1 {
26 compatible = "marvell,pj4b";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <1>;
30 };
31 };
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
37 interrupt-parent = <&gic>;
38 ranges;
40 axi@d4200000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0xd4200000 0x00200000>;
45 ranges;
47 interrupt-controller@d4282000 {
48 compatible = "marvell,mmp3-intc";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0xd4282000 0x1000>,
52 <0xd4284000 0x100>;
53 mrvl,intc-nr-irqs = <64>;
54 };
56 pmic_mux: interrupt-controller@d4282150 {
57 compatible = "mrvl,mmp2-mux-intc";
58 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x150 0x4>, <0x168 0x4>;
62 reg-names = "mux status", "mux mask";
63 mrvl,intc-nr-irqs = <4>;
64 };
66 rtc_mux: interrupt-controller@d4282154 {
67 compatible = "mrvl,mmp2-mux-intc";
68 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-controller;
70 #interrupt-cells = <1>;
71 reg = <0x154 0x4>, <0x16c 0x4>;
72 reg-names = "mux status", "mux mask";
73 mrvl,intc-nr-irqs = <2>;
74 };
76 hsi3_mux: interrupt-controller@d42821bc {
77 compatible = "mrvl,mmp2-mux-intc";
78 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-controller;
80 #interrupt-cells = <1>;
81 reg = <0x1bc 0x4>, <0x1a4 0x4>;
82 reg-names = "mux status", "mux mask";
83 mrvl,intc-nr-irqs = <3>;
84 };
86 gpu_mux: interrupt-controller@d42821c0 {
87 compatible = "mrvl,mmp2-mux-intc";
88 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
89 interrupt-controller;
90 #interrupt-cells = <1>;
91 reg = <0x1c0 0x4>, <0x1a8 0x4>;
92 reg-names = "mux status", "mux mask";
93 mrvl,intc-nr-irqs = <3>;
94 };
96 twsi_mux: interrupt-controller@d4282158 {
97 compatible = "mrvl,mmp2-mux-intc";
98 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
101 reg = <0x158 0x4>, <0x170 0x4>;
102 reg-names = "mux status", "mux mask";
103 mrvl,intc-nr-irqs = <5>;
104 };
106 hsi2_mux: interrupt-controller@d42821c4 {
107 compatible = "mrvl,mmp2-mux-intc";
108 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
111 reg = <0x1c4 0x4>, <0x1ac 0x4>;
112 reg-names = "mux status", "mux mask";
113 mrvl,intc-nr-irqs = <2>;
114 };
116 dxo_mux: interrupt-controller@d42821c8 {
117 compatible = "mrvl,mmp2-mux-intc";
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
121 reg = <0x1c8 0x4>, <0x1b0 0x4>;
122 reg-names = "mux status", "mux mask";
123 mrvl,intc-nr-irqs = <2>;
124 };
126 misc1_mux: interrupt-controller@d428215c {
127 compatible = "mrvl,mmp2-mux-intc";
128 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 reg = <0x15c 0x4>, <0x174 0x4>;
132 reg-names = "mux status", "mux mask";
133 mrvl,intc-nr-irqs = <31>;
134 };
136 ci_mux: interrupt-controller@d42821cc {
137 compatible = "mrvl,mmp2-mux-intc";
138 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 reg = <0x1cc 0x4>, <0x1b4 0x4>;
142 reg-names = "mux status", "mux mask";
143 mrvl,intc-nr-irqs = <2>;
144 };
146 ssp_mux: interrupt-controller@d4282160 {
147 compatible = "mrvl,mmp2-mux-intc";
148 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 reg = <0x160 0x4>, <0x178 0x4>;
152 reg-names = "mux status", "mux mask";
153 mrvl,intc-nr-irqs = <2>;
154 };
156 hsi1_mux: interrupt-controller@d4282184 {
157 compatible = "mrvl,mmp2-mux-intc";
158 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 reg = <0x184 0x4>, <0x17c 0x4>;
162 reg-names = "mux status", "mux mask";
163 mrvl,intc-nr-irqs = <4>;
164 };
166 misc2_mux: interrupt-controller@d4282188 {
167 compatible = "mrvl,mmp2-mux-intc";
168 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 reg = <0x188 0x4>, <0x180 0x4>;
172 reg-names = "mux status", "mux mask";
173 mrvl,intc-nr-irqs = <20>;
174 };
176 hsi0_mux: interrupt-controller@d42821d0 {
177 compatible = "mrvl,mmp2-mux-intc";
178 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 reg = <0x1d0 0x4>, <0x1b8 0x4>;
182 reg-names = "mux status", "mux mask";
183 mrvl,intc-nr-irqs = <5>;
184 };
186 usb_otg_phy0: usb-otg-phy@d4207000 {
187 compatible = "marvell,mmp3-usb-phy";
188 reg = <0xd4207000 0x40>;
189 #phy-cells = <0>;
190 status = "disabled";
191 };
193 usb_otg0: usb-otg@d4208000 {
194 compatible = "marvell,pxau2o-ehci";
195 reg = <0xd4208000 0x200>;
196 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&soc_clocks MMP2_CLK_USB>;
198 clock-names = "USBCLK";
199 phys = <&usb_otg_phy0>;
200 phy-names = "usb";
201 status = "disabled";
202 };
204 mmc1: mmc@d4280000 {
205 compatible = "mrvl,pxav3-mmc";
206 reg = <0xd4280000 0x120>;
207 clocks = <&soc_clocks MMP2_CLK_SDH0>;
208 clock-names = "io";
209 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
210 status = "disabled";
211 };
213 mmc2: mmc@d4280800 {
214 compatible = "mrvl,pxav3-mmc";
215 reg = <0xd4280800 0x120>;
216 clocks = <&soc_clocks MMP2_CLK_SDH1>;
217 clock-names = "io";
218 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
219 status = "disabled";
220 };
222 mmc3: mmc@d4281000 {
223 compatible = "mrvl,pxav3-mmc";
224 reg = <0xd4281000 0x120>;
225 clocks = <&soc_clocks MMP2_CLK_SDH2>;
226 clock-names = "io";
227 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
228 status = "disabled";
229 };
231 mmc4: mmc@d4281800 {
232 compatible = "mrvl,pxav3-mmc";
233 reg = <0xd4281800 0x120>;
234 clocks = <&soc_clocks MMP2_CLK_SDH3>;
235 clock-names = "io";
236 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
237 status = "disabled";
238 };
240 camera0: camera@d420a000 {
241 compatible = "marvell,mmp2-ccic";
242 reg = <0xd420a000 0x800>;
243 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
245 clock-names = "axi";
246 #clock-cells = <0>;
247 clock-output-names = "mclk";
248 status = "disabled";
249 };
251 camera1: camera@d420a800 {
252 compatible = "marvell,mmp2-ccic";
253 reg = <0xd420a800 0x800>;
254 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
256 clock-names = "axi";
257 #clock-cells = <0>;
258 clock-output-names = "mclk";
259 status = "disabled";
260 };
261 };
263 apb@d4000000 {
264 compatible = "simple-bus";
265 #address-cells = <1>;
266 #size-cells = <1>;
267 reg = <0xd4000000 0x00200000>;
268 ranges;
270 timer: timer@d4014000 {
271 compatible = "mrvl,mmp-timer";
272 reg = <0xd4014000 0x100>;
273 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&soc_clocks MMP2_CLK_TIMER>;
275 };
277 uart1: uart@d4030000 {
278 compatible = "mrvl,mmp-uart";
279 reg = <0xd4030000 0x1000>;
280 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&soc_clocks MMP2_CLK_UART0>;
282 resets = <&soc_clocks MMP2_CLK_UART0>;
283 reg-shift = <2>;
284 status = "disabled";
285 };
287 uart2: uart@d4017000 {
288 compatible = "mrvl,mmp-uart";
289 reg = <0xd4017000 0x1000>;
290 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&soc_clocks MMP2_CLK_UART1>;
292 resets = <&soc_clocks MMP2_CLK_UART1>;
293 reg-shift = <2>;
294 status = "disabled";
295 };
297 uart3: uart@d4018000 {
298 compatible = "mrvl,mmp-uart";
299 reg = <0xd4018000 0x1000>;
300 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&soc_clocks MMP2_CLK_UART2>;
302 resets = <&soc_clocks MMP2_CLK_UART2>;
303 reg-shift = <2>;
304 status = "disabled";
305 };
307 uart4: uart@d4016000 {
308 compatible = "mrvl,mmp-uart";
309 reg = <0xd4016000 0x1000>;
310 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&soc_clocks MMP2_CLK_UART3>;
312 resets = <&soc_clocks MMP2_CLK_UART3>;
313 reg-shift = <2>;
314 status = "disabled";
315 };
317 gpio: gpio@d4019000 {
318 compatible = "marvell,mmp2-gpio";
319 #address-cells = <1>;
320 #size-cells = <1>;
321 reg = <0xd4019000 0x1000>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "gpio_mux";
326 clocks = <&soc_clocks MMP2_CLK_GPIO>;
327 resets = <&soc_clocks MMP2_CLK_GPIO>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 ranges;
332 gcb0: gpio@d4019000 {
333 reg = <0xd4019000 0x4>;
334 };
336 gcb1: gpio@d4019004 {
337 reg = <0xd4019004 0x4>;
338 };
340 gcb2: gpio@d4019008 {
341 reg = <0xd4019008 0x4>;
342 };
344 gcb3: gpio@d4019100 {
345 reg = <0xd4019100 0x4>;
346 };
348 gcb4: gpio@d4019104 {
349 reg = <0xd4019104 0x4>;
350 };
352 gcb5: gpio@d4019108 {
353 reg = <0xd4019108 0x4>;
354 };
355 };
357 twsi1: i2c@d4011000 {
358 compatible = "mrvl,mmp-twsi";
359 reg = <0xd4011000 0x70>;
360 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
362 resets = <&soc_clocks MMP2_CLK_TWSI0>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 mrvl,i2c-fast-mode;
366 status = "disabled";
367 };
369 twsi2: i2c@d4031000 {
370 compatible = "mrvl,mmp-twsi";
371 reg = <0xd4031000 0x70>;
372 interrupt-parent = <&twsi_mux>;
373 interrupts = <0>;
374 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
375 resets = <&soc_clocks MMP2_CLK_TWSI1>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 status = "disabled";
379 };
381 twsi3: i2c@d4032000 {
382 compatible = "mrvl,mmp-twsi";
383 reg = <0xd4032000 0x70>;
384 interrupt-parent = <&twsi_mux>;
385 interrupts = <1>;
386 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
387 resets = <&soc_clocks MMP2_CLK_TWSI2>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 status = "disabled";
391 };
393 twsi4: i2c@d4033000 {
394 compatible = "mrvl,mmp-twsi";
395 reg = <0xd4033000 0x70>;
396 interrupt-parent = <&twsi_mux>;
397 interrupts = <2>;
398 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
399 resets = <&soc_clocks MMP2_CLK_TWSI3>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
406 twsi5: i2c@d4033800 {
407 compatible = "mrvl,mmp-twsi";
408 reg = <0xd4033800 0x70>;
409 interrupt-parent = <&twsi_mux>;
410 interrupts = <3>;
411 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
412 resets = <&soc_clocks MMP2_CLK_TWSI4>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 status = "disabled";
416 };
418 twsi6: i2c@d4034000 {
419 compatible = "mrvl,mmp-twsi";
420 reg = <0xd4034000 0x70>;
421 interrupt-parent = <&twsi_mux>;
422 interrupts = <4>;
423 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
424 resets = <&soc_clocks MMP2_CLK_TWSI5>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 status = "disabled";
428 };
430 rtc: rtc@d4010000 {
431 compatible = "mrvl,mmp-rtc";
432 reg = <0xd4010000 0x1000>;
433 interrupts = <1 0>;
434 interrupt-names = "rtc 1Hz", "rtc alarm";
435 interrupt-parent = <&rtc_mux>;
436 clocks = <&soc_clocks MMP2_CLK_RTC>;
437 resets = <&soc_clocks MMP2_CLK_RTC>;
438 status = "disabled";
439 };
441 ssp1: spi@d4035000 {
442 compatible = "marvell,mmp2-ssp";
443 reg = <0xd4035000 0x1000>;
444 clocks = <&soc_clocks MMP2_CLK_SSP0>;
445 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
451 ssp2: spi@d4036000 {
452 compatible = "marvell,mmp2-ssp";
453 reg = <0xd4036000 0x1000>;
454 clocks = <&soc_clocks MMP2_CLK_SSP1>;
455 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
461 ssp3: spi@d4037000 {
462 compatible = "marvell,mmp2-ssp";
463 reg = <0xd4037000 0x1000>;
464 clocks = <&soc_clocks MMP2_CLK_SSP2>;
465 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
471 ssp4: spi@d4039000 {
472 compatible = "marvell,mmp2-ssp";
473 reg = <0xd4039000 0x1000>;
474 clocks = <&soc_clocks MMP2_CLK_SSP3>;
475 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480 };
482 l2: l2-cache-controller@d0020000 {
483 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
484 reg = <0xd0020000 0x1000>;
485 cache-unified;
486 cache-level = <2>;
487 };
489 soc_clocks: clocks@d4050000 {
490 compatible = "marvell,mmp2-clock";
491 reg = <0xd4050000 0x1000>,
492 <0xd4282800 0x400>,
493 <0xd4015000 0x1000>;
494 reg-names = "mpmu", "apmu", "apbc";
495 #clock-cells = <1>;
496 #reset-cells = <1>;
497 #power-domain-cells = <1>;
498 };
500 snoop-control-unit@e0000000 {
501 compatible = "arm,arm11mp-scu";
502 reg = <0xe0000000 0x100>;
503 };
505 gic: interrupt-controller@e0001000 {
506 compatible = "arm,arm11mp-gic";
507 interrupt-controller;
508 #interrupt-cells = <3>;
509 reg = <0xe0001000 0x1000>,
510 <0xe0000100 0x100>;
511 };
513 local-timer@e0000600 {
514 compatible = "arm,arm11mp-twd-timer";
515 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
516 IRQ_TYPE_EDGE_RISING)>;
517 reg = <0xe0000600 0x20>;
518 };
520 watchdog@e0000620 {
521 compatible = "arm,arm11mp-twd-wdt";
522 reg = <0xe0000620 0x20>;
523 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
524 IRQ_TYPE_EDGE_RISING)>;
525 };
526 };
527 };