| blob | 5698a3e241aa0ae867784488833e045695412506 |
1 /*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
16 / {
17 compatible = "ti,omap3430", "ti,omap3";
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu@0 {
37 compatible = "arm,cortex-a8";
38 device_type = "cpu";
39 reg = <0x0>;
41 clocks = <&dpll1_ck>;
42 clock-names = "cpu";
44 clock-latency = <300000>; /* From omap-cpufreq driver */
45 };
46 };
48 pmu@54000000 {
49 compatible = "arm,cortex-a8-pmu";
50 reg = <0x54000000 0x800000>;
51 interrupts = <3>;
52 ti,hwmods = "debugss";
53 };
55 /*
56 * The soc node represents the soc top level view. It is used for IPs
57 * that are not memory mapped in the MPU view or for the MPU itself.
58 */
59 soc {
60 compatible = "ti,omap-infra";
61 mpu {
62 compatible = "ti,omap3-mpu";
63 ti,hwmods = "mpu";
64 };
66 iva: iva {
67 compatible = "ti,iva2.2";
68 ti,hwmods = "iva";
70 dsp {
71 compatible = "ti,omap3-c64";
72 };
73 };
74 };
76 /*
77 * XXX: Use a flat representation of the OMAP3 interconnect.
78 * The real OMAP interconnect network is quite complex.
79 * Since it will not bring real advantage to represent that in DT for
80 * the moment, just use a fake OCP bus entry to represent the whole bus
81 * hierarchy.
82 */
83 ocp@68000000 {
84 compatible = "ti,omap3-l3-smx", "simple-bus";
85 reg = <0x68000000 0x10000>;
86 interrupts = <9 10>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90 ti,hwmods = "l3_main";
92 l4_core: l4@48000000 {
93 compatible = "ti,omap3-l4-core", "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x48000000 0x1000000>;
98 scm: scm@2000 {
99 compatible = "ti,omap3-scm", "simple-bus";
100 reg = <0x2000 0x2000>;
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0 0x2000 0x2000>;
105 omap3_pmx_core: pinmux@30 {
106 compatible = "ti,omap3-padconf",
107 "pinctrl-single";
108 reg = <0x30 0x238>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 #pinctrl-cells = <1>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0xff1f>;
116 };
118 scm_conf: scm_conf@270 {
119 compatible = "syscon", "simple-bus";
120 reg = <0x270 0x330>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges = <0 0x270 0x330>;
125 pbias_regulator: pbias_regulator@2b0 {
126 compatible = "ti,pbias-omap3", "ti,pbias-omap";
127 reg = <0x2b0 0x4>;
128 syscon = <&scm_conf>;
129 pbias_mmc_reg: pbias_mmc_omap2430 {
130 regulator-name = "pbias_mmc_omap2430";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <3000000>;
133 };
134 };
136 scm_clocks: clocks {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 };
140 };
142 scm_clockdomains: clockdomains {
143 };
145 omap3_pmx_wkup: pinmux@a00 {
146 compatible = "ti,omap3-padconf",
147 "pinctrl-single";
148 reg = <0xa00 0x5c>;
149 #address-cells = <1>;
150 #size-cells = <0>;
151 #pinctrl-cells = <1>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 pinctrl-single,register-width = <16>;
155 pinctrl-single,function-mask = <0xff1f>;
156 };
157 };
158 };
160 aes: aes@480c5000 {
161 compatible = "ti,omap3-aes";
162 ti,hwmods = "aes";
163 reg = <0x480c5000 0x50>;
164 interrupts = <0>;
165 dmas = <&sdma 65 &sdma 66>;
166 dma-names = "tx", "rx";
167 };
169 prm: prm@48306000 {
170 compatible = "ti,omap3-prm";
171 reg = <0x48306000 0x4000>;
172 interrupts = <11>;
174 prm_clocks: clocks {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
179 prm_clockdomains: clockdomains {
180 };
181 };
183 cm: cm@48004000 {
184 compatible = "ti,omap3-cm";
185 reg = <0x48004000 0x4000>;
187 cm_clocks: clocks {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 };
192 cm_clockdomains: clockdomains {
193 };
194 };
196 counter32k: counter@48320000 {
197 compatible = "ti,omap-counter32k";
198 reg = <0x48320000 0x20>;
199 ti,hwmods = "counter_32k";
200 };
202 intc: interrupt-controller@48200000 {
203 compatible = "ti,omap3-intc";
204 interrupt-controller;
205 #interrupt-cells = <1>;
206 reg = <0x48200000 0x1000>;
207 };
209 sdma: dma-controller@48056000 {
210 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
211 reg = <0x48056000 0x1000>;
212 interrupts = <12>,
213 <13>,
214 <14>,
215 <15>;
216 #dma-cells = <1>;
217 dma-channels = <32>;
218 dma-requests = <96>;
219 ti,hwmods = "dma";
220 };
222 gpio1: gpio@48310000 {
223 compatible = "ti,omap3-gpio";
224 reg = <0x48310000 0x200>;
225 interrupts = <29>;
226 ti,hwmods = "gpio1";
227 ti,gpio-always-on;
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 };
234 gpio2: gpio@49050000 {
235 compatible = "ti,omap3-gpio";
236 reg = <0x49050000 0x200>;
237 interrupts = <30>;
238 ti,hwmods = "gpio2";
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 };
245 gpio3: gpio@49052000 {
246 compatible = "ti,omap3-gpio";
247 reg = <0x49052000 0x200>;
248 interrupts = <31>;
249 ti,hwmods = "gpio3";
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
254 };
256 gpio4: gpio@49054000 {
257 compatible = "ti,omap3-gpio";
258 reg = <0x49054000 0x200>;
259 interrupts = <32>;
260 ti,hwmods = "gpio4";
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
267 gpio5: gpio@49056000 {
268 compatible = "ti,omap3-gpio";
269 reg = <0x49056000 0x200>;
270 interrupts = <33>;
271 ti,hwmods = "gpio5";
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 };
278 gpio6: gpio@49058000 {
279 compatible = "ti,omap3-gpio";
280 reg = <0x49058000 0x200>;
281 interrupts = <34>;
282 ti,hwmods = "gpio6";
283 gpio-controller;
284 #gpio-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
287 };
289 uart1: serial@4806a000 {
290 compatible = "ti,omap3-uart";
291 reg = <0x4806a000 0x2000>;
292 interrupts-extended = <&intc 72>;
293 dmas = <&sdma 49 &sdma 50>;
294 dma-names = "tx", "rx";
295 ti,hwmods = "uart1";
296 clock-frequency = <48000000>;
297 };
299 uart2: serial@4806c000 {
300 compatible = "ti,omap3-uart";
301 reg = <0x4806c000 0x400>;
302 interrupts-extended = <&intc 73>;
303 dmas = <&sdma 51 &sdma 52>;
304 dma-names = "tx", "rx";
305 ti,hwmods = "uart2";
306 clock-frequency = <48000000>;
307 };
309 uart3: serial@49020000 {
310 compatible = "ti,omap3-uart";
311 reg = <0x49020000 0x400>;
312 interrupts-extended = <&intc 74>;
313 dmas = <&sdma 53 &sdma 54>;
314 dma-names = "tx", "rx";
315 ti,hwmods = "uart3";
316 clock-frequency = <48000000>;
317 };
319 i2c1: i2c@48070000 {
320 compatible = "ti,omap3-i2c";
321 reg = <0x48070000 0x80>;
322 interrupts = <56>;
323 dmas = <&sdma 27 &sdma 28>;
324 dma-names = "tx", "rx";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 ti,hwmods = "i2c1";
328 };
330 i2c2: i2c@48072000 {
331 compatible = "ti,omap3-i2c";
332 reg = <0x48072000 0x80>;
333 interrupts = <57>;
334 dmas = <&sdma 29 &sdma 30>;
335 dma-names = "tx", "rx";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 ti,hwmods = "i2c2";
339 };
341 i2c3: i2c@48060000 {
342 compatible = "ti,omap3-i2c";
343 reg = <0x48060000 0x80>;
344 interrupts = <61>;
345 dmas = <&sdma 25 &sdma 26>;
346 dma-names = "tx", "rx";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 ti,hwmods = "i2c3";
350 };
352 mailbox: mailbox@48094000 {
353 compatible = "ti,omap3-mailbox";
354 ti,hwmods = "mailbox";
355 reg = <0x48094000 0x200>;
356 interrupts = <26>;
357 #mbox-cells = <1>;
358 ti,mbox-num-users = <2>;
359 ti,mbox-num-fifos = <2>;
360 mbox_dsp: dsp {
361 ti,mbox-tx = <0 0 0>;
362 ti,mbox-rx = <1 0 0>;
363 };
364 };
366 mcspi1: spi@48098000 {
367 compatible = "ti,omap2-mcspi";
368 reg = <0x48098000 0x100>;
369 interrupts = <65>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 ti,hwmods = "mcspi1";
373 ti,spi-num-cs = <4>;
374 dmas = <&sdma 35>,
375 <&sdma 36>,
376 <&sdma 37>,
377 <&sdma 38>,
378 <&sdma 39>,
379 <&sdma 40>,
380 <&sdma 41>,
381 <&sdma 42>;
382 dma-names = "tx0", "rx0", "tx1", "rx1",
383 "tx2", "rx2", "tx3", "rx3";
384 };
386 mcspi2: spi@4809a000 {
387 compatible = "ti,omap2-mcspi";
388 reg = <0x4809a000 0x100>;
389 interrupts = <66>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 ti,hwmods = "mcspi2";
393 ti,spi-num-cs = <2>;
394 dmas = <&sdma 43>,
395 <&sdma 44>,
396 <&sdma 45>,
397 <&sdma 46>;
398 dma-names = "tx0", "rx0", "tx1", "rx1";
399 };
401 mcspi3: spi@480b8000 {
402 compatible = "ti,omap2-mcspi";
403 reg = <0x480b8000 0x100>;
404 interrupts = <91>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 ti,hwmods = "mcspi3";
408 ti,spi-num-cs = <2>;
409 dmas = <&sdma 15>,
410 <&sdma 16>,
411 <&sdma 23>,
412 <&sdma 24>;
413 dma-names = "tx0", "rx0", "tx1", "rx1";
414 };
416 mcspi4: spi@480ba000 {
417 compatible = "ti,omap2-mcspi";
418 reg = <0x480ba000 0x100>;
419 interrupts = <48>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 ti,hwmods = "mcspi4";
423 ti,spi-num-cs = <1>;
424 dmas = <&sdma 70>, <&sdma 71>;
425 dma-names = "tx0", "rx0";
426 };
428 hdqw1w: 1w@480b2000 {
429 compatible = "ti,omap3-1w";
430 reg = <0x480b2000 0x1000>;
431 interrupts = <58>;
432 ti,hwmods = "hdq1w";
433 };
435 mmc1: mmc@4809c000 {
436 compatible = "ti,omap3-hsmmc";
437 reg = <0x4809c000 0x200>;
438 interrupts = <83>;
439 ti,hwmods = "mmc1";
440 ti,dual-volt;
441 dmas = <&sdma 61>, <&sdma 62>;
442 dma-names = "tx", "rx";
443 pbias-supply = <&pbias_mmc_reg>;
444 };
446 mmc2: mmc@480b4000 {
447 compatible = "ti,omap3-hsmmc";
448 reg = <0x480b4000 0x200>;
449 interrupts = <86>;
450 ti,hwmods = "mmc2";
451 dmas = <&sdma 47>, <&sdma 48>;
452 dma-names = "tx", "rx";
453 };
455 mmc3: mmc@480ad000 {
456 compatible = "ti,omap3-hsmmc";
457 reg = <0x480ad000 0x200>;
458 interrupts = <94>;
459 ti,hwmods = "mmc3";
460 dmas = <&sdma 77>, <&sdma 78>;
461 dma-names = "tx", "rx";
462 };
464 mmu_isp: mmu@480bd400 {
465 #iommu-cells = <0>;
466 compatible = "ti,omap2-iommu";
467 reg = <0x480bd400 0x80>;
468 interrupts = <24>;
469 ti,hwmods = "mmu_isp";
470 ti,#tlb-entries = <8>;
471 };
473 mmu_iva: mmu@5d000000 {
474 #iommu-cells = <0>;
475 compatible = "ti,omap2-iommu";
476 reg = <0x5d000000 0x80>;
477 interrupts = <28>;
478 ti,hwmods = "mmu_iva";
479 status = "disabled";
480 };
482 wdt2: wdt@48314000 {
483 compatible = "ti,omap3-wdt";
484 reg = <0x48314000 0x80>;
485 ti,hwmods = "wd_timer2";
486 };
488 mcbsp1: mcbsp@48074000 {
489 compatible = "ti,omap3-mcbsp";
490 reg = <0x48074000 0xff>;
491 reg-names = "mpu";
492 interrupts = <16>, /* OCP compliant interrupt */
493 <59>, /* TX interrupt */
494 <60>; /* RX interrupt */
495 interrupt-names = "common", "tx", "rx";
496 ti,buffer-size = <128>;
497 ti,hwmods = "mcbsp1";
498 dmas = <&sdma 31>,
499 <&sdma 32>;
500 dma-names = "tx", "rx";
501 clocks = <&mcbsp1_fck>;
502 clock-names = "fck";
503 status = "disabled";
504 };
506 /* Likely needs to be tagged disabled on HS devices */
507 rng_target: target-module@480a0000 {
508 compatible = "ti,sysc-omap2", "ti,sysc";
509 reg = <0x480a003c 0x4>,
510 <0x480a0040 0x4>,
511 <0x480a0044 0x4>;
512 reg-names = "rev", "sysc", "syss";
513 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
514 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
515 <SYSC_IDLE_NO>;
516 ti,syss-mask = <1>;
517 clocks = <&rng_ick>;
518 clock-names = "ick";
519 #address-cells = <1>;
520 #size-cells = <1>;
521 ranges = <0 0x480a0000 0x2000>;
523 rng: rng@0 {
524 compatible = "ti,omap2-rng";
525 reg = <0x0 0x2000>;
526 interrupts = <52>;
527 };
528 };
530 mcbsp2: mcbsp@49022000 {
531 compatible = "ti,omap3-mcbsp";
532 reg = <0x49022000 0xff>,
533 <0x49028000 0xff>;
534 reg-names = "mpu", "sidetone";
535 interrupts = <17>, /* OCP compliant interrupt */
536 <62>, /* TX interrupt */
537 <63>, /* RX interrupt */
538 <4>; /* Sidetone */
539 interrupt-names = "common", "tx", "rx", "sidetone";
540 ti,buffer-size = <1280>;
541 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
542 dmas = <&sdma 33>,
543 <&sdma 34>;
544 dma-names = "tx", "rx";
545 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
546 clock-names = "fck", "ick";
547 status = "disabled";
548 };
550 mcbsp3: mcbsp@49024000 {
551 compatible = "ti,omap3-mcbsp";
552 reg = <0x49024000 0xff>,
553 <0x4902a000 0xff>;
554 reg-names = "mpu", "sidetone";
555 interrupts = <22>, /* OCP compliant interrupt */
556 <89>, /* TX interrupt */
557 <90>, /* RX interrupt */
558 <5>; /* Sidetone */
559 interrupt-names = "common", "tx", "rx", "sidetone";
560 ti,buffer-size = <128>;
561 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
562 dmas = <&sdma 17>,
563 <&sdma 18>;
564 dma-names = "tx", "rx";
565 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
566 clock-names = "fck", "ick";
567 status = "disabled";
568 };
570 mcbsp4: mcbsp@49026000 {
571 compatible = "ti,omap3-mcbsp";
572 reg = <0x49026000 0xff>;
573 reg-names = "mpu";
574 interrupts = <23>, /* OCP compliant interrupt */
575 <54>, /* TX interrupt */
576 <55>; /* RX interrupt */
577 interrupt-names = "common", "tx", "rx";
578 ti,buffer-size = <128>;
579 ti,hwmods = "mcbsp4";
580 dmas = <&sdma 19>,
581 <&sdma 20>;
582 dma-names = "tx", "rx";
583 clocks = <&mcbsp4_fck>;
584 clock-names = "fck";
585 #sound-dai-cells = <0>;
586 status = "disabled";
587 };
589 mcbsp5: mcbsp@48096000 {
590 compatible = "ti,omap3-mcbsp";
591 reg = <0x48096000 0xff>;
592 reg-names = "mpu";
593 interrupts = <27>, /* OCP compliant interrupt */
594 <81>, /* TX interrupt */
595 <82>; /* RX interrupt */
596 interrupt-names = "common", "tx", "rx";
597 ti,buffer-size = <128>;
598 ti,hwmods = "mcbsp5";
599 dmas = <&sdma 21>,
600 <&sdma 22>;
601 dma-names = "tx", "rx";
602 clocks = <&mcbsp5_fck>;
603 clock-names = "fck";
604 status = "disabled";
605 };
607 sham: sham@480c3000 {
608 compatible = "ti,omap3-sham";
609 ti,hwmods = "sham";
610 reg = <0x480c3000 0x64>;
611 interrupts = <49>;
612 dmas = <&sdma 69>;
613 dma-names = "rx";
614 };
616 timer1: timer@48318000 {
617 compatible = "ti,omap3430-timer";
618 reg = <0x48318000 0x400>;
619 interrupts = <37>;
620 ti,hwmods = "timer1";
621 ti,timer-alwon;
622 };
624 timer2: timer@49032000 {
625 compatible = "ti,omap3430-timer";
626 reg = <0x49032000 0x400>;
627 interrupts = <38>;
628 ti,hwmods = "timer2";
629 };
631 timer3: timer@49034000 {
632 compatible = "ti,omap3430-timer";
633 reg = <0x49034000 0x400>;
634 interrupts = <39>;
635 ti,hwmods = "timer3";
636 };
638 timer4: timer@49036000 {
639 compatible = "ti,omap3430-timer";
640 reg = <0x49036000 0x400>;
641 interrupts = <40>;
642 ti,hwmods = "timer4";
643 };
645 timer5: timer@49038000 {
646 compatible = "ti,omap3430-timer";
647 reg = <0x49038000 0x400>;
648 interrupts = <41>;
649 ti,hwmods = "timer5";
650 ti,timer-dsp;
651 };
653 timer6: timer@4903a000 {
654 compatible = "ti,omap3430-timer";
655 reg = <0x4903a000 0x400>;
656 interrupts = <42>;
657 ti,hwmods = "timer6";
658 ti,timer-dsp;
659 };
661 timer7: timer@4903c000 {
662 compatible = "ti,omap3430-timer";
663 reg = <0x4903c000 0x400>;
664 interrupts = <43>;
665 ti,hwmods = "timer7";
666 ti,timer-dsp;
667 };
669 timer8: timer@4903e000 {
670 compatible = "ti,omap3430-timer";
671 reg = <0x4903e000 0x400>;
672 interrupts = <44>;
673 ti,hwmods = "timer8";
674 ti,timer-pwm;
675 ti,timer-dsp;
676 };
678 timer9: timer@49040000 {
679 compatible = "ti,omap3430-timer";
680 reg = <0x49040000 0x400>;
681 interrupts = <45>;
682 ti,hwmods = "timer9";
683 ti,timer-pwm;
684 };
686 timer10: timer@48086000 {
687 compatible = "ti,omap3430-timer";
688 reg = <0x48086000 0x400>;
689 interrupts = <46>;
690 ti,hwmods = "timer10";
691 ti,timer-pwm;
692 };
694 timer11: timer@48088000 {
695 compatible = "ti,omap3430-timer";
696 reg = <0x48088000 0x400>;
697 interrupts = <47>;
698 ti,hwmods = "timer11";
699 ti,timer-pwm;
700 };
702 timer12: timer@48304000 {
703 compatible = "ti,omap3430-timer";
704 reg = <0x48304000 0x400>;
705 interrupts = <95>;
706 ti,hwmods = "timer12";
707 ti,timer-alwon;
708 ti,timer-secure;
709 };
711 usbhstll: usbhstll@48062000 {
712 compatible = "ti,usbhs-tll";
713 reg = <0x48062000 0x1000>;
714 interrupts = <78>;
715 ti,hwmods = "usb_tll_hs";
716 };
718 usbhshost: usbhshost@48064000 {
719 compatible = "ti,usbhs-host";
720 reg = <0x48064000 0x400>;
721 ti,hwmods = "usb_host_hs";
722 #address-cells = <1>;
723 #size-cells = <1>;
724 ranges;
726 usbhsohci: ohci@48064400 {
727 compatible = "ti,ohci-omap3";
728 reg = <0x48064400 0x400>;
729 interrupts = <76>;
730 remote-wakeup-connected;
731 };
733 usbhsehci: ehci@48064800 {
734 compatible = "ti,ehci-omap";
735 reg = <0x48064800 0x400>;
736 interrupts = <77>;
737 };
738 };
740 gpmc: gpmc@6e000000 {
741 compatible = "ti,omap3430-gpmc";
742 ti,hwmods = "gpmc";
743 reg = <0x6e000000 0x02d0>;
744 interrupts = <20>;
745 dmas = <&sdma 4>;
746 dma-names = "rxtx";
747 gpmc,num-cs = <8>;
748 gpmc,num-waitpins = <4>;
749 #address-cells = <2>;
750 #size-cells = <1>;
751 interrupt-controller;
752 #interrupt-cells = <2>;
753 gpio-controller;
754 #gpio-cells = <2>;
755 };
757 usb_otg_hs: usb_otg_hs@480ab000 {
758 compatible = "ti,omap3-musb";
759 reg = <0x480ab000 0x1000>;
760 interrupts = <92>, <93>;
761 interrupt-names = "mc", "dma";
762 ti,hwmods = "usb_otg_hs";
763 multipoint = <1>;
764 num-eps = <16>;
765 ram-bits = <12>;
766 };
768 dss: dss@48050000 {
769 compatible = "ti,omap3-dss";
770 reg = <0x48050000 0x200>;
771 status = "disabled";
772 ti,hwmods = "dss_core";
773 clocks = <&dss1_alwon_fck>;
774 clock-names = "fck";
775 #address-cells = <1>;
776 #size-cells = <1>;
777 ranges;
779 dispc@48050400 {
780 compatible = "ti,omap3-dispc";
781 reg = <0x48050400 0x400>;
782 interrupts = <25>;
783 ti,hwmods = "dss_dispc";
784 clocks = <&dss1_alwon_fck>;
785 clock-names = "fck";
786 };
788 dsi: encoder@4804fc00 {
789 compatible = "ti,omap3-dsi";
790 reg = <0x4804fc00 0x200>,
791 <0x4804fe00 0x40>,
792 <0x4804ff00 0x20>;
793 reg-names = "proto", "phy", "pll";
794 interrupts = <25>;
795 status = "disabled";
796 ti,hwmods = "dss_dsi1";
797 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
798 clock-names = "fck", "sys_clk";
799 };
801 rfbi: encoder@48050800 {
802 compatible = "ti,omap3-rfbi";
803 reg = <0x48050800 0x100>;
804 status = "disabled";
805 ti,hwmods = "dss_rfbi";
806 clocks = <&dss1_alwon_fck>, <&dss_ick>;
807 clock-names = "fck", "ick";
808 };
810 venc: encoder@48050c00 {
811 compatible = "ti,omap3-venc";
812 reg = <0x48050c00 0x100>;
813 status = "disabled";
814 ti,hwmods = "dss_venc";
815 clocks = <&dss_tv_fck>;
816 clock-names = "fck";
817 };
818 };
820 ssi: ssi-controller@48058000 {
821 compatible = "ti,omap3-ssi";
822 ti,hwmods = "ssi";
824 status = "disabled";
826 reg = <0x48058000 0x1000>,
827 <0x48059000 0x1000>;
828 reg-names = "sys",
829 "gdd";
831 interrupts = <71>;
832 interrupt-names = "gdd_mpu";
834 #address-cells = <1>;
835 #size-cells = <1>;
836 ranges;
838 ssi_port1: ssi-port@4805a000 {
839 compatible = "ti,omap3-ssi-port";
841 reg = <0x4805a000 0x800>,
842 <0x4805a800 0x800>;
843 reg-names = "tx",
844 "rx";
846 interrupts = <67>,
847 <68>;
848 };
850 ssi_port2: ssi-port@4805b000 {
851 compatible = "ti,omap3-ssi-port";
853 reg = <0x4805b000 0x800>,
854 <0x4805b800 0x800>;
855 reg-names = "tx",
856 "rx";
858 interrupts = <69>,
859 <70>;
860 };
861 };
862 };
863 };
865 /include/ "omap3xxx-clocks.dtsi"