| blob | 6c892fc9d72628f1bf057d0d189cd8304f3ea6cc |
1 &l4_abe { /* 0x40100000 */
2 compatible = "ti,omap4-l4-abe", "simple-bus";
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
5 reg-names = "la", "ap";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
9 <0x49000000 0x49000000 0x100000>;
10 segment@0 { /* 0x40100000 */
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges =
15 /* CPU to L4 ABE mapping */
16 <0x00000000 0x00000000 0x000400>, /* ap 0 */
17 <0x00000400 0x00000400 0x000400>, /* ap 1 */
18 <0x00022000 0x00022000 0x001000>, /* ap 2 */
19 <0x00023000 0x00023000 0x001000>, /* ap 3 */
20 <0x00024000 0x00024000 0x001000>, /* ap 4 */
21 <0x00025000 0x00025000 0x001000>, /* ap 5 */
22 <0x00026000 0x00026000 0x001000>, /* ap 6 */
23 <0x00027000 0x00027000 0x001000>, /* ap 7 */
24 <0x00028000 0x00028000 0x001000>, /* ap 8 */
25 <0x00029000 0x00029000 0x001000>, /* ap 9 */
26 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
27 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
28 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
29 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
30 <0x00030000 0x00030000 0x001000>, /* ap 14 */
31 <0x00031000 0x00031000 0x001000>, /* ap 15 */
32 <0x00032000 0x00032000 0x001000>, /* ap 16 */
33 <0x00033000 0x00033000 0x001000>, /* ap 17 */
34 <0x00038000 0x00038000 0x001000>, /* ap 18 */
35 <0x00039000 0x00039000 0x001000>, /* ap 19 */
36 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
37 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
38 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
39 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
40 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
41 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
42 <0x00080000 0x00080000 0x010000>, /* ap 26 */
43 <0x00080000 0x00080000 0x001000>, /* ap 27 */
44 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
45 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
46 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
47 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
48 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
49 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
51 /* L3 to L4 ABE mapping */
52 <0x49000000 0x49000000 0x000400>, /* ap 0 */
53 <0x49000400 0x49000400 0x000400>, /* ap 1 */
54 <0x49022000 0x49022000 0x001000>, /* ap 2 */
55 <0x49023000 0x49023000 0x001000>, /* ap 3 */
56 <0x49024000 0x49024000 0x001000>, /* ap 4 */
57 <0x49025000 0x49025000 0x001000>, /* ap 5 */
58 <0x49026000 0x49026000 0x001000>, /* ap 6 */
59 <0x49027000 0x49027000 0x001000>, /* ap 7 */
60 <0x49028000 0x49028000 0x001000>, /* ap 8 */
61 <0x49029000 0x49029000 0x001000>, /* ap 9 */
62 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
63 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
64 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
65 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
66 <0x49030000 0x49030000 0x001000>, /* ap 14 */
67 <0x49031000 0x49031000 0x001000>, /* ap 15 */
68 <0x49032000 0x49032000 0x001000>, /* ap 16 */
69 <0x49033000 0x49033000 0x001000>, /* ap 17 */
70 <0x49038000 0x49038000 0x001000>, /* ap 18 */
71 <0x49039000 0x49039000 0x001000>, /* ap 19 */
72 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
73 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
74 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
75 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
76 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
77 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
78 <0x49080000 0x49080000 0x010000>, /* ap 26 */
79 <0x49080000 0x49080000 0x001000>, /* ap 27 */
80 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
81 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
82 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
83 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
84 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
85 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
87 target-module@22000 { /* 0x40122000, ap 2 02.0 */
88 compatible = "ti,sysc-omap2", "ti,sysc";
89 reg = <0x2208c 0x4>;
90 reg-names = "sysc";
91 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
92 SYSC_OMAP2_ENAWAKEUP |
93 SYSC_OMAP2_SOFTRESET)>;
94 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
95 <SYSC_IDLE_NO>,
96 <SYSC_IDLE_SMART>;
97 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
98 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
99 clock-names = "fck";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0x0 0x22000 0x1000>,
103 <0x49022000 0x49022000 0x1000>;
105 mcbsp1: mcbsp@0 {
106 compatible = "ti,omap4-mcbsp";
107 reg = <0x0 0xff>, /* MPU private access */
108 <0x49022000 0xff>; /* L3 Interconnect */
109 reg-names = "mpu", "dma";
110 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-names = "common";
112 ti,buffer-size = <128>;
113 dmas = <&sdma 33>,
114 <&sdma 34>;
115 dma-names = "tx", "rx";
116 status = "disabled";
117 };
118 };
120 target-module@24000 { /* 0x40124000, ap 4 04.0 */
121 compatible = "ti,sysc-omap2", "ti,sysc";
122 reg = <0x2408c 0x4>;
123 reg-names = "sysc";
124 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
125 SYSC_OMAP2_ENAWAKEUP |
126 SYSC_OMAP2_SOFTRESET)>;
127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
128 <SYSC_IDLE_NO>,
129 <SYSC_IDLE_SMART>;
130 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
131 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
132 clock-names = "fck";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0x0 0x24000 0x1000>,
136 <0x49024000 0x49024000 0x1000>;
138 mcbsp2: mcbsp@0 {
139 compatible = "ti,omap4-mcbsp";
140 reg = <0x0 0xff>, /* MPU private access */
141 <0x49024000 0xff>; /* L3 Interconnect */
142 reg-names = "mpu", "dma";
143 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
144 interrupt-names = "common";
145 ti,buffer-size = <128>;
146 dmas = <&sdma 17>,
147 <&sdma 18>;
148 dma-names = "tx", "rx";
149 status = "disabled";
150 };
151 };
153 target-module@26000 { /* 0x40126000, ap 6 06.0 */
154 compatible = "ti,sysc-omap2", "ti,sysc";
155 reg = <0x2608c 0x4>;
156 reg-names = "sysc";
157 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
158 SYSC_OMAP2_ENAWAKEUP |
159 SYSC_OMAP2_SOFTRESET)>;
160 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
161 <SYSC_IDLE_NO>,
162 <SYSC_IDLE_SMART>;
163 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
164 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
165 clock-names = "fck";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0x0 0x26000 0x1000>,
169 <0x49026000 0x49026000 0x1000>;
171 mcbsp3: mcbsp@0 {
172 compatible = "ti,omap4-mcbsp";
173 reg = <0x0 0xff>, /* MPU private access */
174 <0x49026000 0xff>; /* L3 Interconnect */
175 reg-names = "mpu", "dma";
176 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "common";
178 ti,buffer-size = <128>;
179 dmas = <&sdma 19>,
180 <&sdma 20>;
181 dma-names = "tx", "rx";
182 status = "disabled";
183 };
184 };
186 target-module@28000 { /* 0x40128000, ap 8 08.0 */
187 compatible = "ti,sysc-mcasp", "ti,sysc";
188 reg = <0x28000 0x4>,
189 <0x28004 0x4>;
190 reg-names = "rev", "sysc";
191 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
192 <SYSC_IDLE_NO>,
193 <SYSC_IDLE_SMART>,
194 <SYSC_IDLE_SMART_WKUP>;
195 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
196 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
197 clock-names = "fck";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0x0 0x28000 0x1000>,
201 <0x49028000 0x49028000 0x1000>;
203 /*
204 * Child device unsupported by davinci-mcasp. At least
205 * RX path is disabled for omap4, and only DIT mode
206 * works with no I2S. See also old Android kernel
207 * omap-mcasp driver for more information.
208 */
209 };
211 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
212 compatible = "ti,sysc";
213 status = "disabled";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges = <0x0 0x2a000 0x1000>,
217 <0x4902a000 0x4902a000 0x1000>;
218 };
220 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
221 compatible = "ti,sysc-omap4", "ti,sysc";
222 ti,hwmods = "dmic";
223 reg = <0x2e000 0x4>,
224 <0x2e010 0x4>;
225 reg-names = "rev", "sysc";
226 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
227 SYSC_OMAP4_SOFTRESET)>;
228 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
229 <SYSC_IDLE_NO>,
230 <SYSC_IDLE_SMART>,
231 <SYSC_IDLE_SMART_WKUP>;
232 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
233 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
234 clock-names = "fck";
235 #address-cells = <1>;
236 #size-cells = <1>;
237 ranges = <0x0 0x2e000 0x1000>,
238 <0x4902e000 0x4902e000 0x1000>;
240 dmic: dmic@0 {
241 compatible = "ti,omap4-dmic";
242 reg = <0x0 0x7f>, /* MPU private access */
243 <0x4902e000 0x7f>; /* L3 Interconnect */
244 reg-names = "mpu", "dma";
245 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
246 dmas = <&sdma 67>;
247 dma-names = "up_link";
248 status = "disabled";
249 };
250 };
252 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
253 compatible = "ti,sysc-omap2", "ti,sysc";
254 reg = <0x30000 0x4>,
255 <0x30010 0x4>,
256 <0x30014 0x4>;
257 reg-names = "rev", "sysc", "syss";
258 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
259 SYSC_OMAP2_SOFTRESET)>;
260 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
261 <SYSC_IDLE_NO>,
262 <SYSC_IDLE_SMART>,
263 <SYSC_IDLE_SMART_WKUP>;
264 ti,syss-mask = <1>;
265 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
266 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
267 clock-names = "fck";
268 #address-cells = <1>;
269 #size-cells = <1>;
270 ranges = <0x0 0x30000 0x1000>,
271 <0x49030000 0x49030000 0x1000>;
273 wdt3: wdt@0 {
274 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
275 reg = <0x0 0x80>;
276 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
277 };
278 };
280 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
281 compatible = "ti,sysc-omap4", "ti,sysc";
282 ti,hwmods = "mcpdm";
283 reg = <0x32000 0x4>,
284 <0x32010 0x4>;
285 reg-names = "rev", "sysc";
286 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
287 SYSC_OMAP4_SOFTRESET)>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
289 <SYSC_IDLE_NO>,
290 <SYSC_IDLE_SMART>,
291 <SYSC_IDLE_SMART_WKUP>;
292 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
293 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
294 clock-names = "fck";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges = <0x0 0x32000 0x1000>,
298 <0x49032000 0x49032000 0x1000>;
300 /* Must be only enabled for boards with pdmclk wired */
301 status = "disabled";
303 mcpdm: mcpdm@0 {
304 compatible = "ti,omap4-mcpdm";
305 reg = <0x0 0x7f>, /* MPU private access */
306 <0x49032000 0x7f>; /* L3 Interconnect */
307 reg-names = "mpu", "dma";
308 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
309 dmas = <&sdma 65>,
310 <&sdma 66>;
311 dma-names = "up_link", "dn_link";
312 };
313 };
315 target-module@38000 { /* 0x40138000, ap 18 12.0 */
316 compatible = "ti,sysc-omap4-timer", "ti,sysc";
317 ti,hwmods = "timer5";
318 reg = <0x38000 0x4>,
319 <0x38010 0x4>;
320 reg-names = "rev", "sysc";
321 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
322 SYSC_OMAP4_SOFTRESET)>;
323 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
324 <SYSC_IDLE_NO>,
325 <SYSC_IDLE_SMART>,
326 <SYSC_IDLE_SMART_WKUP>;
327 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
328 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
329 clock-names = "fck";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 ranges = <0x0 0x38000 0x1000>,
333 <0x49038000 0x49038000 0x1000>;
335 timer5: timer@0 {
336 compatible = "ti,omap4430-timer";
337 reg = <0x00000000 0x80>,
338 <0x49038000 0x80>;
339 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
340 clock-names = "fck";
341 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
342 ti,timer-dsp;
343 };
344 };
346 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
347 compatible = "ti,sysc-omap4-timer", "ti,sysc";
348 ti,hwmods = "timer6";
349 reg = <0x3a000 0x4>,
350 <0x3a010 0x4>;
351 reg-names = "rev", "sysc";
352 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
353 SYSC_OMAP4_SOFTRESET)>;
354 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
355 <SYSC_IDLE_NO>,
356 <SYSC_IDLE_SMART>,
357 <SYSC_IDLE_SMART_WKUP>;
358 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
359 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
360 clock-names = "fck";
361 #address-cells = <1>;
362 #size-cells = <1>;
363 ranges = <0x0 0x3a000 0x1000>,
364 <0x4903a000 0x4903a000 0x1000>;
366 timer6: timer@0 {
367 compatible = "ti,omap4430-timer";
368 reg = <0x00000000 0x80>,
369 <0x4903a000 0x80>;
370 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
371 clock-names = "fck";
372 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
373 ti,timer-dsp;
374 };
375 };
377 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
378 compatible = "ti,sysc-omap4-timer", "ti,sysc";
379 ti,hwmods = "timer7";
380 reg = <0x3c000 0x4>,
381 <0x3c010 0x4>;
382 reg-names = "rev", "sysc";
383 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
384 SYSC_OMAP4_SOFTRESET)>;
385 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
386 <SYSC_IDLE_NO>,
387 <SYSC_IDLE_SMART>,
388 <SYSC_IDLE_SMART_WKUP>;
389 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
390 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
391 clock-names = "fck";
392 #address-cells = <1>;
393 #size-cells = <1>;
394 ranges = <0x0 0x3c000 0x1000>,
395 <0x4903c000 0x4903c000 0x1000>;
397 timer7: timer@0 {
398 compatible = "ti,omap4430-timer";
399 reg = <0x00000000 0x80>,
400 <0x4903c000 0x80>;
401 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
402 clock-names = "fck";
403 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
404 ti,timer-dsp;
405 };
406 };
408 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
409 compatible = "ti,sysc-omap4-timer", "ti,sysc";
410 ti,hwmods = "timer8";
411 reg = <0x3e000 0x4>,
412 <0x3e010 0x4>;
413 reg-names = "rev", "sysc";
414 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
415 SYSC_OMAP4_SOFTRESET)>;
416 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
417 <SYSC_IDLE_NO>,
418 <SYSC_IDLE_SMART>,
419 <SYSC_IDLE_SMART_WKUP>;
420 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
421 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
422 clock-names = "fck";
423 #address-cells = <1>;
424 #size-cells = <1>;
425 ranges = <0x0 0x3e000 0x1000>,
426 <0x4903e000 0x4903e000 0x1000>;
428 timer8: timer@0 {
429 compatible = "ti,omap4430-timer";
430 reg = <0x00000000 0x80>,
431 <0x4903e000 0x80>;
432 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
433 clock-names = "fck";
434 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
435 ti,timer-pwm;
436 ti,timer-dsp;
437 };
438 };
440 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
441 compatible = "ti,sysc";
442 status = "disabled";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges = <0x0 0x80000 0x10000>,
446 <0x49080000 0x49080000 0x10000>;
447 };
449 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
450 compatible = "ti,sysc";
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <1>;
454 ranges = <0x0 0xa0000 0x10000>,
455 <0x490a0000 0x490a0000 0x10000>;
456 };
458 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
459 compatible = "ti,sysc";
460 status = "disabled";
461 #address-cells = <1>;
462 #size-cells = <1>;
463 ranges = <0x0 0xc0000 0x10000>,
464 <0x490c0000 0x490c0000 0x10000>;
465 };
467 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
468 compatible = "ti,sysc-omap4", "ti,sysc";
469 ti,hwmods = "aess";
470 reg = <0xf1000 0x4>,
471 <0xf1010 0x4>;
472 reg-names = "rev", "sysc";
473 ti,sysc-midle = <SYSC_IDLE_FORCE>,
474 <SYSC_IDLE_NO>,
475 <SYSC_IDLE_SMART>,
476 <SYSC_IDLE_SMART_WKUP>;
477 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
478 <SYSC_IDLE_NO>,
479 <SYSC_IDLE_SMART>;
480 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
481 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
482 clock-names = "fck";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges = <0x0 0xf1000 0x1000>,
486 <0x490f1000 0x490f1000 0x1000>;
488 /*
489 * No child device binding or driver in mainline.
490 * See Android tree and related upstreaming efforts
491 * for the old driver.
492 */
493 };
494 };
495 };