1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
36 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
41 clocks = <&dpll_mpu_ck>;
44 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
55 * Note that 4430 needs cross trigger interface (CTI) supported
56 * before we can configure the interrupts. This means sampling
57 * events are not supported for pmu. Note that 4460 does not use
58 * CTI, see also 4460.dtsi.
61 compatible = "arm,cortex-a9-pmu";
62 ti,hwmods = "debugss";
65 gic: interrupt-controller@48241000 {
66 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
69 reg = <0x48241000 0x1000>,
71 interrupt-parent = <&gic>;
74 L2: l2-cache-controller@48242000 {
75 compatible = "arm,pl310-cache";
76 reg = <0x48242000 0x1000>;
81 local-timer@48240600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 clocks = <&mpu_periphclk>;
84 reg = <0x48240600 0x20>;
85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
86 interrupt-parent = <&gic>;
89 wakeupgen: interrupt-controller@48281000 {
90 compatible = "ti,omap4-wugen-mpu";
92 #interrupt-cells = <3>;
93 reg = <0x48281000 0x1000>;
94 interrupt-parent = <&gic>;
98 * The soc node represents the soc top level view. It is used for IPs
99 * that are not memory mapped in the MPU view or for the MPU itself.
102 compatible = "ti,omap-infra";
104 compatible = "ti,omap4-mpu";
110 compatible = "ti,omap3-c64";
115 compatible = "ti,ivahd";
121 * XXX: Use a flat representation of the OMAP4 interconnect.
122 * The real OMAP interconnect network is quite complex.
123 * Since it will not bring real advantage to represent that in DT for
124 * the moment, just use a fake OCP bus entry to represent the whole bus
128 compatible = "ti,omap4-l3-noc", "simple-bus";
129 #address-cells = <1>;
132 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
133 reg = <0x44000000 0x1000>,
136 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
139 l4_wkup: interconnect@4a300000 {
142 l4_cfg: interconnect@4a000000 {
145 l4_per: interconnect@48000000 {
148 l4_abe: interconnect@40100000 {
151 ocmcram: sram@40304000 {
152 compatible = "mmio-sram";
153 reg = <0x40304000 0xa000>; /* 40k */
156 gpmc: gpmc@50000000 {
157 compatible = "ti,omap4430-gpmc";
158 reg = <0x50000000 0x1000>;
159 #address-cells = <2>;
161 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
165 gpmc,num-waitpins = <4>;
168 clocks = <&l3_div_ck>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
176 mmu_dsp: mmu@4a066000 {
177 compatible = "ti,omap4-iommu";
178 reg = <0x4a066000 0x100>;
179 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
180 ti,hwmods = "mmu_dsp";
184 target-module@52000000 {
185 compatible = "ti,sysc-omap4", "ti,sysc";
187 reg = <0x52000000 0x4>,
189 reg-names = "rev", "sysc";
190 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
191 ti,sysc-midle = <SYSC_IDLE_FORCE>,
194 <SYSC_IDLE_SMART_WKUP>;
195 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
198 <SYSC_IDLE_SMART_WKUP>;
199 ti,sysc-delay-us = <2>;
200 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
202 #address-cells = <1>;
204 ranges = <0 0x52000000 0x1000000>;
206 /* No child device binding, driver in staging */
209 mmu_ipu: mmu@55082000 {
210 compatible = "ti,omap4-iommu";
211 reg = <0x55082000 0x100>;
212 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
213 ti,hwmods = "mmu_ipu";
215 ti,iommu-bus-err-back;
217 target-module@4012c000 {
218 compatible = "ti,sysc-omap4", "ti,sysc";
219 ti,hwmods = "slimbus1";
220 reg = <0x4012c000 0x4>,
222 reg-names = "rev", "sysc";
223 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
224 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
227 <SYSC_IDLE_SMART_WKUP>;
228 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
230 #address-cells = <1>;
232 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
233 <0x4902c000 0x4902c000 0x1000>; /* L3 */
235 /* No child device binding or driver in mainline */
239 compatible = "ti,omap4-dmm";
240 reg = <0x4e000000 0x800>;
241 interrupts = <0 113 0x4>;
245 emif1: emif@4c000000 {
246 compatible = "ti,emif-4d";
247 reg = <0x4c000000 0x100>;
248 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
252 hw-caps-read-idle-ctrl;
253 hw-caps-ll-interface;
257 emif2: emif@4d000000 {
258 compatible = "ti,emif-4d";
259 reg = <0x4d000000 0x100>;
260 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
264 hw-caps-read-idle-ctrl;
265 hw-caps-ll-interface;
270 compatible = "ti,omap4-aes";
272 reg = <0x4b501000 0xa0>;
273 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
274 dmas = <&sdma 111>, <&sdma 110>;
275 dma-names = "tx", "rx";
279 compatible = "ti,omap4-aes";
281 reg = <0x4b701000 0xa0>;
282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
283 dmas = <&sdma 114>, <&sdma 113>;
284 dma-names = "tx", "rx";
288 compatible = "ti,omap4-des";
290 reg = <0x480a5000 0xa0>;
291 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
292 dmas = <&sdma 117>, <&sdma 116>;
293 dma-names = "tx", "rx";
296 sham: sham@4b100000 {
297 compatible = "ti,omap4-sham";
299 reg = <0x4b100000 0x300>;
300 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
305 abb_mpu: regulator-abb-mpu {
306 compatible = "ti,abb-v2";
307 regulator-name = "abb_mpu";
308 #address-cells = <0>;
310 ti,tranxdone-status-mask = <0x80>;
311 clocks = <&sys_clkin_ck>;
312 ti,settling-time = <50>;
313 ti,clock-cycles = <16>;
318 abb_iva: regulator-abb-iva {
319 compatible = "ti,abb-v2";
320 regulator-name = "abb_iva";
321 #address-cells = <0>;
323 ti,tranxdone-status-mask = <0x80000000>;
324 clocks = <&sys_clkin_ck>;
325 ti,settling-time = <50>;
326 ti,clock-cycles = <16>;
331 target-module@56000000 {
332 compatible = "ti,sysc-omap4", "ti,sysc";
333 reg = <0x5600fe00 0x4>,
335 reg-names = "rev", "sysc";
336 ti,sysc-midle = <SYSC_IDLE_FORCE>,
339 <SYSC_IDLE_SMART_WKUP>;
340 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
343 <SYSC_IDLE_SMART_WKUP>;
344 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
346 #address-cells = <1>;
348 ranges = <0 0x56000000 0x2000000>;
351 * Closed source PowerVR driver, no child device
352 * binding or driver in mainline
357 compatible = "ti,omap4-dss";
358 reg = <0x58000000 0x80>;
360 ti,hwmods = "dss_core";
361 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
363 #address-cells = <1>;
368 compatible = "ti,omap4-dispc";
369 reg = <0x58001000 0x1000>;
370 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "dss_dispc";
372 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
376 rfbi: encoder@58002000 {
377 compatible = "ti,omap4-rfbi";
378 reg = <0x58002000 0x1000>;
380 ti,hwmods = "dss_rfbi";
381 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
382 clock-names = "fck", "ick";
385 venc: encoder@58003000 {
386 compatible = "ti,omap4-venc";
387 reg = <0x58003000 0x1000>;
389 ti,hwmods = "dss_venc";
390 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
394 dsi1: encoder@58004000 {
395 compatible = "ti,omap4-dsi";
396 reg = <0x58004000 0x200>,
399 reg-names = "proto", "phy", "pll";
400 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
402 ti,hwmods = "dss_dsi1";
403 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
404 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
405 clock-names = "fck", "sys_clk";
408 dsi2: encoder@58005000 {
409 compatible = "ti,omap4-dsi";
410 reg = <0x58005000 0x200>,
413 reg-names = "proto", "phy", "pll";
414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "dss_dsi2";
417 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
418 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
419 clock-names = "fck", "sys_clk";
422 hdmi: encoder@58006000 {
423 compatible = "ti,omap4-hdmi";
424 reg = <0x58006000 0x200>,
428 reg-names = "wp", "pll", "phy", "core";
429 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
431 ti,hwmods = "dss_hdmi";
432 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
433 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
434 clock-names = "fck", "sys_clk";
436 dma-names = "audio_tx";
442 #include "omap4-l4.dtsi"
443 #include "omap4-l4-abe.dtsi"
444 #include "omap44xx-clocks.dtsi"
448 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
454 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
460 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
465 prm_device: prm@1b00 {
466 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";