| blob | 25aacf1ba7084256dfea162f6beed43a9a0ce1bd |
1 &l4_cfg { /* 0x4a000000 */
2 compatible = "ti,omap5-l4-cfg", "simple-bus";
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
6 reg-names = "ap", "la", "ia0";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
15 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
17 segment@0 { /* 0x4a000000 */
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00001000 0x00001000 0x001000>, /* ap 1 */
23 <0x00000800 0x00000800 0x000800>, /* ap 2 */
24 <0x00002000 0x00002000 0x001000>, /* ap 3 */
25 <0x00003000 0x00003000 0x001000>, /* ap 4 */
26 <0x00004000 0x00004000 0x001000>, /* ap 5 */
27 <0x00005000 0x00005000 0x001000>, /* ap 6 */
28 <0x00056000 0x00056000 0x001000>, /* ap 7 */
29 <0x00057000 0x00057000 0x001000>, /* ap 8 */
30 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
31 <0x00058000 0x00058000 0x001000>, /* ap 10 */
32 <0x00062000 0x00062000 0x001000>, /* ap 11 */
33 <0x00063000 0x00063000 0x001000>, /* ap 12 */
34 <0x00008000 0x00008000 0x002000>, /* ap 21 */
35 <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
36 <0x00066000 0x00066000 0x001000>, /* ap 23 */
37 <0x00067000 0x00067000 0x001000>, /* ap 24 */
38 <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
39 <0x00060000 0x00060000 0x001000>, /* ap 70 */
40 <0x00064000 0x00064000 0x001000>, /* ap 71 */
41 <0x00065000 0x00065000 0x001000>, /* ap 72 */
42 <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
43 <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
44 <0x00070000 0x00070000 0x004000>, /* ap 79 */
45 <0x00074000 0x00074000 0x001000>, /* ap 80 */
46 <0x00075000 0x00075000 0x001000>, /* ap 81 */
47 <0x00076000 0x00076000 0x001000>, /* ap 82 */
48 <0x00020000 0x00020000 0x020000>, /* ap 109 */
49 <0x00040000 0x00040000 0x001000>, /* ap 110 */
50 <0x00059000 0x00059000 0x001000>; /* ap 111 */
52 target-module@2000 { /* 0x4a002000, ap 3 44.0 */
53 compatible = "ti,sysc-omap4", "ti,sysc";
54 reg = <0x2000 0x4>;
55 reg-names = "rev";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges = <0x0 0x2000 0x1000>;
60 scm_core: scm@0 {
61 compatible = "ti,omap5-scm-core", "simple-bus";
62 reg = <0x0 0x1000>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges = <0 0 0x800>;
67 scm_conf: scm_conf@0 {
68 compatible = "syscon";
69 reg = <0x0 0x800>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 };
73 };
75 scm_padconf_core: scm@800 {
76 compatible = "ti,omap5-scm-padconf-core",
77 "simple-bus";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x800 0x800>;
82 omap5_pmx_core: pinmux@40 {
83 compatible = "ti,omap5-padconf",
84 "pinctrl-single";
85 reg = <0x40 0x01b6>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88 #pinctrl-cells = <1>;
89 #interrupt-cells = <1>;
90 interrupt-controller;
91 pinctrl-single,register-width = <16>;
92 pinctrl-single,function-mask = <0x7fff>;
93 };
95 omap5_padconf_global: omap5_padconf_global@5a0 {
96 compatible = "syscon",
97 "simple-bus";
98 reg = <0x5a0 0xec>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x5a0 0xec>;
103 pbias_regulator: pbias_regulator@60 {
104 compatible = "ti,pbias-omap5", "ti,pbias-omap";
105 reg = <0x60 0x4>;
106 syscon = <&omap5_padconf_global>;
107 pbias_mmc_reg: pbias_mmc_omap5 {
108 regulator-name = "pbias_mmc_omap5";
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <3300000>;
111 };
112 };
113 };
114 };
115 };
117 target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
118 compatible = "ti,sysc-omap4", "ti,sysc";
119 reg = <0x4000 0x4>;
120 reg-names = "rev";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges = <0x0 0x4000 0x1000>;
125 cm_core_aon: cm_core_aon@0 {
126 compatible = "ti,omap5-cm-core-aon",
127 "simple-bus";
128 reg = <0x0 0x2000>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges = <0 0 0x1000>;
133 cm_core_aon_clocks: clocks {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 };
138 cm_core_aon_clockdomains: clockdomains {
139 };
140 };
141 };
143 target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
144 compatible = "ti,sysc-omap4", "ti,sysc";
145 reg = <0x8000 0x4>;
146 reg-names = "rev";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges = <0x0 0x8000 0x2000>;
151 cm_core: cm_core@0 {
152 compatible = "ti,omap5-cm-core", "simple-bus";
153 reg = <0x0 0x2000>;
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0 0 0x2000>;
158 cm_core_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
163 cm_core_clockdomains: clockdomains {
164 };
165 };
166 };
168 target-module@20000 { /* 0x4a020000, ap 109 08.0 */
169 compatible = "ti,sysc-omap4", "ti,sysc";
170 ti,hwmods = "usb_otg_ss";
171 reg = <0x20000 0x4>,
172 <0x20010 0x4>;
173 reg-names = "rev", "sysc";
174 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
175 ti,sysc-midle = <SYSC_IDLE_FORCE>,
176 <SYSC_IDLE_NO>,
177 <SYSC_IDLE_SMART>,
178 <SYSC_IDLE_SMART_WKUP>;
179 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
180 <SYSC_IDLE_NO>,
181 <SYSC_IDLE_SMART>,
182 <SYSC_IDLE_SMART_WKUP>;
183 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
184 clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
185 clock-names = "fck";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 ranges = <0x0 0x20000 0x20000>;
190 usb3: omap_dwc3@0 {
191 compatible = "ti,dwc3";
192 reg = <0x0 0x10000>;
193 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
195 #size-cells = <1>;
196 utmi-mode = <2>;
197 ranges = <0 0 0x20000>;
198 dwc3: dwc3@10000 {
199 compatible = "snps,dwc3";
200 reg = <0x10000 0x10000>;
201 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "peripheral",
205 "host",
206 "otg";
207 phys = <&usb2_phy>, <&usb3_phy>;
208 phy-names = "usb2-phy", "usb3-phy";
209 dr_mode = "peripheral";
210 };
211 };
212 };
214 target-module@56000 { /* 0x4a056000, ap 7 02.0 */
215 compatible = "ti,sysc-omap2", "ti,sysc";
216 ti,hwmods = "dma_system";
217 reg = <0x56000 0x4>,
218 <0x5602c 0x4>,
219 <0x56028 0x4>;
220 reg-names = "rev", "sysc", "syss";
221 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
222 SYSC_OMAP2_EMUFREE |
223 SYSC_OMAP2_SOFTRESET |
224 SYSC_OMAP2_AUTOIDLE)>;
225 ti,sysc-midle = <SYSC_IDLE_FORCE>,
226 <SYSC_IDLE_NO>,
227 <SYSC_IDLE_SMART>;
228 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
229 <SYSC_IDLE_NO>,
230 <SYSC_IDLE_SMART>;
231 ti,syss-mask = <1>;
232 /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
233 clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
234 clock-names = "fck";
235 #address-cells = <1>;
236 #size-cells = <1>;
237 ranges = <0x0 0x56000 0x1000>;
239 sdma: dma-controller@0 {
240 compatible = "ti,omap4430-sdma";
241 reg = <0x0 0x1000>;
242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
246 #dma-cells = <1>;
247 dma-channels = <32>;
248 dma-requests = <127>;
249 };
250 };
252 target-module@58000 { /* 0x4a058000, ap 10 06.0 */
253 compatible = "ti,sysc";
254 status = "disabled";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges = <0x00000000 0x00058000 0x00001000>,
258 <0x00001000 0x00059000 0x00001000>,
259 <0x00002000 0x0005a000 0x00001000>,
260 <0x00003000 0x0005b000 0x00001000>;
261 };
263 target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
264 compatible = "ti,sysc";
265 status = "disabled";
266 #address-cells = <1>;
267 #size-cells = <1>;
268 ranges = <0x0 0x5e000 0x2000>;
269 };
271 target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
272 compatible = "ti,sysc-omap2", "ti,sysc";
273 ti,hwmods = "usb_tll_hs";
274 reg = <0x62000 0x4>,
275 <0x62010 0x4>,
276 <0x62014 0x4>;
277 reg-names = "rev", "sysc", "syss";
278 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
279 SYSC_OMAP2_ENAWAKEUP |
280 SYSC_OMAP2_SOFTRESET |
281 SYSC_OMAP2_AUTOIDLE)>;
282 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
283 <SYSC_IDLE_NO>,
284 <SYSC_IDLE_SMART>;
285 ti,syss-mask = <1>;
286 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
287 clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
288 clock-names = "fck";
289 #address-cells = <1>;
290 #size-cells = <1>;
291 ranges = <0x0 0x62000 0x1000>;
293 usbhstll: usbhstll@0 {
294 compatible = "ti,usbhs-tll";
295 reg = <0x0 0x1000>;
296 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
297 };
298 };
300 target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
301 compatible = "ti,sysc-omap4", "ti,sysc";
302 ti,hwmods = "usb_host_hs";
303 reg = <0x64000 0x4>,
304 <0x64010 0x4>;
305 reg-names = "rev", "sysc";
306 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
307 ti,sysc-midle = <SYSC_IDLE_FORCE>,
308 <SYSC_IDLE_NO>,
309 <SYSC_IDLE_SMART>,
310 <SYSC_IDLE_SMART_WKUP>;
311 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
312 <SYSC_IDLE_NO>,
313 <SYSC_IDLE_SMART>,
314 <SYSC_IDLE_SMART_WKUP>;
315 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
316 clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
317 clock-names = "fck";
318 #address-cells = <1>;
319 #size-cells = <1>;
320 ranges = <0x0 0x64000 0x1000>;
322 usbhshost: usbhshost@0 {
323 compatible = "ti,usbhs-host";
324 reg = <0x0 0x800>;
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges = <0 0 0x1000>;
328 clocks = <&l3init_60m_fclk>,
329 <&xclk60mhsp1_ck>,
330 <&xclk60mhsp2_ck>;
331 clock-names = "refclk_60m_int",
332 "refclk_60m_ext_p1",
333 "refclk_60m_ext_p2";
335 usbhsohci: ohci@800 {
336 compatible = "ti,ohci-omap3";
337 reg = <0x800 0x400>;
338 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
339 remote-wakeup-connected;
340 };
342 usbhsehci: ehci@c00 {
343 compatible = "ti,ehci-omap";
344 reg = <0xc00 0x400>;
345 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
346 };
347 };
348 };
350 target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
351 compatible = "ti,sysc-omap2", "ti,sysc";
352 ti,hwmods = "mmu_dsp";
353 reg = <0x66000 0x4>,
354 <0x66010 0x4>,
355 <0x66014 0x4>;
356 reg-names = "rev", "sysc", "syss";
357 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
358 SYSC_OMAP2_SOFTRESET |
359 SYSC_OMAP2_AUTOIDLE)>;
360 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
361 <SYSC_IDLE_NO>,
362 <SYSC_IDLE_SMART>;
363 ti,syss-mask = <1>;
364 /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
365 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
366 clock-names = "fck";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0x0 0x66000 0x1000>;
371 /* mmu_dsp cannot be moved before reset driver */
372 status = "disabled";
373 };
375 target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
376 compatible = "ti,sysc";
377 status = "disabled";
378 #address-cells = <1>;
379 #size-cells = <1>;
380 ranges = <0x0 0x70000 0x4000>;
381 };
383 target-module@75000 { /* 0x4a075000, ap 81 32.0 */
384 compatible = "ti,sysc";
385 status = "disabled";
386 #address-cells = <1>;
387 #size-cells = <1>;
388 ranges = <0x0 0x75000 0x1000>;
389 };
390 };
392 segment@80000 { /* 0x4a080000 */
393 compatible = "simple-bus";
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
397 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
398 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
399 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
400 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
401 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
402 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
403 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
404 <0x00074000 0x000f4000 0x001000>, /* ap 25 */
405 <0x00075000 0x000f5000 0x001000>, /* ap 26 */
406 <0x00076000 0x000f6000 0x001000>, /* ap 27 */
407 <0x00077000 0x000f7000 0x001000>, /* ap 28 */
408 <0x00036000 0x000b6000 0x001000>, /* ap 65 */
409 <0x00037000 0x000b7000 0x001000>, /* ap 66 */
410 <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
411 <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
412 <0x00000000 0x00080000 0x004000>, /* ap 83 */
413 <0x00004000 0x00084000 0x001000>, /* ap 84 */
414 <0x00005000 0x00085000 0x001000>, /* ap 85 */
415 <0x00006000 0x00086000 0x001000>, /* ap 86 */
416 <0x00007000 0x00087000 0x001000>, /* ap 87 */
417 <0x00008000 0x00088000 0x001000>, /* ap 88 */
418 <0x00010000 0x00090000 0x004000>, /* ap 89 */
419 <0x00014000 0x00094000 0x001000>, /* ap 90 */
420 <0x00015000 0x00095000 0x001000>, /* ap 91 */
421 <0x00016000 0x00096000 0x001000>, /* ap 92 */
422 <0x00017000 0x00097000 0x001000>, /* ap 93 */
423 <0x00018000 0x00098000 0x001000>, /* ap 94 */
424 <0x00020000 0x000a0000 0x004000>, /* ap 95 */
425 <0x00024000 0x000a4000 0x001000>, /* ap 96 */
426 <0x00025000 0x000a5000 0x001000>, /* ap 97 */
427 <0x00026000 0x000a6000 0x001000>, /* ap 98 */
428 <0x00027000 0x000a7000 0x001000>, /* ap 99 */
429 <0x00028000 0x000a8000 0x001000>; /* ap 100 */
431 target-module@0 { /* 0x4a080000, ap 83 28.0 */
432 compatible = "ti,sysc-omap2", "ti,sysc";
433 ti,hwmods = "ocp2scp1";
434 reg = <0x0 0x4>,
435 <0x10 0x4>,
436 <0x14 0x4>;
437 reg-names = "rev", "sysc", "syss";
438 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
439 SYSC_OMAP2_AUTOIDLE)>;
440 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
441 <SYSC_IDLE_NO>,
442 <SYSC_IDLE_SMART>;
443 ti,syss-mask = <1>;
444 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
445 clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
446 clock-names = "fck";
447 #address-cells = <1>;
448 #size-cells = <1>;
449 ranges = <0x00000000 0x00000000 0x00004000>,
450 <0x00004000 0x00004000 0x00001000>,
451 <0x00005000 0x00005000 0x00001000>,
452 <0x00006000 0x00006000 0x00001000>,
453 <0x00007000 0x00007000 0x00001000>;
455 ocp2scp@0 {
456 compatible = "ti,omap-ocp2scp";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 reg = <0 0x20>;
460 };
462 usb2_phy: usb2phy@4000 {
463 compatible = "ti,omap-usb2";
464 reg = <0x4000 0x7c>;
465 syscon-phy-power = <&scm_conf 0x300>;
466 clocks = <&usb_phy_cm_clk32k>,
467 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
468 clock-names = "wkupclk", "refclk";
469 #phy-cells = <0>;
470 };
472 usb3_phy: usb3phy@4400 {
473 compatible = "ti,omap-usb3";
474 reg = <0x4400 0x80>,
475 <0x4800 0x64>,
476 <0x4c00 0x40>;
477 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
478 syscon-phy-power = <&scm_conf 0x370>;
479 clocks = <&usb_phy_cm_clk32k>,
480 <&sys_clkin>,
481 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
482 clock-names = "wkupclk",
483 "sysclk",
484 "refclk";
485 #phy-cells = <0>;
486 };
487 };
489 target-module@10000 { /* 0x4a090000, ap 89 36.0 */
490 compatible = "ti,sysc-omap2", "ti,sysc";
491 ti,hwmods = "ocp2scp3";
492 reg = <0x10000 0x4>,
493 <0x10010 0x4>,
494 <0x10014 0x4>;
495 reg-names = "rev", "sysc", "syss";
496 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
497 SYSC_OMAP2_AUTOIDLE)>;
498 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
499 <SYSC_IDLE_NO>,
500 <SYSC_IDLE_SMART>;
501 ti,syss-mask = <1>;
502 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
503 clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
504 clock-names = "fck";
505 #address-cells = <1>;
506 #size-cells = <1>;
507 ranges = <0x00000000 0x00010000 0x00004000>,
508 <0x00004000 0x00014000 0x00001000>,
509 <0x00005000 0x00015000 0x00001000>,
510 <0x00006000 0x00016000 0x00001000>,
511 <0x00007000 0x00017000 0x00001000>;
513 ocp2scp@0 {
514 compatible = "ti,omap-ocp2scp";
515 #address-cells = <1>;
516 #size-cells = <1>;
517 reg = <0x0 0x20>;
518 };
520 sata_phy: phy@6000 {
521 compatible = "ti,phy-pipe3-sata";
522 reg = <0x6000 0x80>, /* phy_rx */
523 <0x6400 0x64>, /* phy_tx */
524 <0x6800 0x40>; /* pll_ctrl */
525 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
526 syscon-phy-power = <&scm_conf 0x374>;
527 clocks = <&sys_clkin>,
528 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
529 clock-names = "sysclk", "refclk";
530 #phy-cells = <0>;
531 };
532 };
534 target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
535 compatible = "ti,sysc";
536 status = "disabled";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges = <0x00000000 0x00020000 0x00004000>,
540 <0x00004000 0x00024000 0x00001000>,
541 <0x00005000 0x00025000 0x00001000>,
542 <0x00006000 0x00026000 0x00001000>,
543 <0x00007000 0x00027000 0x00001000>;
544 };
546 target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
547 compatible = "ti,sysc";
548 status = "disabled";
549 #address-cells = <1>;
550 #size-cells = <1>;
551 ranges = <0x0 0x36000 0x1000>;
552 };
554 target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
555 compatible = "ti,sysc";
556 status = "disabled";
557 #address-cells = <1>;
558 #size-cells = <1>;
559 ranges = <0x0 0x4d000 0x1000>;
560 };
562 target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
563 compatible = "ti,sysc";
564 status = "disabled";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges = <0x0 0x59000 0x1000>;
568 };
570 target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
571 compatible = "ti,sysc";
572 status = "disabled";
573 #address-cells = <1>;
574 #size-cells = <1>;
575 ranges = <0x0 0x5b000 0x1000>;
576 };
578 target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
579 compatible = "ti,sysc";
580 status = "disabled";
581 #address-cells = <1>;
582 #size-cells = <1>;
583 ranges = <0x0 0x5d000 0x1000>;
584 };
586 target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
587 compatible = "ti,sysc";
588 status = "disabled";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges = <0x0 0x60000 0x1000>;
592 };
594 target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
595 compatible = "ti,sysc-omap4", "ti,sysc";
596 reg = <0x74000 0x4>,
597 <0x74010 0x4>;
598 reg-names = "rev", "sysc";
599 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
600 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
601 <SYSC_IDLE_NO>,
602 <SYSC_IDLE_SMART>;
603 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
604 clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
605 clock-names = "fck";
606 #address-cells = <1>;
607 #size-cells = <1>;
608 ranges = <0x0 0x74000 0x1000>;
610 mailbox: mailbox@0 {
611 compatible = "ti,omap4-mailbox";
612 reg = <0x0 0x200>;
613 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
614 #mbox-cells = <1>;
615 ti,mbox-num-users = <3>;
616 ti,mbox-num-fifos = <8>;
617 mbox_ipu: mbox_ipu {
618 ti,mbox-tx = <0 0 0>;
619 ti,mbox-rx = <1 0 0>;
620 };
621 mbox_dsp: mbox_dsp {
622 ti,mbox-tx = <3 0 0>;
623 ti,mbox-rx = <2 0 0>;
624 };
625 };
626 };
628 target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
629 compatible = "ti,sysc-omap2", "ti,sysc";
630 ti,hwmods = "spinlock";
631 reg = <0x76000 0x4>,
632 <0x76010 0x4>,
633 <0x76014 0x4>;
634 reg-names = "rev", "sysc", "syss";
635 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
636 SYSC_OMAP2_ENAWAKEUP |
637 SYSC_OMAP2_SOFTRESET |
638 SYSC_OMAP2_AUTOIDLE)>;
639 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
640 <SYSC_IDLE_NO>,
641 <SYSC_IDLE_SMART>;
642 ti,syss-mask = <1>;
643 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
644 clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
645 clock-names = "fck";
646 #address-cells = <1>;
647 #size-cells = <1>;
648 ranges = <0x0 0x76000 0x1000>;
650 hwspinlock: spinlock@0 {
651 compatible = "ti,omap4-hwspinlock";
652 reg = <0x0 0x1000>;
653 #hwlock-cells = <1>;
654 };
655 };
656 };
658 segment@100000 { /* 0x4a100000 */
659 compatible = "simple-bus";
660 #address-cells = <1>;
661 #size-cells = <1>;
662 ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
663 <0x00003000 0x00103000 0x001000>, /* ap 60 */
664 <0x00008000 0x00108000 0x001000>, /* ap 61 */
665 <0x00009000 0x00109000 0x001000>, /* ap 62 */
666 <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
667 <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
668 <0x00040000 0x00140000 0x010000>, /* ap 101 */
669 <0x00050000 0x00150000 0x001000>; /* ap 102 */
671 target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
672 compatible = "ti,sysc";
673 status = "disabled";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges = <0x0 0x2000 0x1000>;
677 };
679 target-module@8000 { /* 0x4a108000, ap 61 26.0 */
680 compatible = "ti,sysc";
681 status = "disabled";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 ranges = <0x0 0x8000 0x1000>;
685 };
687 target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
688 compatible = "ti,sysc";
689 status = "disabled";
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges = <0x0 0xa000 0x1000>;
693 };
695 target-module@40000 { /* 0x4a140000, ap 101 16.0 */
696 compatible = "ti,sysc";
697 status = "disabled";
698 #address-cells = <1>;
699 #size-cells = <1>;
700 ranges = <0x0 0x40000 0x10000>;
701 };
702 };
704 segment@180000 { /* 0x4a180000 */
705 compatible = "simple-bus";
706 #address-cells = <1>;
707 #size-cells = <1>;
708 };
710 segment@200000 { /* 0x4a200000 */
711 compatible = "simple-bus";
712 #address-cells = <1>;
713 #size-cells = <1>;
714 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
715 <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
716 <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
717 <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
718 <0x00006000 0x00206000 0x001000>, /* ap 33 */
719 <0x00007000 0x00207000 0x001000>, /* ap 34 */
720 <0x00004000 0x00204000 0x001000>, /* ap 35 */
721 <0x00005000 0x00205000 0x001000>, /* ap 36 */
722 <0x00012000 0x00212000 0x001000>, /* ap 37 */
723 <0x00013000 0x00213000 0x001000>, /* ap 38 */
724 <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
725 <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
726 <0x00010000 0x00210000 0x001000>, /* ap 41 */
727 <0x00011000 0x00211000 0x001000>, /* ap 42 */
728 <0x00016000 0x00216000 0x001000>, /* ap 43 */
729 <0x00017000 0x00217000 0x001000>, /* ap 44 */
730 <0x00014000 0x00214000 0x001000>, /* ap 45 */
731 <0x00015000 0x00215000 0x001000>, /* ap 46 */
732 <0x00018000 0x00218000 0x001000>, /* ap 47 */
733 <0x00019000 0x00219000 0x001000>, /* ap 48 */
734 <0x00020000 0x00220000 0x001000>, /* ap 49 */
735 <0x00021000 0x00221000 0x001000>, /* ap 50 */
736 <0x00026000 0x00226000 0x001000>, /* ap 51 */
737 <0x00027000 0x00227000 0x001000>, /* ap 52 */
738 <0x00028000 0x00228000 0x001000>, /* ap 53 */
739 <0x00029000 0x00229000 0x001000>, /* ap 54 */
740 <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
741 <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
742 <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
743 <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
744 <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
745 <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
746 <0x00024000 0x00224000 0x001000>, /* ap 75 */
747 <0x00025000 0x00225000 0x001000>, /* ap 76 */
748 <0x00002000 0x00202000 0x001000>, /* ap 103 */
749 <0x00003000 0x00203000 0x001000>, /* ap 104 */
750 <0x00008000 0x00208000 0x001000>, /* ap 105 */
751 <0x00009000 0x00209000 0x001000>, /* ap 106 */
752 <0x00022000 0x00222000 0x001000>, /* ap 107 */
753 <0x00023000 0x00223000 0x001000>; /* ap 108 */
755 target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
756 compatible = "ti,sysc";
757 status = "disabled";
758 #address-cells = <1>;
759 #size-cells = <1>;
760 ranges = <0x0 0x2000 0x1000>;
761 };
763 target-module@4000 { /* 0x4a204000, ap 35 46.0 */
764 compatible = "ti,sysc";
765 status = "disabled";
766 #address-cells = <1>;
767 #size-cells = <1>;
768 ranges = <0x0 0x4000 0x1000>;
769 };
771 target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
772 compatible = "ti,sysc";
773 status = "disabled";
774 #address-cells = <1>;
775 #size-cells = <1>;
776 ranges = <0x0 0x6000 0x1000>;
777 };
779 target-module@8000 { /* 0x4a208000, ap 105 34.0 */
780 compatible = "ti,sysc";
781 status = "disabled";
782 #address-cells = <1>;
783 #size-cells = <1>;
784 ranges = <0x0 0x8000 0x1000>;
785 };
787 target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
788 compatible = "ti,sysc";
789 status = "disabled";
790 #address-cells = <1>;
791 #size-cells = <1>;
792 ranges = <0x0 0xa000 0x1000>;
793 };
795 target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
796 compatible = "ti,sysc";
797 status = "disabled";
798 #address-cells = <1>;
799 #size-cells = <1>;
800 ranges = <0x0 0xc000 0x1000>;
801 };
803 target-module@10000 { /* 0x4a210000, ap 41 56.0 */
804 compatible = "ti,sysc";
805 status = "disabled";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 ranges = <0x0 0x10000 0x1000>;
809 };
811 target-module@12000 { /* 0x4a212000, ap 37 52.0 */
812 compatible = "ti,sysc";
813 status = "disabled";
814 #address-cells = <1>;
815 #size-cells = <1>;
816 ranges = <0x0 0x12000 0x1000>;
817 };
819 target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
820 compatible = "ti,sysc";
821 status = "disabled";
822 #address-cells = <1>;
823 #size-cells = <1>;
824 ranges = <0x0 0x14000 0x1000>;
825 };
827 target-module@16000 { /* 0x4a216000, ap 43 42.0 */
828 compatible = "ti,sysc";
829 status = "disabled";
830 #address-cells = <1>;
831 #size-cells = <1>;
832 ranges = <0x0 0x16000 0x1000>;
833 };
835 target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
836 compatible = "ti,sysc";
837 status = "disabled";
838 #address-cells = <1>;
839 #size-cells = <1>;
840 ranges = <0x0 0x18000 0x1000>;
841 };
843 target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
844 compatible = "ti,sysc";
845 status = "disabled";
846 #address-cells = <1>;
847 #size-cells = <1>;
848 ranges = <0x0 0x1a000 0x1000>;
849 };
851 target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
852 compatible = "ti,sysc";
853 status = "disabled";
854 #address-cells = <1>;
855 #size-cells = <1>;
856 ranges = <0x0 0x1c000 0x1000>;
857 };
859 target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
860 compatible = "ti,sysc";
861 status = "disabled";
862 #address-cells = <1>;
863 #size-cells = <1>;
864 ranges = <0x0 0x1e000 0x1000>;
865 };
867 target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
868 compatible = "ti,sysc";
869 status = "disabled";
870 #address-cells = <1>;
871 #size-cells = <1>;
872 ranges = <0x0 0x20000 0x1000>;
873 };
875 target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
876 compatible = "ti,sysc";
877 status = "disabled";
878 #address-cells = <1>;
879 #size-cells = <1>;
880 ranges = <0x0 0x22000 0x1000>;
881 };
883 target-module@24000 { /* 0x4a224000, ap 75 48.0 */
884 compatible = "ti,sysc";
885 status = "disabled";
886 #address-cells = <1>;
887 #size-cells = <1>;
888 ranges = <0x0 0x24000 0x1000>;
889 };
891 target-module@26000 { /* 0x4a226000, ap 51 24.0 */
892 compatible = "ti,sysc";
893 status = "disabled";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 ranges = <0x0 0x26000 0x1000>;
897 };
899 target-module@28000 { /* 0x4a228000, ap 53 38.0 */
900 compatible = "ti,sysc";
901 status = "disabled";
902 #address-cells = <1>;
903 #size-cells = <1>;
904 ranges = <0x0 0x28000 0x1000>;
905 };
907 target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
908 compatible = "ti,sysc";
909 status = "disabled";
910 #address-cells = <1>;
911 #size-cells = <1>;
912 ranges = <0x0 0x2a000 0x1000>;
913 };
914 };
916 segment@280000 { /* 0x4a280000 */
917 compatible = "simple-bus";
918 #address-cells = <1>;
919 #size-cells = <1>;
920 };
922 segment@300000 { /* 0x4a300000 */
923 compatible = "simple-bus";
924 #address-cells = <1>;
925 #size-cells = <1>;
926 };
927 };
929 &l4_per { /* 0x48000000 */
930 compatible = "ti,omap5-l4-per", "simple-bus";
931 reg = <0x48000000 0x800>,
932 <0x48000800 0x800>,
933 <0x48001000 0x400>,
934 <0x48001400 0x400>,
935 <0x48001800 0x400>,
936 <0x48001c00 0x400>;
937 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
938 #address-cells = <1>;
939 #size-cells = <1>;
940 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
941 <0x00200000 0x48200000 0x200000>; /* segment 1 */
943 segment@0 { /* 0x48000000 */
944 compatible = "simple-bus";
945 #address-cells = <1>;
946 #size-cells = <1>;
947 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
948 <0x00001000 0x00001000 0x000400>, /* ap 1 */
949 <0x00000800 0x00000800 0x000800>, /* ap 2 */
950 <0x00020000 0x00020000 0x001000>, /* ap 3 */
951 <0x00021000 0x00021000 0x001000>, /* ap 4 */
952 <0x00032000 0x00032000 0x001000>, /* ap 5 */
953 <0x00033000 0x00033000 0x001000>, /* ap 6 */
954 <0x00034000 0x00034000 0x001000>, /* ap 7 */
955 <0x00035000 0x00035000 0x001000>, /* ap 8 */
956 <0x00036000 0x00036000 0x001000>, /* ap 9 */
957 <0x00037000 0x00037000 0x001000>, /* ap 10 */
958 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
959 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
960 <0x00055000 0x00055000 0x001000>, /* ap 13 */
961 <0x00056000 0x00056000 0x001000>, /* ap 14 */
962 <0x00057000 0x00057000 0x001000>, /* ap 15 */
963 <0x00058000 0x00058000 0x001000>, /* ap 16 */
964 <0x00059000 0x00059000 0x001000>, /* ap 17 */
965 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
966 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
967 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
968 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
969 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
970 <0x00060000 0x00060000 0x001000>, /* ap 23 */
971 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
972 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
973 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
974 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
975 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
976 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
977 <0x00070000 0x00070000 0x001000>, /* ap 30 */
978 <0x00071000 0x00071000 0x001000>, /* ap 31 */
979 <0x00072000 0x00072000 0x001000>, /* ap 32 */
980 <0x00073000 0x00073000 0x001000>, /* ap 33 */
981 <0x00061000 0x00061000 0x001000>, /* ap 34 */
982 <0x00053000 0x00053000 0x001000>, /* ap 35 */
983 <0x00054000 0x00054000 0x001000>, /* ap 36 */
984 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
985 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
986 <0x00078000 0x00078000 0x001000>, /* ap 39 */
987 <0x00079000 0x00079000 0x001000>, /* ap 40 */
988 <0x00086000 0x00086000 0x001000>, /* ap 41 */
989 <0x00087000 0x00087000 0x001000>, /* ap 42 */
990 <0x00088000 0x00088000 0x001000>, /* ap 43 */
991 <0x00089000 0x00089000 0x001000>, /* ap 44 */
992 <0x00051000 0x00051000 0x001000>, /* ap 45 */
993 <0x00052000 0x00052000 0x001000>, /* ap 46 */
994 <0x00098000 0x00098000 0x001000>, /* ap 47 */
995 <0x00099000 0x00099000 0x001000>, /* ap 48 */
996 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
997 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
998 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
999 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1000 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1001 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1002 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1003 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1004 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1005 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1006 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1007 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1008 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1009 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1010 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1011 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1012 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1013 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1014 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1015 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1016 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1017 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1018 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1019 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1020 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1021 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1022 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1023 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1024 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1025 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1026 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1027 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1028 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1029 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1030 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1031 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1033 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1034 compatible = "ti,sysc-omap2", "ti,sysc";
1035 reg = <0x20050 0x4>,
1036 <0x20054 0x4>,
1037 <0x20058 0x4>;
1038 reg-names = "rev", "sysc", "syss";
1039 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1040 SYSC_OMAP2_SOFTRESET |
1041 SYSC_OMAP2_AUTOIDLE)>;
1042 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1043 <SYSC_IDLE_NO>,
1044 <SYSC_IDLE_SMART>,
1045 <SYSC_IDLE_SMART_WKUP>;
1046 ti,syss-mask = <1>;
1047 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1048 clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
1049 clock-names = "fck";
1050 #address-cells = <1>;
1051 #size-cells = <1>;
1052 ranges = <0x0 0x20000 0x1000>;
1054 uart3: serial@0 {
1055 compatible = "ti,omap4-uart";
1056 reg = <0x0 0x100>;
1057 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1058 clock-frequency = <48000000>;
1059 };
1060 };
1062 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1063 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1064 ti,hwmods = "timer2";
1065 reg = <0x32000 0x4>,
1066 <0x32010 0x4>;
1067 reg-names = "rev", "sysc";
1068 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1069 SYSC_OMAP4_SOFTRESET)>;
1070 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1071 <SYSC_IDLE_NO>,
1072 <SYSC_IDLE_SMART>,
1073 <SYSC_IDLE_SMART_WKUP>;
1074 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1075 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
1076 clock-names = "fck";
1077 #address-cells = <1>;
1078 #size-cells = <1>;
1079 ranges = <0x0 0x32000 0x1000>;
1081 timer2: timer@0 {
1082 compatible = "ti,omap5430-timer";
1083 reg = <0x0 0x80>;
1084 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
1085 clock-names = "fck";
1086 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1087 };
1088 };
1090 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1091 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1092 ti,hwmods = "timer3";
1093 reg = <0x34000 0x4>,
1094 <0x34010 0x4>;
1095 reg-names = "rev", "sysc";
1096 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1097 SYSC_OMAP4_SOFTRESET)>;
1098 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1099 <SYSC_IDLE_NO>,
1100 <SYSC_IDLE_SMART>,
1101 <SYSC_IDLE_SMART_WKUP>;
1102 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1103 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
1104 clock-names = "fck";
1105 #address-cells = <1>;
1106 #size-cells = <1>;
1107 ranges = <0x0 0x34000 0x1000>;
1109 timer3: timer@0 {
1110 compatible = "ti,omap5430-timer";
1111 reg = <0x0 0x80>;
1112 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
1113 clock-names = "fck";
1114 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1116 };
1118 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1119 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1120 ti,hwmods = "timer4";
1121 reg = <0x36000 0x4>,
1122 <0x36010 0x4>;
1123 reg-names = "rev", "sysc";
1124 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1125 SYSC_OMAP4_SOFTRESET)>;
1126 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1127 <SYSC_IDLE_NO>,
1128 <SYSC_IDLE_SMART>,
1129 <SYSC_IDLE_SMART_WKUP>;
1130 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1131 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
1132 clock-names = "fck";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 ranges = <0x0 0x36000 0x1000>;
1137 timer4: timer@0 {
1138 compatible = "ti,omap5430-timer";
1139 reg = <0x0 0x80>;
1140 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
1141 clock-names = "fck";
1142 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1143 };
1144 };
1146 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1147 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1148 ti,hwmods = "timer9";
1149 reg = <0x3e000 0x4>,
1150 <0x3e010 0x4>;
1151 reg-names = "rev", "sysc";
1152 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1153 SYSC_OMAP4_SOFTRESET)>;
1154 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1155 <SYSC_IDLE_NO>,
1156 <SYSC_IDLE_SMART>,
1157 <SYSC_IDLE_SMART_WKUP>;
1158 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1159 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
1160 clock-names = "fck";
1161 #address-cells = <1>;
1162 #size-cells = <1>;
1163 ranges = <0x0 0x3e000 0x1000>;
1165 timer9: timer@0 {
1166 compatible = "ti,omap5430-timer";
1167 reg = <0x0 0x80>;
1168 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
1169 clock-names = "fck";
1170 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1171 ti,timer-pwm;
1172 };
1173 };
1175 target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1176 compatible = "ti,sysc-omap2", "ti,sysc";
1177 reg = <0x51000 0x4>,
1178 <0x51010 0x4>,
1179 <0x51114 0x4>;
1180 reg-names = "rev", "sysc", "syss";
1181 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1182 SYSC_OMAP2_SOFTRESET |
1183 SYSC_OMAP2_AUTOIDLE)>;
1184 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1185 <SYSC_IDLE_NO>,
1186 <SYSC_IDLE_SMART>,
1187 <SYSC_IDLE_SMART_WKUP>;
1188 ti,syss-mask = <1>;
1189 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1190 clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
1191 <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
1192 clock-names = "fck", "dbclk";
1193 #address-cells = <1>;
1194 #size-cells = <1>;
1195 ranges = <0x0 0x51000 0x1000>;
1197 gpio7: gpio@0 {
1198 compatible = "ti,omap4-gpio";
1199 reg = <0x0 0x200>;
1200 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1201 gpio-controller;
1202 #gpio-cells = <2>;
1203 interrupt-controller;
1204 #interrupt-cells = <2>;
1205 };
1206 };
1208 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1209 compatible = "ti,sysc-omap2", "ti,sysc";
1210 reg = <0x53000 0x4>,
1211 <0x53010 0x4>,
1212 <0x53114 0x4>;
1213 reg-names = "rev", "sysc", "syss";
1214 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1215 SYSC_OMAP2_SOFTRESET |
1216 SYSC_OMAP2_AUTOIDLE)>;
1217 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1218 <SYSC_IDLE_NO>,
1219 <SYSC_IDLE_SMART>,
1220 <SYSC_IDLE_SMART_WKUP>;
1221 ti,syss-mask = <1>;
1222 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1223 clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
1224 <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
1225 clock-names = "fck", "dbclk";
1226 #address-cells = <1>;
1227 #size-cells = <1>;
1228 ranges = <0x0 0x53000 0x1000>;
1230 gpio8: gpio@0 {
1231 compatible = "ti,omap4-gpio";
1232 reg = <0x0 0x200>;
1233 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1234 gpio-controller;
1235 #gpio-cells = <2>;
1236 interrupt-controller;
1237 #interrupt-cells = <2>;
1238 };
1239 };
1241 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1242 compatible = "ti,sysc-omap2", "ti,sysc";
1243 reg = <0x55000 0x4>,
1244 <0x55010 0x4>,
1245 <0x55114 0x4>;
1246 reg-names = "rev", "sysc", "syss";
1247 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1248 SYSC_OMAP2_SOFTRESET |
1249 SYSC_OMAP2_AUTOIDLE)>;
1250 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1251 <SYSC_IDLE_NO>,
1252 <SYSC_IDLE_SMART>,
1253 <SYSC_IDLE_SMART_WKUP>;
1254 ti,syss-mask = <1>;
1255 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1256 clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
1257 <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
1258 clock-names = "fck", "dbclk";
1259 #address-cells = <1>;
1260 #size-cells = <1>;
1261 ranges = <0x0 0x55000 0x1000>;
1263 gpio2: gpio@0 {
1264 compatible = "ti,omap4-gpio";
1265 reg = <0x0 0x200>;
1266 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1267 gpio-controller;
1268 #gpio-cells = <2>;
1269 interrupt-controller;
1270 #interrupt-cells = <2>;
1271 };
1272 };
1274 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1275 compatible = "ti,sysc-omap2", "ti,sysc";
1276 reg = <0x57000 0x4>,
1277 <0x57010 0x4>,
1278 <0x57114 0x4>;
1279 reg-names = "rev", "sysc", "syss";
1280 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1281 SYSC_OMAP2_SOFTRESET |
1282 SYSC_OMAP2_AUTOIDLE)>;
1283 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1284 <SYSC_IDLE_NO>,
1285 <SYSC_IDLE_SMART>,
1286 <SYSC_IDLE_SMART_WKUP>;
1287 ti,syss-mask = <1>;
1288 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1289 clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
1290 <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
1291 clock-names = "fck", "dbclk";
1292 #address-cells = <1>;
1293 #size-cells = <1>;
1294 ranges = <0x0 0x57000 0x1000>;
1296 gpio3: gpio@0 {
1297 compatible = "ti,omap4-gpio";
1298 reg = <0x0 0x200>;
1299 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1300 gpio-controller;
1301 #gpio-cells = <2>;
1302 interrupt-controller;
1303 #interrupt-cells = <2>;
1304 };
1305 };
1307 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1308 compatible = "ti,sysc-omap2", "ti,sysc";
1309 reg = <0x59000 0x4>,
1310 <0x59010 0x4>,
1311 <0x59114 0x4>;
1312 reg-names = "rev", "sysc", "syss";
1313 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1314 SYSC_OMAP2_SOFTRESET |
1315 SYSC_OMAP2_AUTOIDLE)>;
1316 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1317 <SYSC_IDLE_NO>,
1318 <SYSC_IDLE_SMART>,
1319 <SYSC_IDLE_SMART_WKUP>;
1320 ti,syss-mask = <1>;
1321 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1322 clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
1323 <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
1324 clock-names = "fck", "dbclk";
1325 #address-cells = <1>;
1326 #size-cells = <1>;
1327 ranges = <0x0 0x59000 0x1000>;
1329 gpio4: gpio@0 {
1330 compatible = "ti,omap4-gpio";
1331 reg = <0x0 0x200>;
1332 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1333 gpio-controller;
1334 #gpio-cells = <2>;
1335 interrupt-controller;
1336 #interrupt-cells = <2>;
1337 };
1338 };
1340 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1341 compatible = "ti,sysc-omap2", "ti,sysc";
1342 reg = <0x5b000 0x4>,
1343 <0x5b010 0x4>,
1344 <0x5b114 0x4>;
1345 reg-names = "rev", "sysc", "syss";
1346 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1347 SYSC_OMAP2_SOFTRESET |
1348 SYSC_OMAP2_AUTOIDLE)>;
1349 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1350 <SYSC_IDLE_NO>,
1351 <SYSC_IDLE_SMART>,
1352 <SYSC_IDLE_SMART_WKUP>;
1353 ti,syss-mask = <1>;
1354 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1355 clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
1356 <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
1357 clock-names = "fck", "dbclk";
1358 #address-cells = <1>;
1359 #size-cells = <1>;
1360 ranges = <0x0 0x5b000 0x1000>;
1362 gpio5: gpio@0 {
1363 compatible = "ti,omap4-gpio";
1364 reg = <0x0 0x200>;
1365 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1366 gpio-controller;
1367 #gpio-cells = <2>;
1368 interrupt-controller;
1369 #interrupt-cells = <2>;
1370 };
1371 };
1373 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1374 compatible = "ti,sysc-omap2", "ti,sysc";
1375 reg = <0x5d000 0x4>,
1376 <0x5d010 0x4>,
1377 <0x5d114 0x4>;
1378 reg-names = "rev", "sysc", "syss";
1379 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1380 SYSC_OMAP2_SOFTRESET |
1381 SYSC_OMAP2_AUTOIDLE)>;
1382 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1383 <SYSC_IDLE_NO>,
1384 <SYSC_IDLE_SMART>,
1385 <SYSC_IDLE_SMART_WKUP>;
1386 ti,syss-mask = <1>;
1387 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1388 clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
1389 <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
1390 clock-names = "fck", "dbclk";
1391 #address-cells = <1>;
1392 #size-cells = <1>;
1393 ranges = <0x0 0x5d000 0x1000>;
1395 gpio6: gpio@0 {
1396 compatible = "ti,omap4-gpio";
1397 reg = <0x0 0x200>;
1398 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1399 gpio-controller;
1400 #gpio-cells = <2>;
1401 interrupt-controller;
1402 #interrupt-cells = <2>;
1403 };
1404 };
1406 target-module@60000 { /* 0x48060000, ap 23 24.0 */
1407 compatible = "ti,sysc-omap2", "ti,sysc";
1408 reg = <0x60000 0x8>,
1409 <0x60010 0x8>,
1410 <0x60090 0x8>;
1411 reg-names = "rev", "sysc", "syss";
1412 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1413 SYSC_OMAP2_ENAWAKEUP |
1414 SYSC_OMAP2_SOFTRESET |
1415 SYSC_OMAP2_AUTOIDLE)>;
1416 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1417 <SYSC_IDLE_NO>,
1418 <SYSC_IDLE_SMART>,
1419 <SYSC_IDLE_SMART_WKUP>;
1420 ti,syss-mask = <1>;
1421 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1422 clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
1423 clock-names = "fck";
1424 #address-cells = <1>;
1425 #size-cells = <1>;
1426 ranges = <0x0 0x60000 0x1000>;
1428 i2c3: i2c@0 {
1429 compatible = "ti,omap4-i2c";
1430 reg = <0x0 0x100>;
1431 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1434 };
1435 };
1437 target-module@66000 { /* 0x48066000, ap 63 4c.0 */
1438 compatible = "ti,sysc-omap2", "ti,sysc";
1439 reg = <0x66050 0x4>,
1440 <0x66054 0x4>,
1441 <0x66058 0x4>;
1442 reg-names = "rev", "sysc", "syss";
1443 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1444 SYSC_OMAP2_SOFTRESET |
1445 SYSC_OMAP2_AUTOIDLE)>;
1446 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1447 <SYSC_IDLE_NO>,
1448 <SYSC_IDLE_SMART>,
1449 <SYSC_IDLE_SMART_WKUP>;
1450 ti,syss-mask = <1>;
1451 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1452 clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
1453 clock-names = "fck";
1454 #address-cells = <1>;
1455 #size-cells = <1>;
1456 ranges = <0x0 0x66000 0x1000>;
1458 uart5: serial@0 {
1459 compatible = "ti,omap4-uart";
1460 reg = <0x0 0x100>;
1461 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1462 clock-frequency = <48000000>;
1463 };
1464 };
1466 target-module@68000 { /* 0x48068000, ap 53 54.0 */
1467 compatible = "ti,sysc-omap2", "ti,sysc";
1468 reg = <0x68050 0x4>,
1469 <0x68054 0x4>,
1470 <0x68058 0x4>;
1471 reg-names = "rev", "sysc", "syss";
1472 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1473 SYSC_OMAP2_SOFTRESET |
1474 SYSC_OMAP2_AUTOIDLE)>;
1475 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1476 <SYSC_IDLE_NO>,
1477 <SYSC_IDLE_SMART>,
1478 <SYSC_IDLE_SMART_WKUP>;
1479 ti,syss-mask = <1>;
1480 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1481 clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
1482 clock-names = "fck";
1483 #address-cells = <1>;
1484 #size-cells = <1>;
1485 ranges = <0x0 0x68000 0x1000>;
1487 uart6: serial@0 {
1488 compatible = "ti,omap4-uart";
1489 reg = <0x0 0x100>;
1490 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1491 clock-frequency = <48000000>;
1492 };
1493 };
1495 target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
1496 compatible = "ti,sysc-omap2", "ti,sysc";
1497 reg = <0x6a050 0x4>,
1498 <0x6a054 0x4>,
1499 <0x6a058 0x4>;
1500 reg-names = "rev", "sysc", "syss";
1501 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1502 SYSC_OMAP2_SOFTRESET |
1503 SYSC_OMAP2_AUTOIDLE)>;
1504 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1505 <SYSC_IDLE_NO>,
1506 <SYSC_IDLE_SMART>,
1507 <SYSC_IDLE_SMART_WKUP>;
1508 ti,syss-mask = <1>;
1509 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1510 clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
1511 clock-names = "fck";
1512 #address-cells = <1>;
1513 #size-cells = <1>;
1514 ranges = <0x0 0x6a000 0x1000>;
1516 uart1: serial@0 {
1517 compatible = "ti,omap4-uart";
1518 reg = <0x0 0x100>;
1519 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1520 clock-frequency = <48000000>;
1521 };
1522 };
1524 target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
1525 compatible = "ti,sysc-omap2", "ti,sysc";
1526 reg = <0x6c050 0x4>,
1527 <0x6c054 0x4>,
1528 <0x6c058 0x4>;
1529 reg-names = "rev", "sysc", "syss";
1530 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1531 SYSC_OMAP2_SOFTRESET |
1532 SYSC_OMAP2_AUTOIDLE)>;
1533 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1534 <SYSC_IDLE_NO>,
1535 <SYSC_IDLE_SMART>,
1536 <SYSC_IDLE_SMART_WKUP>;
1537 ti,syss-mask = <1>;
1538 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1539 clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
1540 clock-names = "fck";
1541 #address-cells = <1>;
1542 #size-cells = <1>;
1543 ranges = <0x0 0x6c000 0x1000>;
1545 uart2: serial@0 {
1546 compatible = "ti,omap4-uart";
1547 reg = <0x0 0x100>;
1548 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1549 clock-frequency = <48000000>;
1550 };
1551 };
1553 target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
1554 compatible = "ti,sysc-omap2", "ti,sysc";
1555 reg = <0x6e050 0x4>,
1556 <0x6e054 0x4>,
1557 <0x6e058 0x4>;
1558 reg-names = "rev", "sysc", "syss";
1559 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1560 SYSC_OMAP2_SOFTRESET |
1561 SYSC_OMAP2_AUTOIDLE)>;
1562 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1563 <SYSC_IDLE_NO>,
1564 <SYSC_IDLE_SMART>,
1565 <SYSC_IDLE_SMART_WKUP>;
1566 ti,syss-mask = <1>;
1567 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1568 clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
1569 clock-names = "fck";
1570 #address-cells = <1>;
1571 #size-cells = <1>;
1572 ranges = <0x0 0x6e000 0x1000>;
1574 uart4: serial@0 {
1575 compatible = "ti,omap4-uart";
1576 reg = <0x0 0x100>;
1577 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1578 clock-frequency = <48000000>;
1579 };
1580 };
1582 target-module@70000 { /* 0x48070000, ap 30 14.0 */
1583 compatible = "ti,sysc-omap2", "ti,sysc";
1584 reg = <0x70000 0x8>,
1585 <0x70010 0x8>,
1586 <0x70090 0x8>;
1587 reg-names = "rev", "sysc", "syss";
1588 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1589 SYSC_OMAP2_ENAWAKEUP |
1590 SYSC_OMAP2_SOFTRESET |
1591 SYSC_OMAP2_AUTOIDLE)>;
1592 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1593 <SYSC_IDLE_NO>,
1594 <SYSC_IDLE_SMART>,
1595 <SYSC_IDLE_SMART_WKUP>;
1596 ti,syss-mask = <1>;
1597 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1598 clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
1599 clock-names = "fck";
1600 #address-cells = <1>;
1601 #size-cells = <1>;
1602 ranges = <0x0 0x70000 0x1000>;
1604 i2c1: i2c@0 {
1605 compatible = "ti,omap4-i2c";
1606 reg = <0x0 0x100>;
1607 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1610 };
1611 };
1613 target-module@72000 { /* 0x48072000, ap 32 1c.0 */
1614 compatible = "ti,sysc-omap2", "ti,sysc";
1615 reg = <0x72000 0x8>,
1616 <0x72010 0x8>,
1617 <0x72090 0x8>;
1618 reg-names = "rev", "sysc", "syss";
1619 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1620 SYSC_OMAP2_ENAWAKEUP |
1621 SYSC_OMAP2_SOFTRESET |
1622 SYSC_OMAP2_AUTOIDLE)>;
1623 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1624 <SYSC_IDLE_NO>,
1625 <SYSC_IDLE_SMART>,
1626 <SYSC_IDLE_SMART_WKUP>;
1627 ti,syss-mask = <1>;
1628 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1629 clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
1630 clock-names = "fck";
1631 #address-cells = <1>;
1632 #size-cells = <1>;
1633 ranges = <0x0 0x72000 0x1000>;
1635 i2c2: i2c@0 {
1636 compatible = "ti,omap4-i2c";
1637 reg = <0x0 0x100>;
1638 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1641 };
1642 };
1644 target-module@78000 { /* 0x48078000, ap 39 12.0 */
1645 compatible = "ti,sysc";
1646 status = "disabled";
1647 #address-cells = <1>;
1648 #size-cells = <1>;
1649 ranges = <0x0 0x78000 0x1000>;
1650 };
1652 target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
1653 compatible = "ti,sysc-omap2", "ti,sysc";
1654 reg = <0x7a000 0x8>,
1655 <0x7a010 0x8>,
1656 <0x7a090 0x8>;
1657 reg-names = "rev", "sysc", "syss";
1658 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1659 SYSC_OMAP2_ENAWAKEUP |
1660 SYSC_OMAP2_SOFTRESET |
1661 SYSC_OMAP2_AUTOIDLE)>;
1662 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1663 <SYSC_IDLE_NO>,
1664 <SYSC_IDLE_SMART>,
1665 <SYSC_IDLE_SMART_WKUP>;
1666 ti,syss-mask = <1>;
1667 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1668 clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
1669 clock-names = "fck";
1670 #address-cells = <1>;
1671 #size-cells = <1>;
1672 ranges = <0x0 0x7a000 0x1000>;
1674 i2c4: i2c@0 {
1675 compatible = "ti,omap4-i2c";
1676 reg = <0x0 0x100>;
1677 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1678 #address-cells = <1>;
1679 #size-cells = <0>;
1680 };
1681 };
1683 target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
1684 compatible = "ti,sysc-omap2", "ti,sysc";
1685 reg = <0x7c000 0x8>,
1686 <0x7c010 0x8>,
1687 <0x7c090 0x8>;
1688 reg-names = "rev", "sysc", "syss";
1689 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1690 SYSC_OMAP2_ENAWAKEUP |
1691 SYSC_OMAP2_SOFTRESET |
1692 SYSC_OMAP2_AUTOIDLE)>;
1693 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1694 <SYSC_IDLE_NO>,
1695 <SYSC_IDLE_SMART>,
1696 <SYSC_IDLE_SMART_WKUP>;
1697 ti,syss-mask = <1>;
1698 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1699 clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
1700 clock-names = "fck";
1701 #address-cells = <1>;
1702 #size-cells = <1>;
1703 ranges = <0x0 0x7c000 0x1000>;
1705 i2c5: i2c@0 {
1706 compatible = "ti,omap4-i2c";
1707 reg = <0x0 0x100>;
1708 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711 };
1712 };
1714 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1715 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1716 ti,hwmods = "timer10";
1717 reg = <0x86000 0x4>,
1718 <0x86010 0x4>;
1719 reg-names = "rev", "sysc";
1720 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1721 SYSC_OMAP4_SOFTRESET)>;
1722 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1723 <SYSC_IDLE_NO>,
1724 <SYSC_IDLE_SMART>,
1725 <SYSC_IDLE_SMART_WKUP>;
1726 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1727 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
1728 clock-names = "fck";
1729 #address-cells = <1>;
1730 #size-cells = <1>;
1731 ranges = <0x0 0x86000 0x1000>;
1733 timer10: timer@0 {
1734 compatible = "ti,omap5430-timer";
1735 reg = <0x0 0x80>;
1736 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
1737 clock-names = "fck";
1738 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1739 ti,timer-pwm;
1740 };
1741 };
1743 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1744 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1745 ti,hwmods = "timer11";
1746 reg = <0x88000 0x4>,
1747 <0x88010 0x4>;
1748 reg-names = "rev", "sysc";
1749 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1750 SYSC_OMAP4_SOFTRESET)>;
1751 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1752 <SYSC_IDLE_NO>,
1753 <SYSC_IDLE_SMART>,
1754 <SYSC_IDLE_SMART_WKUP>;
1755 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1756 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
1757 clock-names = "fck";
1758 #address-cells = <1>;
1759 #size-cells = <1>;
1760 ranges = <0x0 0x88000 0x1000>;
1762 timer11: timer@0 {
1763 compatible = "ti,omap5430-timer";
1764 reg = <0x0 0x80>;
1765 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
1766 clock-names = "fck";
1767 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1768 ti,timer-pwm;
1769 };
1770 };
1772 target-module@90000 { /* 0x48090000, ap 55 1a.0 */
1773 compatible = "ti,sysc";
1774 status = "disabled";
1775 #address-cells = <1>;
1776 #size-cells = <1>;
1777 ranges = <0x0 0x90000 0x2000>;
1778 };
1780 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1781 compatible = "ti,sysc-omap4", "ti,sysc";
1782 reg = <0x98000 0x4>,
1783 <0x98010 0x4>;
1784 reg-names = "rev", "sysc";
1785 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1786 SYSC_OMAP4_SOFTRESET)>;
1787 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1788 <SYSC_IDLE_NO>,
1789 <SYSC_IDLE_SMART>,
1790 <SYSC_IDLE_SMART_WKUP>;
1791 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1792 clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
1793 clock-names = "fck";
1794 #address-cells = <1>;
1795 #size-cells = <1>;
1796 ranges = <0x0 0x98000 0x1000>;
1798 mcspi1: spi@0 {
1799 compatible = "ti,omap4-mcspi";
1800 reg = <0x0 0x200>;
1801 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1802 #address-cells = <1>;
1803 #size-cells = <0>;
1804 ti,spi-num-cs = <4>;
1805 dmas = <&sdma 35>,
1806 <&sdma 36>,
1807 <&sdma 37>,
1808 <&sdma 38>,
1809 <&sdma 39>,
1810 <&sdma 40>,
1811 <&sdma 41>,
1812 <&sdma 42>;
1813 dma-names = "tx0", "rx0", "tx1", "rx1",
1814 "tx2", "rx2", "tx3", "rx3";
1815 };
1816 };
1818 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1819 compatible = "ti,sysc-omap4", "ti,sysc";
1820 reg = <0x9a000 0x4>,
1821 <0x9a010 0x4>;
1822 reg-names = "rev", "sysc";
1823 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1824 SYSC_OMAP4_SOFTRESET)>;
1825 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1826 <SYSC_IDLE_NO>,
1827 <SYSC_IDLE_SMART>,
1828 <SYSC_IDLE_SMART_WKUP>;
1829 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1830 clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
1831 clock-names = "fck";
1832 #address-cells = <1>;
1833 #size-cells = <1>;
1834 ranges = <0x0 0x9a000 0x1000>;
1836 mcspi2: spi@0 {
1837 compatible = "ti,omap4-mcspi";
1838 reg = <0x0 0x200>;
1839 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1842 ti,spi-num-cs = <2>;
1843 dmas = <&sdma 43>,
1844 <&sdma 44>,
1845 <&sdma 45>,
1846 <&sdma 46>;
1847 dma-names = "tx0", "rx0", "tx1", "rx1";
1848 };
1849 };
1851 target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
1852 compatible = "ti,sysc-omap4", "ti,sysc";
1853 reg = <0x9c000 0x4>,
1854 <0x9c010 0x4>;
1855 reg-names = "rev", "sysc";
1856 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1857 SYSC_OMAP4_SOFTRESET)>;
1858 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1859 <SYSC_IDLE_NO>,
1860 <SYSC_IDLE_SMART>,
1861 <SYSC_IDLE_SMART_WKUP>;
1862 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1863 <SYSC_IDLE_NO>,
1864 <SYSC_IDLE_SMART>,
1865 <SYSC_IDLE_SMART_WKUP>;
1866 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
1867 clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
1868 clock-names = "fck";
1869 #address-cells = <1>;
1870 #size-cells = <1>;
1871 ranges = <0x0 0x9c000 0x1000>;
1873 mmc1: mmc@0 {
1874 compatible = "ti,omap4-hsmmc";
1875 reg = <0x0 0x400>;
1876 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1877 ti,dual-volt;
1878 ti,needs-special-reset;
1879 dmas = <&sdma 61>, <&sdma 62>;
1880 dma-names = "tx", "rx";
1881 pbias-supply = <&pbias_mmc_reg>;
1882 };
1883 };
1885 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
1886 compatible = "ti,sysc";
1887 status = "disabled";
1888 #address-cells = <1>;
1889 #size-cells = <1>;
1890 ranges = <0x0 0xa2000 0x1000>;
1891 };
1893 target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
1894 compatible = "ti,sysc";
1895 status = "disabled";
1896 #address-cells = <1>;
1897 #size-cells = <1>;
1898 ranges = <0x00000000 0x000a4000 0x00001000>,
1899 <0x00001000 0x000a5000 0x00001000>;
1900 };
1902 target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
1903 compatible = "ti,sysc";
1904 status = "disabled";
1905 #address-cells = <1>;
1906 #size-cells = <1>;
1907 ranges = <0x0 0xa8000 0x4000>;
1908 };
1910 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
1911 compatible = "ti,sysc-omap4", "ti,sysc";
1912 reg = <0xad000 0x4>,
1913 <0xad010 0x4>;
1914 reg-names = "rev", "sysc";
1915 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1916 SYSC_OMAP4_SOFTRESET)>;
1917 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1918 <SYSC_IDLE_NO>,
1919 <SYSC_IDLE_SMART>,
1920 <SYSC_IDLE_SMART_WKUP>;
1921 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1922 <SYSC_IDLE_NO>,
1923 <SYSC_IDLE_SMART>,
1924 <SYSC_IDLE_SMART_WKUP>;
1925 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1926 clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
1927 clock-names = "fck";
1928 #address-cells = <1>;
1929 #size-cells = <1>;
1930 ranges = <0x0 0xad000 0x1000>;
1932 mmc3: mmc@0 {
1933 compatible = "ti,omap4-hsmmc";
1934 reg = <0x0 0x400>;
1935 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1936 ti,needs-special-reset;
1937 dmas = <&sdma 77>, <&sdma 78>;
1938 dma-names = "tx", "rx";
1939 };
1940 };
1942 target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
1943 compatible = "ti,sysc";
1944 status = "disabled";
1945 #address-cells = <1>;
1946 #size-cells = <1>;
1947 ranges = <0x0 0xb2000 0x1000>;
1948 };
1950 target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
1951 compatible = "ti,sysc-omap4", "ti,sysc";
1952 reg = <0xb4000 0x4>,
1953 <0xb4010 0x4>;
1954 reg-names = "rev", "sysc";
1955 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1956 SYSC_OMAP4_SOFTRESET)>;
1957 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1958 <SYSC_IDLE_NO>,
1959 <SYSC_IDLE_SMART>,
1960 <SYSC_IDLE_SMART_WKUP>;
1961 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1962 <SYSC_IDLE_NO>,
1963 <SYSC_IDLE_SMART>,
1964 <SYSC_IDLE_SMART_WKUP>;
1965 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
1966 clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
1967 clock-names = "fck";
1968 #address-cells = <1>;
1969 #size-cells = <1>;
1970 ranges = <0x0 0xb4000 0x1000>;
1972 mmc2: mmc@0 {
1973 compatible = "ti,omap4-hsmmc";
1974 reg = <0x0 0x400>;
1975 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1976 ti,needs-special-reset;
1977 dmas = <&sdma 47>, <&sdma 48>;
1978 dma-names = "tx", "rx";
1979 };
1980 };
1982 target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
1983 compatible = "ti,sysc-omap4", "ti,sysc";
1984 reg = <0xb8000 0x4>,
1985 <0xb8010 0x4>;
1986 reg-names = "rev", "sysc";
1987 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1988 SYSC_OMAP4_SOFTRESET)>;
1989 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1990 <SYSC_IDLE_NO>,
1991 <SYSC_IDLE_SMART>,
1992 <SYSC_IDLE_SMART_WKUP>;
1993 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1994 clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
1995 clock-names = "fck";
1996 #address-cells = <1>;
1997 #size-cells = <1>;
1998 ranges = <0x0 0xb8000 0x1000>;
2000 mcspi3: spi@0 {
2001 compatible = "ti,omap4-mcspi";
2002 reg = <0x0 0x200>;
2003 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2004 #address-cells = <1>;
2005 #size-cells = <0>;
2006 ti,spi-num-cs = <2>;
2007 dmas = <&sdma 15>, <&sdma 16>;
2008 dma-names = "tx0", "rx0";
2009 };
2010 };
2012 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2013 compatible = "ti,sysc-omap4", "ti,sysc";
2014 reg = <0xba000 0x4>,
2015 <0xba010 0x4>;
2016 reg-names = "rev", "sysc";
2017 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2018 SYSC_OMAP4_SOFTRESET)>;
2019 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2020 <SYSC_IDLE_NO>,
2021 <SYSC_IDLE_SMART>,
2022 <SYSC_IDLE_SMART_WKUP>;
2023 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
2024 clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
2025 clock-names = "fck";
2026 #address-cells = <1>;
2027 #size-cells = <1>;
2028 ranges = <0x0 0xba000 0x1000>;
2030 mcspi4: spi@0 {
2031 compatible = "ti,omap4-mcspi";
2032 reg = <0x0 0x200>;
2033 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036 ti,spi-num-cs = <1>;
2037 dmas = <&sdma 70>, <&sdma 71>;
2038 dma-names = "tx0", "rx0";
2039 };
2040 };
2042 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2043 compatible = "ti,sysc-omap4", "ti,sysc";
2044 reg = <0xd1000 0x4>,
2045 <0xd1010 0x4>;
2046 reg-names = "rev", "sysc";
2047 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2048 SYSC_OMAP4_SOFTRESET)>;
2049 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2050 <SYSC_IDLE_NO>,
2051 <SYSC_IDLE_SMART>,
2052 <SYSC_IDLE_SMART_WKUP>;
2053 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2054 <SYSC_IDLE_NO>,
2055 <SYSC_IDLE_SMART>,
2056 <SYSC_IDLE_SMART_WKUP>;
2057 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
2058 clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
2059 clock-names = "fck";
2060 #address-cells = <1>;
2061 #size-cells = <1>;
2062 ranges = <0x0 0xd1000 0x1000>;
2064 mmc4: mmc@0 {
2065 compatible = "ti,omap4-hsmmc";
2066 reg = <0x0 0x400>;
2067 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2068 ti,needs-special-reset;
2069 dmas = <&sdma 57>, <&sdma 58>;
2070 dma-names = "tx", "rx";
2071 };
2072 };
2074 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2075 compatible = "ti,sysc-omap4", "ti,sysc";
2076 reg = <0xd5000 0x4>,
2077 <0xd5010 0x4>;
2078 reg-names = "rev", "sysc";
2079 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2080 SYSC_OMAP4_SOFTRESET)>;
2081 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2082 <SYSC_IDLE_NO>,
2083 <SYSC_IDLE_SMART>,
2084 <SYSC_IDLE_SMART_WKUP>;
2085 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2086 <SYSC_IDLE_NO>,
2087 <SYSC_IDLE_SMART>,
2088 <SYSC_IDLE_SMART_WKUP>;
2089 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
2090 clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
2091 clock-names = "fck";
2092 #address-cells = <1>;
2093 #size-cells = <1>;
2094 ranges = <0x0 0xd5000 0x1000>;
2096 mmc5: mmc@0 {
2097 compatible = "ti,omap4-hsmmc";
2098 reg = <0x0 0x400>;
2099 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2100 ti,needs-special-reset;
2101 dmas = <&sdma 59>, <&sdma 60>;
2102 dma-names = "tx", "rx";
2103 };
2104 };
2105 };
2107 segment@200000 { /* 0x48200000 */
2108 compatible = "simple-bus";
2109 #address-cells = <1>;
2110 #size-cells = <1>;
2111 };
2112 };
2114 &l4_wkup { /* 0x4ae00000 */
2115 compatible = "ti,omap5-l4-wkup", "simple-bus";
2116 reg = <0x4ae00000 0x800>,
2117 <0x4ae00800 0x800>,
2118 <0x4ae01000 0x1000>;
2119 reg-names = "ap", "la", "ia0";
2120 #address-cells = <1>;
2121 #size-cells = <1>;
2122 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
2123 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
2124 <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
2126 segment@0 { /* 0x4ae00000 */
2127 compatible = "simple-bus";
2128 #address-cells = <1>;
2129 #size-cells = <1>;
2130 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2131 <0x00001000 0x00001000 0x001000>, /* ap 1 */
2132 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2133 <0x00006000 0x00006000 0x002000>, /* ap 3 */
2134 <0x00008000 0x00008000 0x001000>, /* ap 4 */
2135 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
2136 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
2137 <0x00004000 0x00004000 0x001000>, /* ap 17 */
2138 <0x00005000 0x00005000 0x001000>, /* ap 18 */
2139 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
2140 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
2142 target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
2143 compatible = "ti,sysc-omap2", "ti,sysc";
2144 ti,hwmods = "counter_32k";
2145 reg = <0x4000 0x4>,
2146 <0x4010 0x4>;
2147 reg-names = "rev", "sysc";
2148 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2149 <SYSC_IDLE_NO>;
2150 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
2151 clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
2152 clock-names = "fck";
2153 #address-cells = <1>;
2154 #size-cells = <1>;
2155 ranges = <0x0 0x4000 0x1000>;
2157 counter32k: counter@0 {
2158 compatible = "ti,omap-counter32k";
2159 reg = <0x0 0x40>;
2160 };
2161 };
2163 target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
2164 compatible = "ti,sysc-omap4", "ti,sysc";
2165 reg = <0x6000 0x4>;
2166 reg-names = "rev";
2167 #address-cells = <1>;
2168 #size-cells = <1>;
2169 ranges = <0x0 0x6000 0x2000>;
2171 prm: prm@0 {
2172 compatible = "ti,omap5-prm", "simple-bus";
2173 reg = <0x0 0x2000>;
2174 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2175 #address-cells = <1>;
2176 #size-cells = <1>;
2177 ranges = <0 0 0x2000>;
2179 prm_clocks: clocks {
2180 #address-cells = <1>;
2181 #size-cells = <0>;
2182 };
2184 prm_clockdomains: clockdomains {
2185 };
2186 };
2187 };
2189 target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
2190 compatible = "ti,sysc-omap4", "ti,sysc";
2191 reg = <0xa000 0x4>;
2192 reg-names = "rev";
2193 #address-cells = <1>;
2194 #size-cells = <1>;
2195 ranges = <0x0 0xa000 0x1000>;
2197 scrm: scrm@0 {
2198 compatible = "ti,omap5-scrm";
2199 reg = <0x0 0x1000>;
2201 scrm_clocks: clocks {
2202 #address-cells = <1>;
2203 #size-cells = <0>;
2204 };
2206 scrm_clockdomains: clockdomains {
2207 };
2208 };
2209 };
2211 target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
2212 compatible = "ti,sysc-omap4", "ti,sysc";
2213 reg = <0xc000 0x4>;
2214 reg-names = "rev";
2215 #address-cells = <1>;
2216 #size-cells = <1>;
2217 ranges = <0x0 0xc000 0x1000>;
2219 omap5_pmx_wkup: pinmux@840 {
2220 compatible = "ti,omap5-padconf",
2221 "pinctrl-single";
2222 reg = <0x840 0x003c>;
2223 #address-cells = <1>;
2224 #size-cells = <0>;
2225 #pinctrl-cells = <1>;
2226 #interrupt-cells = <1>;
2227 interrupt-controller;
2228 pinctrl-single,register-width = <16>;
2229 pinctrl-single,function-mask = <0x7fff>;
2230 };
2232 omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
2233 compatible = "ti,omap5-scm-wkup-pad-conf",
2234 "simple-bus";
2235 reg = <0xda0 0x60>;
2236 #address-cells = <1>;
2237 #size-cells = <1>;
2238 ranges = <0 0 0x60>;
2240 scm_wkup_pad_conf: scm_conf@0 {
2241 compatible = "syscon", "simple-bus";
2242 reg = <0x0 0x60>;
2243 #address-cells = <1>;
2244 #size-cells = <1>;
2245 ranges = <0 0x0 0x60>;
2247 scm_wkup_pad_conf_clocks: clocks@0 {
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2250 };
2251 };
2252 };
2253 };
2254 };
2256 segment@10000 { /* 0x4ae10000 */
2257 compatible = "simple-bus";
2258 #address-cells = <1>;
2259 #size-cells = <1>;
2260 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
2261 <0x00001000 0x00011000 0x001000>, /* ap 6 */
2262 <0x00004000 0x00014000 0x001000>, /* ap 7 */
2263 <0x00005000 0x00015000 0x001000>, /* ap 8 */
2264 <0x00008000 0x00018000 0x001000>, /* ap 9 */
2265 <0x00009000 0x00019000 0x001000>, /* ap 10 */
2266 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
2267 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
2269 target-module@0 { /* 0x4ae10000, ap 5 10.0 */
2270 compatible = "ti,sysc-omap2", "ti,sysc";
2271 reg = <0x0 0x4>,
2272 <0x10 0x4>,
2273 <0x114 0x4>;
2274 reg-names = "rev", "sysc", "syss";
2275 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2276 SYSC_OMAP2_SOFTRESET |
2277 SYSC_OMAP2_AUTOIDLE)>;
2278 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2279 <SYSC_IDLE_NO>,
2280 <SYSC_IDLE_SMART>,
2281 <SYSC_IDLE_SMART_WKUP>;
2282 ti,syss-mask = <1>;
2283 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
2284 clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
2285 <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
2286 clock-names = "fck", "dbclk";
2287 #address-cells = <1>;
2288 #size-cells = <1>;
2289 ranges = <0x0 0x0 0x1000>;
2291 gpio1: gpio@0 {
2292 compatible = "ti,omap4-gpio";
2293 reg = <0x0 0x200>;
2294 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2295 ti,gpio-always-on;
2296 gpio-controller;
2297 #gpio-cells = <2>;
2298 interrupt-controller;
2299 #interrupt-cells = <2>;
2300 };
2301 };
2303 target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
2304 compatible = "ti,sysc-omap2", "ti,sysc";
2305 reg = <0x4000 0x4>,
2306 <0x4010 0x4>,
2307 <0x4014 0x4>;
2308 reg-names = "rev", "sysc", "syss";
2309 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
2310 SYSC_OMAP2_SOFTRESET)>;
2311 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2312 <SYSC_IDLE_NO>,
2313 <SYSC_IDLE_SMART>,
2314 <SYSC_IDLE_SMART_WKUP>;
2315 ti,syss-mask = <1>;
2316 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
2317 clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
2318 clock-names = "fck";
2319 #address-cells = <1>;
2320 #size-cells = <1>;
2321 ranges = <0x0 0x4000 0x1000>;
2323 wdt2: wdt@0 {
2324 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
2325 reg = <0x0 0x80>;
2326 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2327 };
2328 };
2330 target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
2331 compatible = "ti,sysc-omap4-timer", "ti,sysc";
2332 ti,hwmods = "timer1";
2333 reg = <0x8000 0x4>,
2334 <0x8010 0x4>;
2335 reg-names = "rev", "sysc";
2336 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2337 SYSC_OMAP4_SOFTRESET)>;
2338 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2339 <SYSC_IDLE_NO>,
2340 <SYSC_IDLE_SMART>,
2341 <SYSC_IDLE_SMART_WKUP>;
2342 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
2343 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
2344 clock-names = "fck";
2345 #address-cells = <1>;
2346 #size-cells = <1>;
2347 ranges = <0x0 0x8000 0x1000>;
2349 timer1: timer@0 {
2350 compatible = "ti,omap5430-timer";
2351 reg = <0x0 0x80>;
2352 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
2353 clock-names = "fck";
2354 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2355 ti,timer-alwon;
2356 };
2357 };
2359 target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
2360 compatible = "ti,sysc-omap2", "ti,sysc";
2361 ti,hwmods = "kbd";
2362 reg = <0xc000 0x4>,
2363 <0xc010 0x4>;
2364 reg-names = "rev", "sysc";
2365 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
2366 SYSC_OMAP2_SOFTRESET)>;
2367 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2368 <SYSC_IDLE_NO>,
2369 <SYSC_IDLE_SMART>;
2370 /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
2371 clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
2372 clock-names = "fck";
2373 #address-cells = <1>;
2374 #size-cells = <1>;
2375 ranges = <0x0 0xc000 0x1000>;
2377 keypad: keypad@0 {
2378 compatible = "ti,omap4-keypad";
2379 reg = <0x0 0x400>;
2380 };
2381 };
2382 };
2384 segment@20000 { /* 0x4ae20000 */
2385 compatible = "simple-bus";
2386 #address-cells = <1>;
2387 #size-cells = <1>;
2388 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
2389 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
2390 <0x00000000 0x00020000 0x001000>, /* ap 21 */
2391 <0x00001000 0x00021000 0x001000>, /* ap 22 */
2392 <0x00002000 0x00022000 0x001000>, /* ap 23 */
2393 <0x00003000 0x00023000 0x001000>, /* ap 24 */
2394 <0x00007000 0x00027000 0x000400>, /* ap 25 */
2395 <0x00008000 0x00028000 0x000800>, /* ap 26 */
2396 <0x00009000 0x00029000 0x000100>, /* ap 27 */
2397 <0x00008800 0x00028800 0x000200>, /* ap 28 */
2398 <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
2400 target-module@0 { /* 0x4ae20000, ap 21 04.0 */
2401 compatible = "ti,sysc";
2402 status = "disabled";
2403 #address-cells = <1>;
2404 #size-cells = <1>;
2405 ranges = <0x0 0x0 0x1000>;
2406 };
2408 target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
2409 compatible = "ti,sysc";
2410 status = "disabled";
2411 #address-cells = <1>;
2412 #size-cells = <1>;
2413 ranges = <0x0 0x2000 0x1000>;
2414 };
2416 target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
2417 compatible = "ti,sysc";
2418 status = "disabled";
2419 #address-cells = <1>;
2420 #size-cells = <1>;
2421 ranges = <0x00000000 0x00006000 0x00001000>,
2422 <0x00001000 0x00007000 0x00000400>,
2423 <0x00002000 0x00008000 0x00000800>,
2424 <0x00002800 0x00008800 0x00000200>,
2425 <0x00002a00 0x00008a00 0x00000100>,
2426 <0x00003000 0x00009000 0x00000100>;
2427 };
2428 };
2429 };