1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Veyron Fievel Rev 0+ board device tree source
5 * Copyright 2016 Google, Inc
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
13 model = "Google Fievel";
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
19 "google,veyron", "rockchip,rk3288";
21 /delete-node/ bt-activity;
24 compatible = "regulator-fixed";
25 regulator-name = "vccsys";
31 * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
35 compatible = "regulator-fixed";
38 regulator-name = "vcc33_io";
41 vcc5_host1: vcc5-host1-regulator {
42 compatible = "regulator-fixed";
44 gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&hub_usb1_pwr_en>;
47 regulator-name = "vcc5_host1";
52 vcc5_host2: vcc5-host2-regulator {
53 compatible = "regulator-fixed";
55 gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&hub_usb2_pwr_en>;
58 regulator-name = "vcc5_host2";
63 vcc5v_otg: vcc5v-otg-regulator {
64 compatible = "regulator-fixed";
66 gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&usb_otg_pwr_en>;
69 regulator-name = "vcc5_otg";
74 ext_gmac: external-gmac-clock {
75 compatible = "fixed-clock";
77 clock-frequency = <125000000>;
78 clock-output-names = "ext_gmac";
85 assigned-clocks = <&cru SCLK_MAC>;
86 assigned-clock-parents = <&ext_gmac>;
87 clock_in_out = "input";
88 phy-handle = <ðphy>;
90 phy-supply = <&vcc33_lan>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
97 * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
98 * with a 30ms settling time.
100 snps,reset-gpio = <&gpio4 RK_PB0 0>;
101 snps,reset-active-low;
102 snps,reset-delays-us = <0 10000 30000>;
106 compatible = "snps,dwmac-mdio";
107 #address-cells = <1>;
110 ethphy: ethernet-phy@1 {
117 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
118 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
122 vcc6-supply = <&vcc33_sys>;
123 vcc10-supply = <&vcc33_sys>;
124 vcc11-supply = <&vcc_5v>;
125 vcc12-supply = <&vcc33_sys>;
128 /delete-node/ LDO_REG1;
131 * According to the schematic, vcc18_lcdt is for
134 vcc18_lcdt: LDO_REG2 {
137 regulator-min-microvolt = <1800000>;
138 regulator-max-microvolt = <1800000>;
139 regulator-name = "vdd18_lcdt";
140 regulator-state-mem {
141 regulator-off-in-suspend;
146 * This is not a pwren anymore, but the real power supply,
147 * vdd10_lcd for HDMI_AVDD_1V0
149 vdd10_lcd: LDO_REG7 {
152 regulator-min-microvolt = <1000000>;
153 regulator-max-microvolt = <1000000>;
154 regulator-name = "vdd10_lcd";
155 regulator-state-mem {
156 regulator-off-in-suspend;
161 vcc33_ccd: LDO_REG8 {
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-name = "vcc33_ccd";
167 regulator-state-mem {
168 regulator-off-in-suspend;
172 vcc33_lan: SWITCH_REG2 {
173 regulator-name = "vcc33_lan";
179 #address-cells = <1>;
183 compatible = "marvell,sd8897-bt";
185 interrupt-parent = <&gpio4>;
186 interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
187 marvell,wakeup-pin = /bits/ 16 <13>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&bt_host_wake_l>;
195 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&vcc50_hdmi_en>;
202 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&drv_5v>;
208 gpio-line-names = "PMIC_SLEEP_AP",
232 gpio-line-names = "CONFIG0",
255 gpio-line-names = "FLASH0_D0",
273 "FLASH0_CS2/EMMC_CMD",
275 "FLASH0_DQS/EMMC_CLKO",
293 gpio-line-names = "MAC_MDC",
331 gpio-line-names = "",
356 gpio-line-names = "I2S0_SCLK",
379 gpio-line-names = "LCD_BL_PWM",
408 gpio-line-names = "RAM_ID0",
422 pinctrl-names = "default", "sleep";
424 /* Common for sleep and wake, but no owners */
439 /* Common for sleep and wake, but no owners */
455 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
461 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
465 rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
469 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
474 vcc50_hdmi_en: vcc50-hdmi-en {
475 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
480 pwr_led1_on: pwr-led1-on {
481 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
484 pwr_led1_blink: pwr-led1-blink {
485 rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
491 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
495 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
500 usb_otg_ilim_sel: usb-otg-ilim-sel {
501 rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
504 usb_usb_ilim_sel: usb-usb-ilim-sel {
505 rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
510 hub_usb1_pwr_en: hub_usb1_pwr_en {
511 rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
514 hub_usb2_pwr_en: hub_usb2_pwr_en {
515 rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
518 usb_otg_pwr_en: usb_otg_pwr_en {
519 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;