arch/arm/boot/dts/rk3288-veyron-minnie.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Minnie Rev 0+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9 #include "rk3288-veyron-chromebook.dtsi"
  10
  11 / {
  12         model = "Google Minnie";
  13         compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
  14                      "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
  15                      "google,veyron-minnie-rev0", "google,veyron-minnie",
  16                      "google,veyron", "rockchip,rk3288";
  17
  18         volume_buttons: volume-buttons {
  19                 compatible = "gpio-keys";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&volum_down_l &volum_up_l>;
  22
  23                 volum_down {
  24                         label = "Volum_down";
  25                         gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
  26                         linux,code = <KEY_VOLUMEDOWN>;
  27                         debounce-interval = <100>;
  28                 };
  29
  30                 volum_up {
  31                         label = "Volum_up";
  32                         gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
  33                         linux,code = <KEY_VOLUMEUP>;
  34                         debounce-interval = <100>;
  35                 };
  36         };
  37 };
  38
  39 &backlight {
  40         /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
  41         brightness-levels = <0 3 255>;
  42         num-interpolated-steps = <252>;
  43 };
  44
  45 &i2c_tunnel {
  46         battery: bq27500@55 {
  47                 compatible = "ti,bq27500";
  48                 reg = <0x55>;
  49         };
  50 };
  51
  52 &i2c3 {
  53         status = "okay";
  54
  55         clock-frequency = <400000>;
  56         i2c-scl-falling-time-ns = <50>;
  57         i2c-scl-rising-time-ns = <300>;
  58
  59         touchscreen@10 {
  60                 compatible = "elan,ekth3500";
  61                 reg = <0x10>;
  62                 interrupt-parent = <&gpio2>;
  63                 interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&touch_int &touch_rst>;
  66                 reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
  67                 vcc33-supply = <&vcc33_touch>;
  68                 vccio-supply = <&vcc33_touch>;
  69         };
  70 };
  71
  72 &panel {
  73         compatible = "auo,b101ean01", "simple-panel";
  74
  75         /delete-node/ panel-timing;
  76
  77         panel-timing {
  78                 clock-frequency = <66666667>;
  79                 hactive = <1280>;
  80                 hfront-porch = <18>;
  81                 hback-porch = <21>;
  82                 hsync-len = <32>;
  83                 vactive = <800>;
  84                 vfront-porch = <4>;
  85                 vback-porch = <8>;
  86                 vsync-len = <18>;
  87         };
  88 };
  89
  90 &rk808 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
  93
  94         regulators {
  95                 vcc33_touch: LDO_REG2 {
  96                         regulator-min-microvolt = <3300000>;
  97                         regulator-max-microvolt = <3300000>;
  98                         regulator-name = "vcc33_touch";
  99                         regulator-state-mem {
 100                                 regulator-off-in-suspend;
 101                         };
 102                 };
 103
 104                 vcc5v_touch: SWITCH_REG2 {
 105                         regulator-name = "vcc5v_touch";
 106                         regulator-state-mem {
 107                                 regulator-off-in-suspend;
 108                         };
 109                 };
 110         };
 111 };
 112
 113 &sdmmc {
 114         disable-wp;
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
 117                         &sdmmc_bus4>;
 118 };
 119
 120 &vcc_5v {
 121         enable-active-high;
 122         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&drv_5v>;
 125 };
 126
 127 &vcc50_hdmi {
 128         enable-active-high;
 129         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&vcc50_hdmi_en>;
 132 };
 133
 134 &gpio0 {
 135         gpio-line-names = "PMIC_SLEEP_AP",
 136                           "DDRIO_PWROFF",
 137                           "DDRIO_RETEN",
 138                           "TS3A227E_INT_L",
 139                           "PMIC_INT_L",
 140                           "PWR_KEY_L",
 141                           "AP_LID_INT_L",
 142                           "EC_IN_RW",
 143
 144                           "AC_PRESENT_AP",
 145                           /*
 146                            * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
 147                            * it REC_MODE_L.
 148                            */
 149                           "RECOVERY_SW_L",
 150                           "OTP_OUT",
 151                           "HOST1_PWR_EN",
 152                           "USBOTG_PWREN_H",
 153                           "AP_WARM_RESET_H",
 154                           "nFALUT2",
 155                           "I2C0_SDA_PMIC",
 156
 157                           "I2C0_SCL_PMIC",
 158                           "SUSPEND_L",
 159                           "USB_INT";
 160 };
 161
 162 &gpio2 {
 163         gpio-line-names = "CONFIG0",
 164                           "CONFIG1",
 165                           "CONFIG2",
 166                           "",
 167                           "",
 168                           "",
 169                           "",
 170                           "CONFIG3",
 171
 172                           "PROCHOT#",
 173                           "EMMC_RST_L",
 174                           "",
 175                           "",
 176                           "BL_PWR_EN",
 177                           "AVDD_1V8_DISP_EN",
 178                           "TOUCH_INT",
 179                           "TOUCH_RST",
 180
 181                           "I2C3_SCL_TP",
 182                           "I2C3_SDA_TP";
 183 };
 184
 185 &gpio3 {
 186         gpio-line-names = "FLASH0_D0",
 187                           "FLASH0_D1",
 188                           "FLASH0_D2",
 189                           "FLASH0_D3",
 190                           "FLASH0_D4",
 191                           "FLASH0_D5",
 192                           "FLASH0_D6",
 193                           "FLASH0_D7",
 194
 195                           "",
 196                           "",
 197                           "",
 198                           "",
 199                           "",
 200                           "",
 201                           "",
 202                           "",
 203
 204                           "FLASH0_CS2/EMMC_CMD",
 205                           "",
 206                           "FLASH0_DQS/EMMC_CLKO";
 207 };
 208
 209 &gpio4 {
 210         gpio-line-names = "",
 211                           "",
 212                           "",
 213                           "",
 214                           "",
 215                           "",
 216                           "",
 217                           "",
 218
 219                           "",
 220                           "",
 221                           "",
 222                           "",
 223                           "",
 224                           "",
 225                           "",
 226                           "",
 227
 228                           "UART0_RXD",
 229                           "UART0_TXD",
 230                           "UART0_CTS",
 231                           "UART0_RTS",
 232                           "SDIO0_D0",
 233                           "SDIO0_D1",
 234                           "SDIO0_D2",
 235                           "SDIO0_D3",
 236
 237                           "SDIO0_CMD",
 238                           "SDIO0_CLK",
 239                           "dev_wake",
 240                           "",
 241                           "WIFI_ENABLE_H",
 242                           "BT_ENABLE_L",
 243                           "WIFI_HOST_WAKE",
 244                           "BT_HOST_WAKE";
 245 };
 246
 247 &gpio5 {
 248         gpio-line-names = "",
 249                           "",
 250                           "",
 251                           "",
 252                           "",
 253                           "",
 254                           "",
 255                           "",
 256
 257                           "",
 258                           "",
 259                           "Volum_Up#",
 260                           "Volum_Down#",
 261                           "SPI0_CLK",
 262                           "SPI0_CS0",
 263                           "SPI0_TXD",
 264                           "SPI0_RXD",
 265
 266                           "",
 267                           "",
 268                           "",
 269                           "VCC50_HDMI_EN";
 270 };
 271
 272 &gpio6 {
 273         gpio-line-names = "I2S0_SCLK",
 274                           "I2S0_LRCK_RX",
 275                           "I2S0_LRCK_TX",
 276                           "I2S0_SDI",
 277                           "I2S0_SDO0",
 278                           "HP_DET_H",
 279                           "",
 280                           "INT_CODEC",
 281
 282                           "I2S0_CLK",
 283                           "I2C2_SDA",
 284                           "I2C2_SCL",
 285                           "MICDET",
 286                           "",
 287                           "",
 288                           "",
 289                           "",
 290
 291                           "SDMMC_D0",
 292                           "SDMMC_D1",
 293                           "SDMMC_D2",
 294                           "SDMMC_D3",
 295                           "SDMMC_CLK",
 296                           "SDMMC_CMD";
 297 };
 298
 299 &gpio7 {
 300         gpio-line-names = "LCDC_BL",
 301                           "PWM_LOG",
 302                           "BL_EN",
 303                           "TRACKPAD_INT",
 304                           "TPM_INT_H",
 305                           "SDMMC_DET_L",
 306                           /*
 307                            * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
 308                            * it FW_WP_AP.
 309                            */
 310                           "AP_FLASH_WP_L",
 311                           "EC_INT",
 312
 313                           "CPU_NMI",
 314                           "DVS_OK",
 315                           "SDMMC_WP",
 316                           "EDP_HPD",
 317                           "DVS1",
 318                           "nFALUT1",
 319                           "LCD_EN",
 320                           "DVS2",
 321
 322                           "VCC5V_GOOD_H",
 323                           "I2C4_SDA_TP",
 324                           "I2C4_SCL_TP",
 325                           "I2C5_SDA_HDMI",
 326                           "I2C5_SCL_HDMI",
 327                           "5V_DRV",
 328                           "UART2_RXD",
 329                           "UART2_TXD";
 330 };
 331
 332 &gpio8 {
 333         gpio-line-names = "RAM_ID0",
 334                           "RAM_ID1",
 335                           "RAM_ID2",
 336                           "RAM_ID3",
 337                           "I2C1_SDA_TPM",
 338                           "I2C1_SCL_TPM",
 339                           "SPI2_CLK",
 340                           "SPI2_CS0",
 341
 342                           "SPI2_RXD",
 343                           "SPI2_TXD";
 344 };
 345
 346 &pinctrl {
 347         buck-5v {
 348                 drv_5v: drv-5v {
 349                         rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 350                 };
 351         };
 352
 353         buttons {
 354                 volum_down_l: volum-down-l {
 355                         rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
 356                 };
 357
 358                 volum_up_l: volum-up-l {
 359                         rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
 360                 };
 361         };
 362
 363         hdmi {
 364                 vcc50_hdmi_en: vcc50-hdmi-en {
 365                         rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 366                 };
 367         };
 368
 369         pmic {
 370                 dvs_1: dvs-1 {
 371                         rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
 372                 };
 373
 374                 dvs_2: dvs-2 {
 375                         rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
 376                 };
 377         };
 378
 379         prochot {
 380                 gpio_prochot: gpio-prochot {
 381                         rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 382                 };
 383         };
 384
 385         touchscreen {
 386                 touch_int: touch-int {
 387                         rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 388                 };
 389
 390                 touch_rst: touch-rst {
 391                         rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 392                 };
 393         };
 394 };