| blob | f770aace0efd6c8602c7d964926f47a7e463d8e8 |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
4 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
5 *
6 * Copyright (C) 2013 Atmel,
7 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
8 */
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 serial5 = &uart0;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 i2c2 = &i2c2;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a5";
49 reg = <0x0>;
50 };
51 };
53 pmu {
54 compatible = "arm,cortex-a5-pmu";
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
56 };
58 memory {
59 device_type = "memory";
60 reg = <0x20000000 0x8000000>;
61 };
63 clocks {
64 slow_xtal: slow_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
70 main_xtal: main_xtal {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <0>;
74 };
76 adc_op_clk: adc_op_clk{
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <1000000>;
80 };
81 };
83 sram: sram@300000 {
84 compatible = "mmio-sram";
85 reg = <0x00300000 0x20000>;
86 };
88 ahb {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
94 apb {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
100 mmc0: mmc@f0000000 {
101 compatible = "atmel,hsmci";
102 reg = <0xf0000000 0x600>;
103 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
104 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
105 dma-names = "rxtx";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
108 status = "disabled";
109 #address-cells = <1>;
110 #size-cells = <0>;
111 clocks = <&mci0_clk>;
112 clock-names = "mci_clk";
113 };
115 spi0: spi@f0004000 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "atmel,at91rm9200-spi";
119 reg = <0xf0004000 0x100>;
120 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
121 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
122 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
123 dma-names = "tx", "rx";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi0>;
126 clocks = <&spi0_clk>;
127 clock-names = "spi_clk";
128 status = "disabled";
129 };
131 ssc0: ssc@f0008000 {
132 compatible = "atmel,at91sam9g45-ssc";
133 reg = <0xf0008000 0x4000>;
134 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
135 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
136 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
137 dma-names = "tx", "rx";
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
140 clocks = <&ssc0_clk>;
141 clock-names = "pclk";
142 status = "disabled";
143 };
145 tcb0: timer@f0010000 {
146 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0xf0010000 0x100>;
150 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
151 clocks = <&tcb0_clk>, <&clk32k>;
152 clock-names = "t0_clk", "slow_clk";
153 };
155 i2c0: i2c@f0014000 {
156 compatible = "atmel,at91sam9x5-i2c";
157 reg = <0xf0014000 0x4000>;
158 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
159 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
160 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
161 dma-names = "tx", "rx";
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c0>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 clocks = <&twi0_clk>;
167 status = "disabled";
168 };
170 i2c1: i2c@f0018000 {
171 compatible = "atmel,at91sam9x5-i2c";
172 reg = <0xf0018000 0x4000>;
173 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
174 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
175 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
176 dma-names = "tx", "rx";
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c1>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&twi1_clk>;
182 status = "disabled";
183 };
185 usart0: serial@f001c000 {
186 compatible = "atmel,at91sam9260-usart";
187 reg = <0xf001c000 0x100>;
188 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
189 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
190 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
191 dma-names = "tx", "rx";
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_usart0>;
194 clocks = <&usart0_clk>;
195 clock-names = "usart";
196 status = "disabled";
197 };
199 usart1: serial@f0020000 {
200 compatible = "atmel,at91sam9260-usart";
201 reg = <0xf0020000 0x100>;
202 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
203 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
204 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
205 dma-names = "tx", "rx";
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_usart1>;
208 clocks = <&usart1_clk>;
209 clock-names = "usart";
210 status = "disabled";
211 };
213 uart0: serial@f0024000 {
214 compatible = "atmel,at91sam9260-usart";
215 reg = <0xf0024000 0x100>;
216 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_uart0>;
219 clocks = <&uart0_clk>;
220 clock-names = "usart";
221 status = "disabled";
222 };
224 pwm0: pwm@f002c000 {
225 compatible = "atmel,sama5d3-pwm";
226 reg = <0xf002c000 0x300>;
227 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
228 #pwm-cells = <3>;
229 clocks = <&pwm_clk>;
230 status = "disabled";
231 };
233 isi: isi@f0034000 {
234 compatible = "atmel,at91sam9g45-isi";
235 reg = <0xf0034000 0x4000>;
236 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_isi_data_0_7>;
239 clocks = <&isi_clk>;
240 clock-names = "isi_clk";
241 status = "disabled";
242 port {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 };
246 };
248 sfr: sfr@f0038000 {
249 compatible = "atmel,sama5d3-sfr", "syscon";
250 reg = <0xf0038000 0x60>;
251 };
253 mmc1: mmc@f8000000 {
254 compatible = "atmel,hsmci";
255 reg = <0xf8000000 0x600>;
256 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
257 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
258 dma-names = "rxtx";
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
261 status = "disabled";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 clocks = <&mci1_clk>;
265 clock-names = "mci_clk";
266 };
268 spi1: spi@f8008000 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 compatible = "atmel,at91rm9200-spi";
272 reg = <0xf8008000 0x100>;
273 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
274 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
275 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
276 dma-names = "tx", "rx";
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_spi1>;
279 clocks = <&spi1_clk>;
280 clock-names = "spi_clk";
281 status = "disabled";
282 };
284 ssc1: ssc@f800c000 {
285 compatible = "atmel,at91sam9g45-ssc";
286 reg = <0xf800c000 0x4000>;
287 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
288 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
289 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
290 dma-names = "tx", "rx";
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
293 clocks = <&ssc1_clk>;
294 clock-names = "pclk";
295 status = "disabled";
296 };
298 adc0: adc@f8018000 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "atmel,at91sam9x5-adc";
302 reg = <0xf8018000 0x100>;
303 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
304 pinctrl-names = "default";
305 pinctrl-0 = <
306 &pinctrl_adc0_adtrg
307 &pinctrl_adc0_ad0
308 &pinctrl_adc0_ad1
309 &pinctrl_adc0_ad2
310 &pinctrl_adc0_ad3
311 &pinctrl_adc0_ad4
312 &pinctrl_adc0_ad5
313 &pinctrl_adc0_ad6
314 &pinctrl_adc0_ad7
315 &pinctrl_adc0_ad8
316 &pinctrl_adc0_ad9
317 &pinctrl_adc0_ad10
318 &pinctrl_adc0_ad11
319 >;
320 clocks = <&adc_clk>,
321 <&adc_op_clk>;
322 clock-names = "adc_clk", "adc_op_clk";
323 atmel,adc-channels-used = <0xfff>;
324 atmel,adc-startup-time = <40>;
325 atmel,adc-use-external-triggers;
326 atmel,adc-vref = <3000>;
327 atmel,adc-res = <10 12>;
328 atmel,adc-sample-hold-time = <11>;
329 atmel,adc-res-names = "lowres", "highres";
330 status = "disabled";
332 trigger0 {
333 trigger-name = "external-rising";
334 trigger-value = <0x1>;
335 trigger-external;
336 };
337 trigger1 {
338 trigger-name = "external-falling";
339 trigger-value = <0x2>;
340 trigger-external;
341 };
342 trigger2 {
343 trigger-name = "external-any";
344 trigger-value = <0x3>;
345 trigger-external;
346 };
347 trigger3 {
348 trigger-name = "continuous";
349 trigger-value = <0x6>;
350 };
351 };
353 i2c2: i2c@f801c000 {
354 compatible = "atmel,at91sam9x5-i2c";
355 reg = <0xf801c000 0x4000>;
356 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
357 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
358 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
359 dma-names = "tx", "rx";
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c2>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clocks = <&twi2_clk>;
365 status = "disabled";
366 };
368 usart2: serial@f8020000 {
369 compatible = "atmel,at91sam9260-usart";
370 reg = <0xf8020000 0x100>;
371 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
372 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
373 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
374 dma-names = "tx", "rx";
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usart2>;
377 clocks = <&usart2_clk>;
378 clock-names = "usart";
379 status = "disabled";
380 };
382 usart3: serial@f8024000 {
383 compatible = "atmel,at91sam9260-usart";
384 reg = <0xf8024000 0x100>;
385 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
386 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
387 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
388 dma-names = "tx", "rx";
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usart3>;
391 clocks = <&usart3_clk>;
392 clock-names = "usart";
393 status = "disabled";
394 };
396 sha@f8034000 {
397 compatible = "atmel,at91sam9g46-sha";
398 reg = <0xf8034000 0x100>;
399 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
400 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
401 dma-names = "tx";
402 clocks = <&sha_clk>;
403 clock-names = "sha_clk";
404 };
406 aes@f8038000 {
407 compatible = "atmel,at91sam9g46-aes";
408 reg = <0xf8038000 0x100>;
409 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
410 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
411 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
412 dma-names = "tx", "rx";
413 clocks = <&aes_clk>;
414 clock-names = "aes_clk";
415 };
417 tdes@f803c000 {
418 compatible = "atmel,at91sam9g46-tdes";
419 reg = <0xf803c000 0x100>;
420 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
421 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
422 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
423 dma-names = "tx", "rx";
424 clocks = <&tdes_clk>;
425 clock-names = "tdes_clk";
426 };
428 trng@f8040000 {
429 compatible = "atmel,at91sam9g45-trng";
430 reg = <0xf8040000 0x100>;
431 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
432 clocks = <&trng_clk>;
433 };
435 hsmc: hsmc@ffffc000 {
436 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
437 reg = <0xffffc000 0x1000>;
438 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
439 clocks = <&hsmc_clk>;
440 #address-cells = <1>;
441 #size-cells = <1>;
442 ranges;
444 pmecc: ecc-engine@ffffc070 {
445 compatible = "atmel,at91sam9g45-pmecc";
446 reg = <0xffffc070 0x490>,
447 <0xffffc500 0x100>;
448 };
449 };
451 dma0: dma-controller@ffffe600 {
452 compatible = "atmel,at91sam9g45-dma";
453 reg = <0xffffe600 0x200>;
454 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
455 #dma-cells = <2>;
456 clocks = <&dma0_clk>;
457 clock-names = "dma_clk";
458 };
460 dma1: dma-controller@ffffe800 {
461 compatible = "atmel,at91sam9g45-dma";
462 reg = <0xffffe800 0x200>;
463 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
464 #dma-cells = <2>;
465 clocks = <&dma1_clk>;
466 clock-names = "dma_clk";
467 };
469 ramc0: ramc@ffffea00 {
470 compatible = "atmel,sama5d3-ddramc";
471 reg = <0xffffea00 0x200>;
472 clocks = <&ddrck>, <&mpddr_clk>;
473 clock-names = "ddrck", "mpddr";
474 };
476 dbgu: serial@ffffee00 {
477 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
478 reg = <0xffffee00 0x200>;
479 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
480 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
481 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
482 dma-names = "tx", "rx";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_dbgu>;
485 clocks = <&dbgu_clk>;
486 clock-names = "usart";
487 status = "disabled";
488 };
490 aic: interrupt-controller@fffff000 {
491 #interrupt-cells = <3>;
492 compatible = "atmel,sama5d3-aic";
493 interrupt-controller;
494 reg = <0xfffff000 0x200>;
495 atmel,external-irqs = <47>;
496 };
498 pinctrl: pinctrl@fffff200 {
499 #address-cells = <1>;
500 #size-cells = <1>;
501 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
502 ranges = <0xfffff200 0xfffff200 0xa00>;
503 atmel,mux-mask = <
504 /* A B C */
505 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
506 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
507 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
508 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
509 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
510 >;
512 /* shared pinctrl settings */
513 adc0 {
514 pinctrl_adc0_adtrg: adc0_adtrg {
515 atmel,pins =
516 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
517 };
518 pinctrl_adc0_ad0: adc0_ad0 {
519 atmel,pins =
520 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
521 };
522 pinctrl_adc0_ad1: adc0_ad1 {
523 atmel,pins =
524 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
525 };
526 pinctrl_adc0_ad2: adc0_ad2 {
527 atmel,pins =
528 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
529 };
530 pinctrl_adc0_ad3: adc0_ad3 {
531 atmel,pins =
532 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
533 };
534 pinctrl_adc0_ad4: adc0_ad4 {
535 atmel,pins =
536 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
537 };
538 pinctrl_adc0_ad5: adc0_ad5 {
539 atmel,pins =
540 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
541 };
542 pinctrl_adc0_ad6: adc0_ad6 {
543 atmel,pins =
544 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
545 };
546 pinctrl_adc0_ad7: adc0_ad7 {
547 atmel,pins =
548 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
549 };
550 pinctrl_adc0_ad8: adc0_ad8 {
551 atmel,pins =
552 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
553 };
554 pinctrl_adc0_ad9: adc0_ad9 {
555 atmel,pins =
556 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
557 };
558 pinctrl_adc0_ad10: adc0_ad10 {
559 atmel,pins =
560 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
561 };
562 pinctrl_adc0_ad11: adc0_ad11 {
563 atmel,pins =
564 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
565 };
566 };
568 dbgu {
569 pinctrl_dbgu: dbgu-0 {
570 atmel,pins =
571 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
572 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
573 };
574 };
576 ebi {
577 pinctrl_ebi_addr: ebi-addr-0 {
578 atmel,pins =
579 <AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
580 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
581 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
582 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
583 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
584 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
585 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
586 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
587 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
588 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
589 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
590 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
591 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
592 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
593 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
594 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
595 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
596 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
597 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
598 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
599 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
600 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
601 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
602 };
604 pinctrl_ebi_nand_addr: ebi-addr-1 {
605 atmel,pins =
606 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
607 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
608 };
610 pinctrl_ebi_cs0: ebi-cs0-0 {
611 atmel,pins =
612 <AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
613 };
615 pinctrl_ebi_cs1: ebi-cs1-0 {
616 atmel,pins =
617 <AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
618 };
620 pinctrl_ebi_cs2: ebi-cs2-0 {
621 atmel,pins =
622 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
623 };
625 pinctrl_ebi_nwait: ebi-nwait-0 {
626 atmel,pins =
627 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
628 };
630 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
631 atmel,pins =
632 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
633 };
634 };
636 i2c0 {
637 pinctrl_i2c0: i2c0-0 {
638 atmel,pins =
639 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
640 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
641 };
642 };
644 i2c1 {
645 pinctrl_i2c1: i2c1-0 {
646 atmel,pins =
647 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
648 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
649 };
650 };
652 i2c2 {
653 pinctrl_i2c2: i2c2-0 {
654 atmel,pins =
655 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
656 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
657 };
658 };
660 isi {
661 pinctrl_isi_data_0_7: isi-0-data-0-7 {
662 atmel,pins =
663 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
664 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
665 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
666 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
667 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
668 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
669 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
670 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
671 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
672 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
673 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
674 };
676 pinctrl_isi_data_8_9: isi-0-data-8-9 {
677 atmel,pins =
678 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
679 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
680 };
682 pinctrl_isi_data_10_11: isi-0-data-10-11 {
683 atmel,pins =
684 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
685 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
686 };
687 };
689 mmc0 {
690 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
691 atmel,pins =
692 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
693 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
694 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
695 };
696 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
697 atmel,pins =
698 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
699 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
700 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
701 };
702 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
703 atmel,pins =
704 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
705 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
706 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
707 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
708 };
709 };
711 mmc1 {
712 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
713 atmel,pins =
714 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
715 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
716 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
717 };
718 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
719 atmel,pins =
720 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
721 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
722 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
723 };
724 };
726 nand0 {
727 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
728 atmel,pins =
729 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
730 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
731 };
732 };
734 pwm0 {
735 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
736 atmel,pins =
737 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
738 };
739 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
740 atmel,pins =
741 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
742 };
743 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
744 atmel,pins =
745 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
746 };
747 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
748 atmel,pins =
749 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
750 };
752 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
753 atmel,pins =
754 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
755 };
756 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
757 atmel,pins =
758 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
759 };
760 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
761 atmel,pins =
762 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
763 };
764 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
765 atmel,pins =
766 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
767 };
768 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
769 atmel,pins =
770 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
771 };
772 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
773 atmel,pins =
774 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
775 };
777 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
778 atmel,pins =
779 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
780 };
781 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
782 atmel,pins =
783 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
784 };
785 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
786 atmel,pins =
787 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
788 };
789 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
790 atmel,pins =
791 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
792 };
794 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
795 atmel,pins =
796 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
797 };
798 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
799 atmel,pins =
800 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
801 };
802 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
803 atmel,pins =
804 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
805 };
806 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
807 atmel,pins =
808 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
809 };
810 };
812 spi0 {
813 pinctrl_spi0: spi0-0 {
814 atmel,pins =
815 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
816 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
817 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
818 };
819 };
821 spi1 {
822 pinctrl_spi1: spi1-0 {
823 atmel,pins =
824 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
825 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
826 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
827 };
828 };
830 ssc0 {
831 pinctrl_ssc0_tx: ssc0_tx {
832 atmel,pins =
833 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
834 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
835 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
836 };
838 pinctrl_ssc0_rx: ssc0_rx {
839 atmel,pins =
840 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
841 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
842 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
843 };
844 };
846 ssc1 {
847 pinctrl_ssc1_tx: ssc1_tx {
848 atmel,pins =
849 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
850 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
851 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
852 };
854 pinctrl_ssc1_rx: ssc1_rx {
855 atmel,pins =
856 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
857 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
858 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
859 };
860 };
862 uart0 {
863 pinctrl_uart0: uart0-0 {
864 atmel,pins =
865 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with PWMFI2, ISI_D8 */
866 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
867 };
868 };
870 uart1 {
871 pinctrl_uart1: uart1-0 {
872 atmel,pins =
873 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with TWD0, ISI_VSYNC */
874 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
875 };
876 };
878 usart0 {
879 pinctrl_usart0: usart0-0 {
880 atmel,pins =
881 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
882 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
883 };
885 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
886 atmel,pins =
887 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
888 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
889 };
890 };
892 usart1 {
893 pinctrl_usart1: usart1-0 {
894 atmel,pins =
895 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
896 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
897 };
899 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
900 atmel,pins =
901 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
902 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
903 };
904 };
906 usart2 {
907 pinctrl_usart2: usart2-0 {
908 atmel,pins =
909 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A25 */
910 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts NCS0 */
911 };
913 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
914 atmel,pins =
915 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
916 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
917 };
918 };
920 usart3 {
921 pinctrl_usart3: usart3-0 {
922 atmel,pins =
923 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A18 */
924 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with A19 */
925 };
927 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
928 atmel,pins =
929 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
930 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
931 };
932 };
935 pioA: gpio@fffff200 {
936 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
937 reg = <0xfffff200 0x100>;
938 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
939 #gpio-cells = <2>;
940 gpio-controller;
941 interrupt-controller;
942 #interrupt-cells = <2>;
943 clocks = <&pioA_clk>;
944 };
946 pioB: gpio@fffff400 {
947 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
948 reg = <0xfffff400 0x100>;
949 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
950 #gpio-cells = <2>;
951 gpio-controller;
952 interrupt-controller;
953 #interrupt-cells = <2>;
954 clocks = <&pioB_clk>;
955 };
957 pioC: gpio@fffff600 {
958 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
959 reg = <0xfffff600 0x100>;
960 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
961 #gpio-cells = <2>;
962 gpio-controller;
963 interrupt-controller;
964 #interrupt-cells = <2>;
965 clocks = <&pioC_clk>;
966 };
968 pioD: gpio@fffff800 {
969 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
970 reg = <0xfffff800 0x100>;
971 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
972 #gpio-cells = <2>;
973 gpio-controller;
974 interrupt-controller;
975 #interrupt-cells = <2>;
976 clocks = <&pioD_clk>;
977 };
979 pioE: gpio@fffffa00 {
980 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
981 reg = <0xfffffa00 0x100>;
982 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
983 #gpio-cells = <2>;
984 gpio-controller;
985 interrupt-controller;
986 #interrupt-cells = <2>;
987 clocks = <&pioE_clk>;
988 };
989 };
991 pmc: pmc@fffffc00 {
992 compatible = "atmel,sama5d3-pmc", "syscon";
993 reg = <0xfffffc00 0x120>;
994 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
995 interrupt-controller;
996 #address-cells = <1>;
997 #size-cells = <0>;
998 #interrupt-cells = <1>;
1000 main_rc_osc: main_rc_osc {
1001 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
1002 #clock-cells = <0>;
1003 interrupt-parent = <&pmc>;
1004 interrupts = <AT91_PMC_MOSCRCS>;
1005 clock-frequency = <12000000>;
1006 clock-accuracy = <50000000>;
1007 };
1009 main_osc: main_osc {
1010 compatible = "atmel,at91rm9200-clk-main-osc";
1011 #clock-cells = <0>;
1012 interrupt-parent = <&pmc>;
1013 interrupts = <AT91_PMC_MOSCS>;
1014 clocks = <&main_xtal>;
1015 };
1017 main: mainck {
1018 compatible = "atmel,at91sam9x5-clk-main";
1019 #clock-cells = <0>;
1020 interrupt-parent = <&pmc>;
1021 interrupts = <AT91_PMC_MOSCSELS>;
1022 clocks = <&main_rc_osc &main_osc>;
1023 };
1025 plla: pllack {
1026 compatible = "atmel,sama5d3-clk-pll";
1027 #clock-cells = <0>;
1028 interrupt-parent = <&pmc>;
1029 interrupts = <AT91_PMC_LOCKA>;
1030 clocks = <&main>;
1031 reg = <0>;
1032 atmel,clk-input-range = <8000000 50000000>;
1033 #atmel,pll-clk-output-range-cells = <4>;
1034 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
1035 };
1037 plladiv: plladivck {
1038 compatible = "atmel,at91sam9x5-clk-plldiv";
1039 #clock-cells = <0>;
1040 clocks = <&plla>;
1041 };
1043 utmi: utmick {
1044 compatible = "atmel,at91sam9x5-clk-utmi";
1045 #clock-cells = <0>;
1046 interrupt-parent = <&pmc>;
1047 interrupts = <AT91_PMC_LOCKU>;
1048 clocks = <&main>;
1049 };
1051 mck: masterck {
1052 compatible = "atmel,at91sam9x5-clk-master";
1053 #clock-cells = <0>;
1054 interrupt-parent = <&pmc>;
1055 interrupts = <AT91_PMC_MCKRDY>;
1056 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
1057 atmel,clk-output-range = <0 166000000>;
1058 atmel,clk-divisors = <1 2 4 3>;
1059 };
1061 usb: usbck {
1062 compatible = "atmel,at91sam9x5-clk-usb";
1063 #clock-cells = <0>;
1064 clocks = <&plladiv>, <&utmi>;
1065 };
1067 prog: progck {
1068 compatible = "atmel,at91sam9x5-clk-programmable";
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 interrupt-parent = <&pmc>;
1072 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
1074 prog0: prog0 {
1075 #clock-cells = <0>;
1076 reg = <0>;
1077 interrupts = <AT91_PMC_PCKRDY(0)>;
1078 };
1080 prog1: prog1 {
1081 #clock-cells = <0>;
1082 reg = <1>;
1083 interrupts = <AT91_PMC_PCKRDY(1)>;
1084 };
1086 prog2: prog2 {
1087 #clock-cells = <0>;
1088 reg = <2>;
1089 interrupts = <AT91_PMC_PCKRDY(2)>;
1090 };
1091 };
1093 smd: smdclk {
1094 compatible = "atmel,at91sam9x5-clk-smd";
1095 #clock-cells = <0>;
1096 clocks = <&plladiv>, <&utmi>;
1097 };
1099 systemck {
1100 compatible = "atmel,at91rm9200-clk-system";
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1104 ddrck: ddrck {
1105 #clock-cells = <0>;
1106 reg = <2>;
1107 clocks = <&mck>;
1108 };
1110 smdck: smdck {
1111 #clock-cells = <0>;
1112 reg = <4>;
1113 clocks = <&smd>;
1114 };
1116 uhpck: uhpck {
1117 #clock-cells = <0>;
1118 reg = <6>;
1119 clocks = <&usb>;
1120 };
1122 udpck: udpck {
1123 #clock-cells = <0>;
1124 reg = <7>;
1125 clocks = <&usb>;
1126 };
1128 pck0: pck0 {
1129 #clock-cells = <0>;
1130 reg = <8>;
1131 clocks = <&prog0>;
1132 };
1134 pck1: pck1 {
1135 #clock-cells = <0>;
1136 reg = <9>;
1137 clocks = <&prog1>;
1138 };
1140 pck2: pck2 {
1141 #clock-cells = <0>;
1142 reg = <10>;
1143 clocks = <&prog2>;
1144 };
1145 };
1147 periphck {
1148 compatible = "atmel,at91sam9x5-clk-peripheral";
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 clocks = <&mck>;
1153 dbgu_clk: dbgu_clk {
1154 #clock-cells = <0>;
1155 reg = <2>;
1156 };
1158 hsmc_clk: hsmc_clk {
1159 #clock-cells = <0>;
1160 reg = <5>;
1161 };
1163 pioA_clk: pioA_clk {
1164 #clock-cells = <0>;
1165 reg = <6>;
1166 };
1168 pioB_clk: pioB_clk {
1169 #clock-cells = <0>;
1170 reg = <7>;
1171 };
1173 pioC_clk: pioC_clk {
1174 #clock-cells = <0>;
1175 reg = <8>;
1176 };
1178 pioD_clk: pioD_clk {
1179 #clock-cells = <0>;
1180 reg = <9>;
1181 };
1183 pioE_clk: pioE_clk {
1184 #clock-cells = <0>;
1185 reg = <10>;
1186 };
1188 usart0_clk: usart0_clk {
1189 #clock-cells = <0>;
1190 reg = <12>;
1191 atmel,clk-output-range = <0 66000000>;
1192 };
1194 usart1_clk: usart1_clk {
1195 #clock-cells = <0>;
1196 reg = <13>;
1197 atmel,clk-output-range = <0 66000000>;
1198 };
1200 usart2_clk: usart2_clk {
1201 #clock-cells = <0>;
1202 reg = <14>;
1203 atmel,clk-output-range = <0 66000000>;
1204 };
1206 usart3_clk: usart3_clk {
1207 #clock-cells = <0>;
1208 reg = <15>;
1209 atmel,clk-output-range = <0 66000000>;
1210 };
1212 uart0_clk: uart0_clk {
1213 #clock-cells = <0>;
1214 reg = <16>;
1215 atmel,clk-output-range = <0 66000000>;
1216 };
1218 twi0_clk: twi0_clk {
1219 reg = <18>;
1220 #clock-cells = <0>;
1221 atmel,clk-output-range = <0 16625000>;
1222 };
1224 twi1_clk: twi1_clk {
1225 #clock-cells = <0>;
1226 reg = <19>;
1227 atmel,clk-output-range = <0 16625000>;
1228 };
1230 twi2_clk: twi2_clk {
1231 #clock-cells = <0>;
1232 reg = <20>;
1233 atmel,clk-output-range = <0 16625000>;
1234 };
1236 mci0_clk: mci0_clk {
1237 #clock-cells = <0>;
1238 reg = <21>;
1239 };
1241 mci1_clk: mci1_clk {
1242 #clock-cells = <0>;
1243 reg = <22>;
1244 };
1246 spi0_clk: spi0_clk {
1247 #clock-cells = <0>;
1248 reg = <24>;
1249 atmel,clk-output-range = <0 133000000>;
1250 };
1252 spi1_clk: spi1_clk {
1253 #clock-cells = <0>;
1254 reg = <25>;
1255 atmel,clk-output-range = <0 133000000>;
1256 };
1258 tcb0_clk: tcb0_clk {
1259 #clock-cells = <0>;
1260 reg = <26>;
1261 atmel,clk-output-range = <0 133000000>;
1262 };
1264 pwm_clk: pwm_clk {
1265 #clock-cells = <0>;
1266 reg = <28>;
1267 };
1269 adc_clk: adc_clk {
1270 #clock-cells = <0>;
1271 reg = <29>;
1272 atmel,clk-output-range = <0 66000000>;
1273 };
1275 dma0_clk: dma0_clk {
1276 #clock-cells = <0>;
1277 reg = <30>;
1278 };
1280 dma1_clk: dma1_clk {
1281 #clock-cells = <0>;
1282 reg = <31>;
1283 };
1285 uhphs_clk: uhphs_clk {
1286 #clock-cells = <0>;
1287 reg = <32>;
1288 };
1290 udphs_clk: udphs_clk {
1291 #clock-cells = <0>;
1292 reg = <33>;
1293 };
1295 isi_clk: isi_clk {
1296 #clock-cells = <0>;
1297 reg = <37>;
1298 };
1300 ssc0_clk: ssc0_clk {
1301 #clock-cells = <0>;
1302 reg = <38>;
1303 atmel,clk-output-range = <0 66000000>;
1304 };
1306 ssc1_clk: ssc1_clk {
1307 #clock-cells = <0>;
1308 reg = <39>;
1309 atmel,clk-output-range = <0 66000000>;
1310 };
1312 sha_clk: sha_clk {
1313 #clock-cells = <0>;
1314 reg = <42>;
1315 };
1317 aes_clk: aes_clk {
1318 #clock-cells = <0>;
1319 reg = <43>;
1320 };
1322 tdes_clk: tdes_clk {
1323 #clock-cells = <0>;
1324 reg = <44>;
1325 };
1327 trng_clk: trng_clk {
1328 #clock-cells = <0>;
1329 reg = <45>;
1330 };
1332 fuse_clk: fuse_clk {
1333 #clock-cells = <0>;
1334 reg = <48>;
1335 };
1337 mpddr_clk: mpddr_clk {
1338 #clock-cells = <0>;
1339 reg = <49>;
1340 };
1341 };
1342 };
1344 reset_controller: rstc@fffffe00 {
1345 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1346 reg = <0xfffffe00 0x10>;
1347 clocks = <&clk32k>;
1348 };
1350 shutdown_controller: shutdown-controller@fffffe10 {
1351 compatible = "atmel,at91sam9x5-shdwc";
1352 reg = <0xfffffe10 0x10>;
1353 clocks = <&clk32k>;
1354 };
1356 pit: timer@fffffe30 {
1357 compatible = "atmel,at91sam9260-pit";
1358 reg = <0xfffffe30 0xf>;
1359 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1360 clocks = <&mck>;
1361 };
1363 watchdog: watchdog@fffffe40 {
1364 compatible = "atmel,at91sam9260-wdt";
1365 reg = <0xfffffe40 0x10>;
1366 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1367 clocks = <&clk32k>;
1368 atmel,watchdog-type = "hardware";
1369 atmel,reset-type = "all";
1370 atmel,dbg-halt;
1371 status = "disabled";
1372 };
1374 clk32k: sckc@fffffe50 {
1375 compatible = "atmel,sama5d3-sckc";
1376 reg = <0xfffffe50 0x4>;
1377 clocks = <&slow_xtal>;
1378 #clock-cells = <0>;
1379 };
1381 rtc@fffffeb0 {
1382 compatible = "atmel,at91rm9200-rtc";
1383 reg = <0xfffffeb0 0x30>;
1384 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1385 clocks = <&clk32k>;
1386 };
1387 };
1389 nfc_sram: sram@200000 {
1390 compatible = "mmio-sram";
1391 no-memory-wc;
1392 reg = <0x200000 0x2400>;
1393 };
1395 usb0: gadget@500000 {
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1398 compatible = "atmel,sama5d3-udc";
1399 reg = <0x00500000 0x100000
1400 0xf8030000 0x4000>;
1401 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1402 clocks = <&udphs_clk>, <&utmi>;
1403 clock-names = "pclk", "hclk";
1404 status = "disabled";
1406 ep@0 {
1407 reg = <0>;
1408 atmel,fifo-size = <64>;
1409 atmel,nb-banks = <1>;
1410 };
1412 ep@1 {
1413 reg = <1>;
1414 atmel,fifo-size = <1024>;
1415 atmel,nb-banks = <3>;
1416 atmel,can-dma;
1417 atmel,can-isoc;
1418 };
1420 ep@2 {
1421 reg = <2>;
1422 atmel,fifo-size = <1024>;
1423 atmel,nb-banks = <3>;
1424 atmel,can-dma;
1425 atmel,can-isoc;
1426 };
1428 ep@3 {
1429 reg = <3>;
1430 atmel,fifo-size = <1024>;
1431 atmel,nb-banks = <2>;
1432 atmel,can-dma;
1433 };
1435 ep@4 {
1436 reg = <4>;
1437 atmel,fifo-size = <1024>;
1438 atmel,nb-banks = <2>;
1439 atmel,can-dma;
1440 };
1442 ep@5 {
1443 reg = <5>;
1444 atmel,fifo-size = <1024>;
1445 atmel,nb-banks = <2>;
1446 atmel,can-dma;
1447 };
1449 ep@6 {
1450 reg = <6>;
1451 atmel,fifo-size = <1024>;
1452 atmel,nb-banks = <2>;
1453 atmel,can-dma;
1454 };
1456 ep@7 {
1457 reg = <7>;
1458 atmel,fifo-size = <1024>;
1459 atmel,nb-banks = <2>;
1460 atmel,can-dma;
1461 };
1463 ep@8 {
1464 reg = <8>;
1465 atmel,fifo-size = <1024>;
1466 atmel,nb-banks = <2>;
1467 };
1469 ep@9 {
1470 reg = <9>;
1471 atmel,fifo-size = <1024>;
1472 atmel,nb-banks = <2>;
1473 };
1475 ep@10 {
1476 reg = <10>;
1477 atmel,fifo-size = <1024>;
1478 atmel,nb-banks = <2>;
1479 };
1481 ep@11 {
1482 reg = <11>;
1483 atmel,fifo-size = <1024>;
1484 atmel,nb-banks = <2>;
1485 };
1487 ep@12 {
1488 reg = <12>;
1489 atmel,fifo-size = <1024>;
1490 atmel,nb-banks = <2>;
1491 };
1493 ep@13 {
1494 reg = <13>;
1495 atmel,fifo-size = <1024>;
1496 atmel,nb-banks = <2>;
1497 };
1499 ep@14 {
1500 reg = <14>;
1501 atmel,fifo-size = <1024>;
1502 atmel,nb-banks = <2>;
1503 };
1505 ep@15 {
1506 reg = <15>;
1507 atmel,fifo-size = <1024>;
1508 atmel,nb-banks = <2>;
1509 };
1510 };
1512 usb1: ohci@600000 {
1513 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1514 reg = <0x00600000 0x100000>;
1515 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1516 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1517 clock-names = "ohci_clk", "hclk", "uhpck";
1518 status = "disabled";
1519 };
1521 usb2: ehci@700000 {
1522 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1523 reg = <0x00700000 0x100000>;
1524 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1525 clocks = <&utmi>, <&uhphs_clk>;
1526 clock-names = "usb_clk", "ehci_clk";
1527 status = "disabled";
1528 };
1530 ebi: ebi@10000000 {
1531 compatible = "atmel,sama5d3-ebi";
1532 #address-cells = <2>;
1533 #size-cells = <1>;
1534 atmel,smc = <&hsmc>;
1535 reg = <0x10000000 0x10000000
1536 0x40000000 0x30000000>;
1537 ranges = <0x0 0x0 0x10000000 0x10000000
1538 0x1 0x0 0x40000000 0x10000000
1539 0x2 0x0 0x50000000 0x10000000
1540 0x3 0x0 0x60000000 0x10000000>;
1541 clocks = <&mck>;
1542 status = "disabled";
1544 nand_controller: nand-controller {
1545 compatible = "atmel,sama5d3-nand-controller";
1546 atmel,nfc-sram = <&nfc_sram>;
1547 atmel,nfc-io = <&nfc_io>;
1548 ecc-engine = <&pmecc>;
1549 #address-cells = <2>;
1550 #size-cells = <1>;
1551 ranges;
1552 status = "disabled";
1553 };
1554 };
1556 nfc_io: nfc-io@70000000 {
1557 compatible = "atmel,sama5d3-nfc-io", "syscon";
1558 reg = <0x70000000 0x8000000>;
1559 };
1560 };
1561 };