| blob | 4f3993cc022796c4a3946af0e1aabd984f3937d7 |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Altera <www.altera.com>
4 */
6 #include <dt-bindings/reset/altr,rst-mgr.h>
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
12 aliases {
13 serial0 = &uart0;
14 serial1 = &uart1;
15 timer0 = &timer0;
16 timer1 = &timer1;
17 timer2 = &timer2;
18 timer3 = &timer3;
19 };
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
26 cpu0: cpu@0 {
27 compatible = "arm,cortex-a9";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 };
32 cpu1: cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 };
38 };
40 pmu: pmu@ff111000 {
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
47 };
49 intc: intc@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
55 };
57 soc {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 device_type = "soc";
62 interrupt-parent = <&intc>;
63 ranges;
65 amba {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
71 pdma: pdma@ffe01000 {
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
75 <0 105 4>,
76 <0 106 4>,
77 <0 107 4>,
78 <0 108 4>,
79 <0 109 4>,
80 <0 110 4>,
81 <0 111 4>;
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
85 clocks = <&l4_main_clk>;
86 clock-names = "apb_pclk";
87 resets = <&rst DMA_RESET>;
88 reset-names = "dma";
89 };
90 };
92 base_fpga_region {
93 compatible = "fpga-region";
94 fpga-mgr = <&fpgamgr0>;
96 #address-cells = <0x1>;
97 #size-cells = <0x1>;
98 };
100 can0: can@ffc00000 {
101 compatible = "bosch,d_can";
102 reg = <0xffc00000 0x1000>;
103 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
104 clocks = <&can0_clk>;
105 resets = <&rst CAN0_RESET>;
106 status = "disabled";
107 };
109 can1: can@ffc01000 {
110 compatible = "bosch,d_can";
111 reg = <0xffc01000 0x1000>;
112 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
113 clocks = <&can1_clk>;
114 resets = <&rst CAN1_RESET>;
115 status = "disabled";
116 };
118 clkmgr@ffd04000 {
119 compatible = "altr,clk-mgr";
120 reg = <0xffd04000 0x1000>;
122 clocks {
123 #address-cells = <1>;
124 #size-cells = <0>;
126 osc1: osc1 {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 };
131 osc2: osc2 {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 };
136 f2s_periph_ref_clk: f2s_periph_ref_clk {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 };
141 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 };
146 main_pll: main_pll@40 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #clock-cells = <0>;
150 compatible = "altr,socfpga-pll-clock";
151 clocks = <&osc1>;
152 reg = <0x40>;
154 mpuclk: mpuclk@48 {
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
158 div-reg = <0xe0 0 9>;
159 reg = <0x48>;
160 };
162 mainclk: mainclk@4c {
163 #clock-cells = <0>;
164 compatible = "altr,socfpga-perip-clk";
165 clocks = <&main_pll>;
166 div-reg = <0xe4 0 9>;
167 reg = <0x4C>;
168 };
170 dbg_base_clk: dbg_base_clk@50 {
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-perip-clk";
173 clocks = <&main_pll>, <&osc1>;
174 div-reg = <0xe8 0 9>;
175 reg = <0x50>;
176 };
178 main_qspi_clk: main_qspi_clk@54 {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x54>;
183 };
185 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x58>;
190 };
192 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-perip-clk";
195 clocks = <&main_pll>;
196 reg = <0x5C>;
197 };
198 };
200 periph_pll: periph_pll@80 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-pll-clock";
205 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
206 reg = <0x80>;
208 emac0_clk: emac0_clk@88 {
209 #clock-cells = <0>;
210 compatible = "altr,socfpga-perip-clk";
211 clocks = <&periph_pll>;
212 reg = <0x88>;
213 };
215 emac1_clk: emac1_clk@8c {
216 #clock-cells = <0>;
217 compatible = "altr,socfpga-perip-clk";
218 clocks = <&periph_pll>;
219 reg = <0x8C>;
220 };
222 per_qspi_clk: per_qsi_clk@90 {
223 #clock-cells = <0>;
224 compatible = "altr,socfpga-perip-clk";
225 clocks = <&periph_pll>;
226 reg = <0x90>;
227 };
229 per_nand_mmc_clk: per_nand_mmc_clk@94 {
230 #clock-cells = <0>;
231 compatible = "altr,socfpga-perip-clk";
232 clocks = <&periph_pll>;
233 reg = <0x94>;
234 };
236 per_base_clk: per_base_clk@98 {
237 #clock-cells = <0>;
238 compatible = "altr,socfpga-perip-clk";
239 clocks = <&periph_pll>;
240 reg = <0x98>;
241 };
243 h2f_usr1_clk: h2f_usr1_clk@9c {
244 #clock-cells = <0>;
245 compatible = "altr,socfpga-perip-clk";
246 clocks = <&periph_pll>;
247 reg = <0x9C>;
248 };
249 };
251 sdram_pll: sdram_pll@c0 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-pll-clock";
256 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
257 reg = <0xC0>;
259 ddr_dqs_clk: ddr_dqs_clk@c8 {
260 #clock-cells = <0>;
261 compatible = "altr,socfpga-perip-clk";
262 clocks = <&sdram_pll>;
263 reg = <0xC8>;
264 };
266 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
267 #clock-cells = <0>;
268 compatible = "altr,socfpga-perip-clk";
269 clocks = <&sdram_pll>;
270 reg = <0xCC>;
271 };
273 ddr_dq_clk: ddr_dq_clk@d0 {
274 #clock-cells = <0>;
275 compatible = "altr,socfpga-perip-clk";
276 clocks = <&sdram_pll>;
277 reg = <0xD0>;
278 };
280 h2f_usr2_clk: h2f_usr2_clk@d4 {
281 #clock-cells = <0>;
282 compatible = "altr,socfpga-perip-clk";
283 clocks = <&sdram_pll>;
284 reg = <0xD4>;
285 };
286 };
288 mpu_periph_clk: mpu_periph_clk {
289 #clock-cells = <0>;
290 compatible = "altr,socfpga-perip-clk";
291 clocks = <&mpuclk>;
292 fixed-divider = <4>;
293 };
295 mpu_l2_ram_clk: mpu_l2_ram_clk {
296 #clock-cells = <0>;
297 compatible = "altr,socfpga-perip-clk";
298 clocks = <&mpuclk>;
299 fixed-divider = <2>;
300 };
302 l4_main_clk: l4_main_clk {
303 #clock-cells = <0>;
304 compatible = "altr,socfpga-gate-clk";
305 clocks = <&mainclk>;
306 clk-gate = <0x60 0>;
307 };
309 l3_main_clk: l3_main_clk {
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-perip-clk";
312 clocks = <&mainclk>;
313 fixed-divider = <1>;
314 };
316 l3_mp_clk: l3_mp_clk {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-gate-clk";
319 clocks = <&mainclk>;
320 div-reg = <0x64 0 2>;
321 clk-gate = <0x60 1>;
322 };
324 l3_sp_clk: l3_sp_clk {
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-gate-clk";
327 clocks = <&l3_mp_clk>;
328 div-reg = <0x64 2 2>;
329 };
331 l4_mp_clk: l4_mp_clk {
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&mainclk>, <&per_base_clk>;
335 div-reg = <0x64 4 3>;
336 clk-gate = <0x60 2>;
337 };
339 l4_sp_clk: l4_sp_clk {
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&mainclk>, <&per_base_clk>;
343 div-reg = <0x64 7 3>;
344 clk-gate = <0x60 3>;
345 };
347 dbg_at_clk: dbg_at_clk {
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&dbg_base_clk>;
351 div-reg = <0x68 0 2>;
352 clk-gate = <0x60 4>;
353 };
355 dbg_clk: dbg_clk {
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-gate-clk";
358 clocks = <&dbg_at_clk>;
359 div-reg = <0x68 2 2>;
360 clk-gate = <0x60 5>;
361 };
363 dbg_trace_clk: dbg_trace_clk {
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&dbg_base_clk>;
367 div-reg = <0x6C 0 3>;
368 clk-gate = <0x60 6>;
369 };
371 dbg_timer_clk: dbg_timer_clk {
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&dbg_base_clk>;
375 clk-gate = <0x60 7>;
376 };
378 cfg_clk: cfg_clk {
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-gate-clk";
381 clocks = <&cfg_h2f_usr0_clk>;
382 clk-gate = <0x60 8>;
383 };
385 h2f_user0_clk: h2f_user0_clk {
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-gate-clk";
388 clocks = <&cfg_h2f_usr0_clk>;
389 clk-gate = <0x60 9>;
390 };
392 emac_0_clk: emac_0_clk {
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-gate-clk";
395 clocks = <&emac0_clk>;
396 clk-gate = <0xa0 0>;
397 };
399 emac_1_clk: emac_1_clk {
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-gate-clk";
402 clocks = <&emac1_clk>;
403 clk-gate = <0xa0 1>;
404 };
406 usb_mp_clk: usb_mp_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&per_base_clk>;
410 clk-gate = <0xa0 2>;
411 div-reg = <0xa4 0 3>;
412 };
414 spi_m_clk: spi_m_clk {
415 #clock-cells = <0>;
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
418 clk-gate = <0xa0 3>;
419 div-reg = <0xa4 3 3>;
420 };
422 can0_clk: can0_clk {
423 #clock-cells = <0>;
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&per_base_clk>;
426 clk-gate = <0xa0 4>;
427 div-reg = <0xa4 6 3>;
428 };
430 can1_clk: can1_clk {
431 #clock-cells = <0>;
432 compatible = "altr,socfpga-gate-clk";
433 clocks = <&per_base_clk>;
434 clk-gate = <0xa0 5>;
435 div-reg = <0xa4 9 3>;
436 };
438 gpio_db_clk: gpio_db_clk {
439 #clock-cells = <0>;
440 compatible = "altr,socfpga-gate-clk";
441 clocks = <&per_base_clk>;
442 clk-gate = <0xa0 6>;
443 div-reg = <0xa8 0 24>;
444 };
446 h2f_user1_clk: h2f_user1_clk {
447 #clock-cells = <0>;
448 compatible = "altr,socfpga-gate-clk";
449 clocks = <&h2f_usr1_clk>;
450 clk-gate = <0xa0 7>;
451 };
453 sdmmc_clk: sdmmc_clk {
454 #clock-cells = <0>;
455 compatible = "altr,socfpga-gate-clk";
456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
457 clk-gate = <0xa0 8>;
458 clk-phase = <0 135>;
459 };
461 sdmmc_clk_divided: sdmmc_clk_divided {
462 #clock-cells = <0>;
463 compatible = "altr,socfpga-gate-clk";
464 clocks = <&sdmmc_clk>;
465 clk-gate = <0xa0 8>;
466 fixed-divider = <4>;
467 };
469 nand_x_clk: nand_x_clk {
470 #clock-cells = <0>;
471 compatible = "altr,socfpga-gate-clk";
472 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
473 clk-gate = <0xa0 9>;
474 };
476 nand_ecc_clk: nand_ecc_clk {
477 #clock-cells = <0>;
478 compatible = "altr,socfpga-gate-clk";
479 clocks = <&nand_x_clk>;
480 clk-gate = <0xa0 9>;
481 };
483 nand_clk: nand_clk {
484 #clock-cells = <0>;
485 compatible = "altr,socfpga-gate-clk";
486 clocks = <&nand_x_clk>;
487 clk-gate = <0xa0 10>;
488 fixed-divider = <4>;
489 };
491 qspi_clk: qspi_clk {
492 #clock-cells = <0>;
493 compatible = "altr,socfpga-gate-clk";
494 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
495 clk-gate = <0xa0 11>;
496 };
498 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
499 #clock-cells = <0>;
500 compatible = "altr,socfpga-gate-clk";
501 clocks = <&ddr_dqs_clk>;
502 clk-gate = <0xd8 0>;
503 };
505 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
506 #clock-cells = <0>;
507 compatible = "altr,socfpga-gate-clk";
508 clocks = <&ddr_2x_dqs_clk>;
509 clk-gate = <0xd8 1>;
510 };
512 ddr_dq_clk_gate: ddr_dq_clk_gate {
513 #clock-cells = <0>;
514 compatible = "altr,socfpga-gate-clk";
515 clocks = <&ddr_dq_clk>;
516 clk-gate = <0xd8 2>;
517 };
519 h2f_user2_clk: h2f_user2_clk {
520 #clock-cells = <0>;
521 compatible = "altr,socfpga-gate-clk";
522 clocks = <&h2f_usr2_clk>;
523 clk-gate = <0xd8 3>;
524 };
526 };
527 };
529 fpga_bridge0: fpga_bridge@ff400000 {
530 compatible = "altr,socfpga-lwhps2fpga-bridge";
531 reg = <0xff400000 0x100000>;
532 resets = <&rst LWHPS2FPGA_RESET>;
533 clocks = <&l4_main_clk>;
534 };
536 fpga_bridge1: fpga_bridge@ff500000 {
537 compatible = "altr,socfpga-hps2fpga-bridge";
538 reg = <0xff500000 0x10000>;
539 resets = <&rst HPS2FPGA_RESET>;
540 clocks = <&l4_main_clk>;
541 };
543 fpgamgr0: fpgamgr@ff706000 {
544 compatible = "altr,socfpga-fpga-mgr";
545 reg = <0xff706000 0x1000
546 0xffb90000 0x4>;
547 interrupts = <0 175 4>;
548 };
550 gmac0: ethernet@ff700000 {
551 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
552 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
553 reg = <0xff700000 0x2000>;
554 interrupts = <0 115 4>;
555 interrupt-names = "macirq";
556 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
557 clocks = <&emac_0_clk>;
558 clock-names = "stmmaceth";
559 resets = <&rst EMAC0_RESET>;
560 reset-names = "stmmaceth";
561 snps,multicast-filter-bins = <256>;
562 snps,perfect-filter-entries = <128>;
563 tx-fifo-depth = <4096>;
564 rx-fifo-depth = <4096>;
565 status = "disabled";
566 };
568 gmac1: ethernet@ff702000 {
569 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
570 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
571 reg = <0xff702000 0x2000>;
572 interrupts = <0 120 4>;
573 interrupt-names = "macirq";
574 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
575 clocks = <&emac_1_clk>;
576 clock-names = "stmmaceth";
577 resets = <&rst EMAC1_RESET>;
578 reset-names = "stmmaceth";
579 snps,multicast-filter-bins = <256>;
580 snps,perfect-filter-entries = <128>;
581 tx-fifo-depth = <4096>;
582 rx-fifo-depth = <4096>;
583 status = "disabled";
584 };
586 gpio0: gpio@ff708000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "snps,dw-apb-gpio";
590 reg = <0xff708000 0x1000>;
591 clocks = <&l4_mp_clk>;
592 resets = <&rst GPIO0_RESET>;
593 status = "disabled";
595 porta: gpio-controller@0 {
596 compatible = "snps,dw-apb-gpio-port";
597 gpio-controller;
598 #gpio-cells = <2>;
599 snps,nr-gpios = <29>;
600 reg = <0>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 interrupts = <0 164 4>;
604 };
605 };
607 gpio1: gpio@ff709000 {
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "snps,dw-apb-gpio";
611 reg = <0xff709000 0x1000>;
612 clocks = <&l4_mp_clk>;
613 resets = <&rst GPIO1_RESET>;
614 status = "disabled";
616 portb: gpio-controller@0 {
617 compatible = "snps,dw-apb-gpio-port";
618 gpio-controller;
619 #gpio-cells = <2>;
620 snps,nr-gpios = <29>;
621 reg = <0>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 interrupts = <0 165 4>;
625 };
626 };
628 gpio2: gpio@ff70a000 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "snps,dw-apb-gpio";
632 reg = <0xff70a000 0x1000>;
633 clocks = <&l4_mp_clk>;
634 resets = <&rst GPIO2_RESET>;
635 status = "disabled";
637 portc: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <27>;
642 reg = <0>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 interrupts = <0 166 4>;
646 };
647 };
649 i2c0: i2c@ffc04000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,designware-i2c";
653 reg = <0xffc04000 0x1000>;
654 resets = <&rst I2C0_RESET>;
655 clocks = <&l4_sp_clk>;
656 interrupts = <0 158 0x4>;
657 status = "disabled";
658 };
660 i2c1: i2c@ffc05000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "snps,designware-i2c";
664 reg = <0xffc05000 0x1000>;
665 resets = <&rst I2C1_RESET>;
666 clocks = <&l4_sp_clk>;
667 interrupts = <0 159 0x4>;
668 status = "disabled";
669 };
671 i2c2: i2c@ffc06000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc06000 0x1000>;
676 resets = <&rst I2C2_RESET>;
677 clocks = <&l4_sp_clk>;
678 interrupts = <0 160 0x4>;
679 status = "disabled";
680 };
682 i2c3: i2c@ffc07000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "snps,designware-i2c";
686 reg = <0xffc07000 0x1000>;
687 resets = <&rst I2C3_RESET>;
688 clocks = <&l4_sp_clk>;
689 interrupts = <0 161 0x4>;
690 status = "disabled";
691 };
693 eccmgr: eccmgr {
694 compatible = "altr,socfpga-ecc-manager";
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges;
699 l2-ecc@ffd08140 {
700 compatible = "altr,socfpga-l2-ecc";
701 reg = <0xffd08140 0x4>;
702 interrupts = <0 36 1>, <0 37 1>;
703 };
705 ocram-ecc@ffd08144 {
706 compatible = "altr,socfpga-ocram-ecc";
707 reg = <0xffd08144 0x4>;
708 iram = <&ocram>;
709 interrupts = <0 178 1>, <0 179 1>;
710 };
711 };
713 L2: l2-cache@fffef000 {
714 compatible = "arm,pl310-cache";
715 reg = <0xfffef000 0x1000>;
716 interrupts = <0 38 0x04>;
717 cache-unified;
718 cache-level = <2>;
719 arm,tag-latency = <1 1 1>;
720 arm,data-latency = <2 1 1>;
721 prefetch-data = <1>;
722 prefetch-instr = <1>;
723 arm,shared-override;
724 arm,double-linefill = <1>;
725 arm,double-linefill-incr = <0>;
726 arm,double-linefill-wrap = <1>;
727 arm,prefetch-drop = <0>;
728 arm,prefetch-offset = <7>;
729 };
731 l3regs@0xff800000 {
732 compatible = "altr,l3regs", "syscon";
733 reg = <0xff800000 0x1000>;
734 };
736 mmc: dwmmc0@ff704000 {
737 compatible = "altr,socfpga-dw-mshc";
738 reg = <0xff704000 0x1000>;
739 interrupts = <0 139 4>;
740 fifo-depth = <0x400>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
744 clock-names = "biu", "ciu";
745 resets = <&rst SDMMC_RESET>;
746 status = "disabled";
747 };
749 nand0: nand@ff900000 {
750 #address-cells = <0x1>;
751 #size-cells = <0x0>;
752 compatible = "altr,socfpga-denali-nand";
753 reg = <0xff900000 0x100000>,
754 <0xffb80000 0x10000>;
755 reg-names = "nand_data", "denali_reg";
756 interrupts = <0x0 0x90 0x4>;
757 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
758 clock-names = "nand", "nand_x", "ecc";
759 resets = <&rst NAND_RESET>;
760 status = "disabled";
761 };
763 ocram: sram@ffff0000 {
764 compatible = "mmio-sram";
765 reg = <0xffff0000 0x10000>;
766 };
768 qspi: spi@ff705000 {
769 compatible = "cdns,qspi-nor";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 reg = <0xff705000 0x1000>,
773 <0xffa00000 0x1000>;
774 interrupts = <0 151 4>;
775 cdns,fifo-depth = <128>;
776 cdns,fifo-width = <4>;
777 cdns,trigger-address = <0x00000000>;
778 clocks = <&qspi_clk>;
779 resets = <&rst QSPI_RESET>;
780 status = "disabled";
781 };
783 rst: rstmgr@ffd05000 {
784 #reset-cells = <1>;
785 compatible = "altr,rst-mgr";
786 reg = <0xffd05000 0x1000>;
787 altr,modrst-offset = <0x10>;
788 };
790 scu: snoop-control-unit@fffec000 {
791 compatible = "arm,cortex-a9-scu";
792 reg = <0xfffec000 0x100>;
793 };
795 sdr: sdr@ffc25000 {
796 compatible = "altr,sdr-ctl", "syscon";
797 reg = <0xffc25000 0x1000>;
798 resets = <&rst SDR_RESET>;
799 };
801 sdramedac {
802 compatible = "altr,sdram-edac";
803 altr,sdr-syscon = <&sdr>;
804 interrupts = <0 39 4>;
805 };
807 spi0: spi@fff00000 {
808 compatible = "snps,dw-apb-ssi";
809 #address-cells = <1>;
810 #size-cells = <0>;
811 reg = <0xfff00000 0x1000>;
812 interrupts = <0 154 4>;
813 num-cs = <4>;
814 clocks = <&spi_m_clk>;
815 resets = <&rst SPIM0_RESET>;
816 status = "disabled";
817 };
819 spi1: spi@fff01000 {
820 compatible = "snps,dw-apb-ssi";
821 #address-cells = <1>;
822 #size-cells = <0>;
823 reg = <0xfff01000 0x1000>;
824 interrupts = <0 155 4>;
825 num-cs = <4>;
826 clocks = <&spi_m_clk>;
827 resets = <&rst SPIM1_RESET>;
828 status = "disabled";
829 };
831 sysmgr: sysmgr@ffd08000 {
832 compatible = "altr,sys-mgr", "syscon";
833 reg = <0xffd08000 0x4000>;
834 };
836 /* Local timer */
837 timer@fffec600 {
838 compatible = "arm,cortex-a9-twd-timer";
839 reg = <0xfffec600 0x100>;
840 interrupts = <1 13 0xf01>;
841 clocks = <&mpu_periph_clk>;
842 };
844 timer0: timer0@ffc08000 {
845 compatible = "snps,dw-apb-timer";
846 interrupts = <0 167 4>;
847 reg = <0xffc08000 0x1000>;
848 clocks = <&l4_sp_clk>;
849 clock-names = "timer";
850 resets = <&rst SPTIMER0_RESET>;
851 reset-names = "timer";
852 };
854 timer1: timer1@ffc09000 {
855 compatible = "snps,dw-apb-timer";
856 interrupts = <0 168 4>;
857 reg = <0xffc09000 0x1000>;
858 clocks = <&l4_sp_clk>;
859 clock-names = "timer";
860 resets = <&rst SPTIMER1_RESET>;
861 reset-names = "timer";
862 };
864 timer2: timer2@ffd00000 {
865 compatible = "snps,dw-apb-timer";
866 interrupts = <0 169 4>;
867 reg = <0xffd00000 0x1000>;
868 clocks = <&osc1>;
869 clock-names = "timer";
870 resets = <&rst OSC1TIMER0_RESET>;
871 reset-names = "timer";
872 };
874 timer3: timer3@ffd01000 {
875 compatible = "snps,dw-apb-timer";
876 interrupts = <0 170 4>;
877 reg = <0xffd01000 0x1000>;
878 clocks = <&osc1>;
879 clock-names = "timer";
880 resets = <&rst OSC1TIMER1_RESET>;
881 reset-names = "timer";
882 };
884 uart0: serial0@ffc02000 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0xffc02000 0x1000>;
887 interrupts = <0 162 4>;
888 reg-shift = <2>;
889 reg-io-width = <4>;
890 clocks = <&l4_sp_clk>;
891 dmas = <&pdma 28>,
892 <&pdma 29>;
893 dma-names = "tx", "rx";
894 resets = <&rst UART0_RESET>;
895 };
897 uart1: serial1@ffc03000 {
898 compatible = "snps,dw-apb-uart";
899 reg = <0xffc03000 0x1000>;
900 interrupts = <0 163 4>;
901 reg-shift = <2>;
902 reg-io-width = <4>;
903 clocks = <&l4_sp_clk>;
904 dmas = <&pdma 30>,
905 <&pdma 31>;
906 dma-names = "tx", "rx";
907 resets = <&rst UART1_RESET>;
908 };
910 usbphy0: usbphy {
911 #phy-cells = <0>;
912 compatible = "usb-nop-xceiv";
913 status = "okay";
914 };
916 usb0: usb@ffb00000 {
917 compatible = "snps,dwc2";
918 reg = <0xffb00000 0xffff>;
919 interrupts = <0 125 4>;
920 clocks = <&usb_mp_clk>;
921 clock-names = "otg";
922 resets = <&rst USB0_RESET>;
923 reset-names = "dwc2";
924 phys = <&usbphy0>;
925 phy-names = "usb2-phy";
926 status = "disabled";
927 };
929 usb1: usb@ffb40000 {
930 compatible = "snps,dwc2";
931 reg = <0xffb40000 0xffff>;
932 interrupts = <0 128 4>;
933 clocks = <&usb_mp_clk>;
934 clock-names = "otg";
935 resets = <&rst USB1_RESET>;
936 reset-names = "dwc2";
937 phys = <&usbphy0>;
938 phy-names = "usb2-phy";
939 status = "disabled";
940 };
942 watchdog0: watchdog@ffd02000 {
943 compatible = "snps,dw-wdt";
944 reg = <0xffd02000 0x1000>;
945 interrupts = <0 171 4>;
946 clocks = <&osc1>;
947 resets = <&rst L4WD0_RESET>;
948 status = "disabled";
949 };
951 watchdog1: watchdog@ffd03000 {
952 compatible = "snps,dw-wdt";
953 reg = <0xffd03000 0x1000>;
954 interrupts = <0 172 4>;
955 clocks = <&osc1>;
956 resets = <&rst L4WD1_RESET>;
957 status = "disabled";
958 };
959 };
960 };