1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Linaro Ltd.
11 /* Hog a few default settings */
12 pinctrl-names = "default";
13 pinctrl-0 = <&gpio2_default_mode>,
14 <&gpio10_default_mode>,
15 <&gpio11_default_mode>,
16 <&gpio13_default_mode>,
17 <&gpio34_default_mode>,
18 <&gpio50_default_mode>,
21 <&modsclsda_default_mode>,
22 <&resethw_default_mode>,
23 <&service_default_mode>;
26 * Pins 2, 10, 11, 13, 34 and 50
27 * are muxed in as GPIO, and configured as INPUT PULL DOWN
30 gpio2_default_mode: gpio2_default {
43 gpio10_default_mode: gpio10_default {
46 groups = "gpio10_d_1";
56 gpio11_default_mode: gpio11_default {
59 groups = "gpio11_d_1";
69 gpio13_default_mode: gpio13_default {
72 groups = "gpio13_d_1";
82 gpio34_default_mode: gpio34_default {
85 groups = "gpio34_a_1";
95 gpio50_default_mode: gpio50_default {
98 groups = "gpio50_d_1";
107 /* This sets up the PWM pin 14 */
109 pwm_default_mode: pwm_default {
112 groups = "pwmout1_d_1";
121 /* This sets up audio interface 2 */
123 adi2_default_mode: adi2_default {
138 /* Modem I2C setup (SCL and SDA pins) */
140 modsclsda_default_mode: modsclsda_default {
142 function = "modsclsda";
143 groups = "modsclsda_d_1";
154 resethw_default_mode: resethw_default {
156 function = "resethw";
157 groups = "resethw_d_1";
167 service_default_mode: service_default {
169 function = "service";
170 groups = "service_d_1";
180 * Clock output pins associated with regulators.
183 sysclkreq2_default_mode: sysclkreq2_default {
185 function = "sysclkreq";
186 groups = "sysclkreq2_d_1";
194 sysclkreq2_sleep_mode: sysclkreq2_sleep {
197 groups = "gpio1_a_1";
207 sysclkreq4_default_mode: sysclkreq4_default {
209 function = "sysclkreq";
210 groups = "sysclkreq4_d_1";
218 sysclkreq4_sleep_mode: sysclkreq4_sleep {
221 groups = "gpio3_a_1";