| blob | 5c8a826b3195868ffbd204bcdc419279dacc0313 |
1 /*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
52 / {
53 #address-cells = <1>;
54 #size-cells = <1>;
56 clocks {
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
61 };
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
73 };
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
79 };
80 };
82 soc {
83 romem: nvmem@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ts_cal1: calib@22c {
89 reg = <0x22c 0x2>;
90 };
91 ts_cal2: calib@22e {
92 reg = <0x22e 0x2>;
93 };
94 };
96 timer2: timer@40000000 {
97 compatible = "st,stm32-timer";
98 reg = <0x40000000 0x400>;
99 interrupts = <28>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
101 status = "disabled";
102 };
104 timers2: timers@40000000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "st,stm32-timers";
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clock-names = "int";
111 status = "disabled";
113 pwm {
114 compatible = "st,stm32-pwm";
115 #pwm-cells = <3>;
116 status = "disabled";
117 };
119 timer@1 {
120 compatible = "st,stm32-timer-trigger";
121 reg = <1>;
122 status = "disabled";
123 };
124 };
126 timer3: timer@40000400 {
127 compatible = "st,stm32-timer";
128 reg = <0x40000400 0x400>;
129 interrupts = <29>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
131 status = "disabled";
132 };
134 timers3: timers@40000400 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "st,stm32-timers";
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
140 clock-names = "int";
141 status = "disabled";
143 pwm {
144 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
146 status = "disabled";
147 };
149 timer@2 {
150 compatible = "st,stm32-timer-trigger";
151 reg = <2>;
152 status = "disabled";
153 };
154 };
156 timer4: timer@40000800 {
157 compatible = "st,stm32-timer";
158 reg = <0x40000800 0x400>;
159 interrupts = <30>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
161 status = "disabled";
162 };
164 timers4: timers@40000800 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "st,stm32-timers";
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
170 clock-names = "int";
171 status = "disabled";
173 pwm {
174 compatible = "st,stm32-pwm";
175 #pwm-cells = <3>;
176 status = "disabled";
177 };
179 timer@3 {
180 compatible = "st,stm32-timer-trigger";
181 reg = <3>;
182 status = "disabled";
183 };
184 };
186 timer5: timer@40000c00 {
187 compatible = "st,stm32-timer";
188 reg = <0x40000c00 0x400>;
189 interrupts = <50>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
191 };
193 timers5: timers@40000c00 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "st,stm32-timers";
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
199 clock-names = "int";
200 status = "disabled";
202 pwm {
203 compatible = "st,stm32-pwm";
204 #pwm-cells = <3>;
205 status = "disabled";
206 };
208 timer@4 {
209 compatible = "st,stm32-timer-trigger";
210 reg = <4>;
211 status = "disabled";
212 };
213 };
215 timer6: timer@40001000 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001000 0x400>;
218 interrupts = <54>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
220 status = "disabled";
221 };
223 timers6: timers@40001000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
229 clock-names = "int";
230 status = "disabled";
232 timer@5 {
233 compatible = "st,stm32-timer-trigger";
234 reg = <5>;
235 status = "disabled";
236 };
237 };
239 timer7: timer@40001400 {
240 compatible = "st,stm32-timer";
241 reg = <0x40001400 0x400>;
242 interrupts = <55>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
244 status = "disabled";
245 };
247 timers7: timers@40001400 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "st,stm32-timers";
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
253 clock-names = "int";
254 status = "disabled";
256 timer@6 {
257 compatible = "st,stm32-timer-trigger";
258 reg = <6>;
259 status = "disabled";
260 };
261 };
263 timers12: timers@40001800 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "st,stm32-timers";
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
269 clock-names = "int";
270 status = "disabled";
272 pwm {
273 compatible = "st,stm32-pwm";
274 #pwm-cells = <3>;
275 status = "disabled";
276 };
278 timer@11 {
279 compatible = "st,stm32-timer-trigger";
280 reg = <11>;
281 status = "disabled";
282 };
283 };
285 timers13: timers@40001c00 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "st,stm32-timers";
289 reg = <0x40001C00 0x400>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
291 clock-names = "int";
292 status = "disabled";
294 pwm {
295 compatible = "st,stm32-pwm";
296 #pwm-cells = <3>;
297 status = "disabled";
298 };
299 };
301 timers14: timers@40002000 {
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "st,stm32-timers";
305 reg = <0x40002000 0x400>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
307 clock-names = "int";
308 status = "disabled";
310 pwm {
311 compatible = "st,stm32-pwm";
312 #pwm-cells = <3>;
313 status = "disabled";
314 };
315 };
317 rtc: rtc@40002800 {
318 compatible = "st,stm32-rtc";
319 reg = <0x40002800 0x400>;
320 clocks = <&rcc 1 CLK_RTC>;
321 clock-names = "ck_rtc";
322 assigned-clocks = <&rcc 1 CLK_RTC>;
323 assigned-clock-parents = <&rcc 1 CLK_LSE>;
324 interrupt-parent = <&exti>;
325 interrupts = <17 1>;
326 interrupt-names = "alarm";
327 st,syscfg = <&pwrcfg 0x00 0x100>;
328 status = "disabled";
329 };
331 iwdg: watchdog@40003000 {
332 compatible = "st,stm32-iwdg";
333 reg = <0x40003000 0x400>;
334 clocks = <&clk_lsi>;
335 clock-names = "lsi";
336 status = "disabled";
337 };
339 spi2: spi@40003800 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 compatible = "st,stm32f4-spi";
343 reg = <0x40003800 0x400>;
344 interrupts = <36>;
345 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
346 status = "disabled";
347 };
349 spi3: spi@40003c00 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 compatible = "st,stm32f4-spi";
353 reg = <0x40003c00 0x400>;
354 interrupts = <51>;
355 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
356 status = "disabled";
357 };
359 usart2: serial@40004400 {
360 compatible = "st,stm32-uart";
361 reg = <0x40004400 0x400>;
362 interrupts = <38>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
364 status = "disabled";
365 };
367 usart3: serial@40004800 {
368 compatible = "st,stm32-uart";
369 reg = <0x40004800 0x400>;
370 interrupts = <39>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
372 status = "disabled";
373 dmas = <&dma1 1 4 0x400 0x0>,
374 <&dma1 3 4 0x400 0x0>;
375 dma-names = "rx", "tx";
376 };
378 usart4: serial@40004c00 {
379 compatible = "st,stm32-uart";
380 reg = <0x40004c00 0x400>;
381 interrupts = <52>;
382 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
383 status = "disabled";
384 };
386 usart5: serial@40005000 {
387 compatible = "st,stm32-uart";
388 reg = <0x40005000 0x400>;
389 interrupts = <53>;
390 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
391 status = "disabled";
392 };
394 i2c1: i2c@40005400 {
395 compatible = "st,stm32f4-i2c";
396 reg = <0x40005400 0x400>;
397 interrupts = <31>,
398 <32>;
399 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
400 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
406 dac: dac@40007400 {
407 compatible = "st,stm32f4-dac-core";
408 reg = <0x40007400 0x400>;
409 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
410 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
411 clock-names = "pclk";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 status = "disabled";
416 dac1: dac@1 {
417 compatible = "st,stm32-dac";
418 #io-channels-cells = <1>;
419 reg = <1>;
420 status = "disabled";
421 };
423 dac2: dac@2 {
424 compatible = "st,stm32-dac";
425 #io-channels-cells = <1>;
426 reg = <2>;
427 status = "disabled";
428 };
429 };
431 usart7: serial@40007800 {
432 compatible = "st,stm32-uart";
433 reg = <0x40007800 0x400>;
434 interrupts = <82>;
435 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
436 status = "disabled";
437 };
439 usart8: serial@40007c00 {
440 compatible = "st,stm32-uart";
441 reg = <0x40007c00 0x400>;
442 interrupts = <83>;
443 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
444 status = "disabled";
445 };
447 timers1: timers@40010000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "st,stm32-timers";
451 reg = <0x40010000 0x400>;
452 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
453 clock-names = "int";
454 status = "disabled";
456 pwm {
457 compatible = "st,stm32-pwm";
458 #pwm-cells = <3>;
459 status = "disabled";
460 };
462 timer@0 {
463 compatible = "st,stm32-timer-trigger";
464 reg = <0>;
465 status = "disabled";
466 };
467 };
469 timers8: timers@40010400 {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 compatible = "st,stm32-timers";
473 reg = <0x40010400 0x400>;
474 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
475 clock-names = "int";
476 status = "disabled";
478 pwm {
479 compatible = "st,stm32-pwm";
480 #pwm-cells = <3>;
481 status = "disabled";
482 };
484 timer@7 {
485 compatible = "st,stm32-timer-trigger";
486 reg = <7>;
487 status = "disabled";
488 };
489 };
491 usart1: serial@40011000 {
492 compatible = "st,stm32-uart";
493 reg = <0x40011000 0x400>;
494 interrupts = <37>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
496 status = "disabled";
497 dmas = <&dma2 2 4 0x400 0x0>,
498 <&dma2 7 4 0x400 0x0>;
499 dma-names = "rx", "tx";
500 };
502 usart6: serial@40011400 {
503 compatible = "st,stm32-uart";
504 reg = <0x40011400 0x400>;
505 interrupts = <71>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
507 status = "disabled";
508 };
510 adc: adc@40012000 {
511 compatible = "st,stm32f4-adc-core";
512 reg = <0x40012000 0x400>;
513 interrupts = <18>;
514 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
515 clock-names = "adc";
516 interrupt-controller;
517 #interrupt-cells = <1>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 status = "disabled";
522 adc1: adc@0 {
523 compatible = "st,stm32f4-adc";
524 #io-channel-cells = <1>;
525 reg = <0x0>;
526 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
527 interrupt-parent = <&adc>;
528 interrupts = <0>;
529 dmas = <&dma2 0 0 0x400 0x0>;
530 dma-names = "rx";
531 status = "disabled";
532 };
534 adc2: adc@100 {
535 compatible = "st,stm32f4-adc";
536 #io-channel-cells = <1>;
537 reg = <0x100>;
538 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
539 interrupt-parent = <&adc>;
540 interrupts = <1>;
541 dmas = <&dma2 3 1 0x400 0x0>;
542 dma-names = "rx";
543 status = "disabled";
544 };
546 adc3: adc@200 {
547 compatible = "st,stm32f4-adc";
548 #io-channel-cells = <1>;
549 reg = <0x200>;
550 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
551 interrupt-parent = <&adc>;
552 interrupts = <2>;
553 dmas = <&dma2 1 2 0x400 0x0>;
554 dma-names = "rx";
555 status = "disabled";
556 };
557 };
559 sdio: sdio@40012c00 {
560 compatible = "arm,pl180", "arm,primecell";
561 arm,primecell-periphid = <0x00880180>;
562 reg = <0x40012c00 0x400>;
563 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
564 clock-names = "apb_pclk";
565 interrupts = <49>;
566 max-frequency = <48000000>;
567 status = "disabled";
568 };
570 spi1: spi@40013000 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "st,stm32f4-spi";
574 reg = <0x40013000 0x400>;
575 interrupts = <35>;
576 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
577 status = "disabled";
578 };
580 spi4: spi@40013400 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "st,stm32f4-spi";
584 reg = <0x40013400 0x400>;
585 interrupts = <84>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
587 status = "disabled";
588 };
590 syscfg: system-config@40013800 {
591 compatible = "syscon";
592 reg = <0x40013800 0x400>;
593 };
595 exti: interrupt-controller@40013c00 {
596 compatible = "st,stm32-exti";
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 reg = <0x40013C00 0x400>;
600 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
601 };
603 timers9: timers@40014000 {
604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "st,stm32-timers";
607 reg = <0x40014000 0x400>;
608 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
609 clock-names = "int";
610 status = "disabled";
612 pwm {
613 compatible = "st,stm32-pwm";
614 #pwm-cells = <3>;
615 status = "disabled";
616 };
618 timer@8 {
619 compatible = "st,stm32-timer-trigger";
620 reg = <8>;
621 status = "disabled";
622 };
623 };
625 timers10: timers@40014400 {
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "st,stm32-timers";
629 reg = <0x40014400 0x400>;
630 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
631 clock-names = "int";
632 status = "disabled";
634 pwm {
635 compatible = "st,stm32-pwm";
636 #pwm-cells = <3>;
637 status = "disabled";
638 };
639 };
641 timers11: timers@40014800 {
642 #address-cells = <1>;
643 #size-cells = <0>;
644 compatible = "st,stm32-timers";
645 reg = <0x40014800 0x400>;
646 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
647 clock-names = "int";
648 status = "disabled";
650 pwm {
651 compatible = "st,stm32-pwm";
652 #pwm-cells = <3>;
653 status = "disabled";
654 };
655 };
657 spi5: spi@40015000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "st,stm32f4-spi";
661 reg = <0x40015000 0x400>;
662 interrupts = <85>;
663 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
664 status = "disabled";
665 };
667 spi6: spi@40015400 {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "st,stm32f4-spi";
671 reg = <0x40015400 0x400>;
672 interrupts = <86>;
673 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
674 status = "disabled";
675 };
677 pwrcfg: power-config@40007000 {
678 compatible = "syscon";
679 reg = <0x40007000 0x400>;
680 };
682 ltdc: display-controller@40016800 {
683 compatible = "st,stm32-ltdc";
684 reg = <0x40016800 0x200>;
685 interrupts = <88>, <89>;
686 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
687 clocks = <&rcc 1 CLK_LCD>;
688 clock-names = "lcd";
689 status = "disabled";
690 };
692 crc: crc@40023000 {
693 compatible = "st,stm32f4-crc";
694 reg = <0x40023000 0x400>;
695 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
696 status = "disabled";
697 };
699 rcc: rcc@40023810 {
700 #reset-cells = <1>;
701 #clock-cells = <2>;
702 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
703 reg = <0x40023800 0x400>;
704 clocks = <&clk_hse>, <&clk_i2s_ckin>;
705 st,syscfg = <&pwrcfg>;
706 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
707 assigned-clock-rates = <1000000>;
708 };
710 dma1: dma-controller@40026000 {
711 compatible = "st,stm32-dma";
712 reg = <0x40026000 0x400>;
713 interrupts = <11>,
714 <12>,
715 <13>,
716 <14>,
717 <15>,
718 <16>,
719 <17>,
720 <47>;
721 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
722 #dma-cells = <4>;
723 };
725 dma2: dma-controller@40026400 {
726 compatible = "st,stm32-dma";
727 reg = <0x40026400 0x400>;
728 interrupts = <56>,
729 <57>,
730 <58>,
731 <59>,
732 <60>,
733 <68>,
734 <69>,
735 <70>;
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
737 #dma-cells = <4>;
738 st,mem2mem;
739 };
741 mac: ethernet@40028000 {
742 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
743 reg = <0x40028000 0x8000>;
744 reg-names = "stmmaceth";
745 interrupts = <61>;
746 interrupt-names = "macirq";
747 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
748 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
749 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
750 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
751 st,syscon = <&syscfg 0x4>;
752 snps,pbl = <8>;
753 snps,mixed-burst;
754 status = "disabled";
755 };
757 usbotg_hs: usb@40040000 {
758 compatible = "snps,dwc2";
759 reg = <0x40040000 0x40000>;
760 interrupts = <77>;
761 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
762 clock-names = "otg";
763 status = "disabled";
764 };
766 usbotg_fs: usb@50000000 {
767 compatible = "st,stm32f4x9-fsotg";
768 reg = <0x50000000 0x40000>;
769 interrupts = <67>;
770 clocks = <&rcc 0 39>;
771 clock-names = "otg";
772 status = "disabled";
773 };
775 dcmi: dcmi@50050000 {
776 compatible = "st,stm32-dcmi";
777 reg = <0x50050000 0x400>;
778 interrupts = <78>;
779 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
780 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
781 clock-names = "mclk";
782 pinctrl-names = "default";
783 pinctrl-0 = <&dcmi_pins>;
784 dmas = <&dma2 1 1 0x414 0x3>;
785 dma-names = "tx";
786 status = "disabled";
787 };
789 rng: rng@50060800 {
790 compatible = "st,stm32-rng";
791 reg = <0x50060800 0x400>;
792 interrupts = <80>;
793 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
795 };
796 };
797 };
799 &systick {
800 clocks = <&rcc 1 SYSTICK>;
801 status = "okay";
802 };