| blob | 3d1ecb408b03fcd8becfe7ccb14c432ebd16adc3 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 / {
9 soc {
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
17 pins-are-numbered;
19 gpioa: gpio@50002000 {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
27 status = "disabled";
28 };
30 gpiob: gpio@50003000 {
31 gpio-controller;
32 #gpio-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 reg = <0x1000 0x400>;
36 clocks = <&rcc GPIOB>;
37 st,bank-name = "GPIOB";
38 status = "disabled";
39 };
41 gpioc: gpio@50004000 {
42 gpio-controller;
43 #gpio-cells = <2>;
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 reg = <0x2000 0x400>;
47 clocks = <&rcc GPIOC>;
48 st,bank-name = "GPIOC";
49 status = "disabled";
50 };
52 gpiod: gpio@50005000 {
53 gpio-controller;
54 #gpio-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 reg = <0x3000 0x400>;
58 clocks = <&rcc GPIOD>;
59 st,bank-name = "GPIOD";
60 status = "disabled";
61 };
63 gpioe: gpio@50006000 {
64 gpio-controller;
65 #gpio-cells = <2>;
66 interrupt-controller;
67 #interrupt-cells = <2>;
68 reg = <0x4000 0x400>;
69 clocks = <&rcc GPIOE>;
70 st,bank-name = "GPIOE";
71 status = "disabled";
72 };
74 gpiof: gpio@50007000 {
75 gpio-controller;
76 #gpio-cells = <2>;
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 reg = <0x5000 0x400>;
80 clocks = <&rcc GPIOF>;
81 st,bank-name = "GPIOF";
82 status = "disabled";
83 };
85 gpiog: gpio@50008000 {
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-controller;
89 #interrupt-cells = <2>;
90 reg = <0x6000 0x400>;
91 clocks = <&rcc GPIOG>;
92 st,bank-name = "GPIOG";
93 status = "disabled";
94 };
96 gpioh: gpio@50009000 {
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupt-cells = <2>;
101 reg = <0x7000 0x400>;
102 clocks = <&rcc GPIOH>;
103 st,bank-name = "GPIOH";
104 status = "disabled";
105 };
107 gpioi: gpio@5000a000 {
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 reg = <0x8000 0x400>;
113 clocks = <&rcc GPIOI>;
114 st,bank-name = "GPIOI";
115 status = "disabled";
116 };
118 gpioj: gpio@5000b000 {
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 reg = <0x9000 0x400>;
124 clocks = <&rcc GPIOJ>;
125 st,bank-name = "GPIOJ";
126 status = "disabled";
127 };
129 gpiok: gpio@5000c000 {
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 reg = <0xa000 0x400>;
135 clocks = <&rcc GPIOK>;
136 st,bank-name = "GPIOK";
137 status = "disabled";
138 };
140 adc12_ain_pins_a: adc12-ain-0 {
141 pins {
142 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
143 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
144 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
145 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
146 };
147 };
149 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
150 pins {
151 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
152 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
153 };
154 };
156 cec_pins_a: cec-0 {
157 pins {
158 pinmux = <STM32_PINMUX('A', 15, AF4)>;
159 bias-disable;
160 drive-open-drain;
161 slew-rate = <0>;
162 };
163 };
165 cec_pins_sleep_a: cec-sleep-0 {
166 pins {
167 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
168 };
169 };
171 cec_pins_b: cec-1 {
172 pins {
173 pinmux = <STM32_PINMUX('B', 6, AF5)>;
174 bias-disable;
175 drive-open-drain;
176 slew-rate = <0>;
177 };
178 };
180 cec_pins_sleep_b: cec-sleep-1 {
181 pins {
182 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
183 };
184 };
186 dac_ch1_pins_a: dac-ch1 {
187 pins {
188 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
189 };
190 };
192 dac_ch2_pins_a: dac-ch2 {
193 pins {
194 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
195 };
196 };
198 dcmi_pins_a: dcmi-0 {
199 pins {
200 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
201 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
202 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
203 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
204 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
205 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
206 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
207 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
208 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
209 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
210 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
211 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
212 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
213 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
214 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
215 bias-disable;
216 };
217 };
219 dcmi_sleep_pins_a: dcmi-sleep-0 {
220 pins {
221 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
222 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
223 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
224 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
225 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
226 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
227 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
228 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
229 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
230 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
231 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
232 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
233 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
234 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
235 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
236 };
237 };
239 ethernet0_rgmii_pins_a: rgmii-0 {
240 pins1 {
241 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
242 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
243 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
244 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
245 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
246 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
247 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
248 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
249 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
250 bias-disable;
251 drive-push-pull;
252 slew-rate = <3>;
253 };
254 pins2 {
255 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
256 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
257 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
258 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
259 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
260 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
261 bias-disable;
262 };
263 };
265 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
266 pins1 {
267 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
268 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
269 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
270 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
271 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
272 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
273 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
274 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
275 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
276 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
277 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
278 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
279 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
280 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
281 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
282 };
283 };
285 fmc_pins_a: fmc-0 {
286 pins1 {
287 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
288 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
289 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
290 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
291 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
292 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
293 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
294 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
295 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
296 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
297 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
298 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
299 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
300 bias-disable;
301 drive-push-pull;
302 slew-rate = <1>;
303 };
304 pins2 {
305 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
306 bias-pull-up;
307 };
308 };
310 fmc_sleep_pins_a: fmc-sleep-0 {
311 pins {
312 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
313 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
314 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
315 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
316 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
317 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
318 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
319 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
320 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
321 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
322 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
323 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
324 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
325 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
326 };
327 };
329 i2c1_pins_a: i2c1-0 {
330 pins {
331 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
332 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
333 bias-disable;
334 drive-open-drain;
335 slew-rate = <0>;
336 };
337 };
339 i2c1_pins_sleep_a: i2c1-1 {
340 pins {
341 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
342 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
343 };
344 };
346 i2c1_pins_b: i2c1-2 {
347 pins {
348 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
349 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
350 bias-disable;
351 drive-open-drain;
352 slew-rate = <0>;
353 };
354 };
356 i2c1_pins_sleep_b: i2c1-3 {
357 pins {
358 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
359 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
360 };
361 };
363 i2c2_pins_a: i2c2-0 {
364 pins {
365 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
366 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
367 bias-disable;
368 drive-open-drain;
369 slew-rate = <0>;
370 };
371 };
373 i2c2_pins_sleep_a: i2c2-1 {
374 pins {
375 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
376 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
377 };
378 };
380 i2c2_pins_b1: i2c2-2 {
381 pins {
382 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
383 bias-disable;
384 drive-open-drain;
385 slew-rate = <0>;
386 };
387 };
389 i2c2_pins_sleep_b1: i2c2-3 {
390 pins {
391 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
392 };
393 };
395 i2c5_pins_a: i2c5-0 {
396 pins {
397 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
398 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
399 bias-disable;
400 drive-open-drain;
401 slew-rate = <0>;
402 };
403 };
405 i2c5_pins_sleep_a: i2c5-1 {
406 pins {
407 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
408 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
410 };
411 };
413 i2s2_pins_a: i2s2-0 {
414 pins {
415 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
416 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
417 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
418 slew-rate = <1>;
419 drive-push-pull;
420 bias-disable;
421 };
422 };
424 i2s2_pins_sleep_a: i2s2-1 {
425 pins {
426 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
427 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
428 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
429 };
430 };
432 ltdc_pins_a: ltdc-a-0 {
433 pins {
434 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
435 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
436 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
437 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
438 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
439 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
440 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
441 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
442 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
443 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
444 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
445 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
446 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
447 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
448 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
449 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
450 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
451 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
452 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
453 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
454 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
455 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
456 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
457 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
458 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
459 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
460 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
461 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
462 bias-disable;
463 drive-push-pull;
464 slew-rate = <1>;
465 };
466 };
468 ltdc_pins_sleep_a: ltdc-a-1 {
469 pins {
470 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
471 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
472 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
473 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
474 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
475 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
476 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
477 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
478 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
479 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
480 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
481 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
482 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
483 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
484 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
485 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
486 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
487 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
488 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
489 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
490 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
491 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
492 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
493 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
494 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
495 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
496 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
497 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
498 };
499 };
501 ltdc_pins_b: ltdc-b-0 {
502 pins {
503 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
504 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
505 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
506 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
507 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
508 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
509 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
510 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
511 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
512 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
513 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
514 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
515 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
516 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
517 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
518 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
519 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
520 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
521 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
522 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
523 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
524 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
525 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
526 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
527 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
528 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
529 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
530 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
531 bias-disable;
532 drive-push-pull;
533 slew-rate = <1>;
534 };
535 };
537 ltdc_pins_sleep_b: ltdc-b-1 {
538 pins {
539 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
540 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
541 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
542 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
543 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
544 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
545 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
546 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
547 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
548 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
549 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
550 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
551 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
552 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
553 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
554 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
555 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
556 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
557 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
558 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
559 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
560 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
561 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
562 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
563 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
564 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
565 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
566 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
567 };
568 };
570 m_can1_pins_a: m-can1-0 {
571 pins1 {
572 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
573 slew-rate = <1>;
574 drive-push-pull;
575 bias-disable;
576 };
577 pins2 {
578 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
579 bias-disable;
580 };
581 };
583 m_can1_sleep_pins_a: m_can1-sleep-0 {
584 pins {
585 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
586 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
587 };
588 };
590 pwm2_pins_a: pwm2-0 {
591 pins {
592 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
593 bias-pull-down;
594 drive-push-pull;
595 slew-rate = <0>;
596 };
597 };
599 pwm8_pins_a: pwm8-0 {
600 pins {
601 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
602 bias-pull-down;
603 drive-push-pull;
604 slew-rate = <0>;
605 };
606 };
608 pwm12_pins_a: pwm12-0 {
609 pins {
610 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
611 bias-pull-down;
612 drive-push-pull;
613 slew-rate = <0>;
614 };
615 };
617 qspi_clk_pins_a: qspi-clk-0 {
618 pins {
619 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
620 bias-disable;
621 drive-push-pull;
622 slew-rate = <3>;
623 };
624 };
626 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
627 pins {
628 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
629 };
630 };
632 qspi_bk1_pins_a: qspi-bk1-0 {
633 pins1 {
634 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
635 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
636 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
637 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
638 bias-disable;
639 drive-push-pull;
640 slew-rate = <1>;
641 };
642 pins2 {
643 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
644 bias-pull-up;
645 drive-push-pull;
646 slew-rate = <1>;
647 };
648 };
650 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
651 pins {
652 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
653 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
654 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
655 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
656 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
657 };
658 };
660 qspi_bk2_pins_a: qspi-bk2-0 {
661 pins1 {
662 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
663 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
664 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
665 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
666 bias-disable;
667 drive-push-pull;
668 slew-rate = <1>;
669 };
670 pins2 {
671 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
672 bias-pull-up;
673 drive-push-pull;
674 slew-rate = <1>;
675 };
676 };
678 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
679 pins {
680 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
681 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
682 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
683 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
684 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
685 };
686 };
688 sai2a_pins_a: sai2a-0 {
689 pins {
690 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
691 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
692 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
693 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
694 slew-rate = <0>;
695 drive-push-pull;
696 bias-disable;
697 };
698 };
700 sai2a_sleep_pins_a: sai2a-1 {
701 pins {
702 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
703 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
704 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
705 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
706 };
707 };
709 sai2b_pins_a: sai2b-0 {
710 pins1 {
711 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
712 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
713 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
714 slew-rate = <0>;
715 drive-push-pull;
716 bias-disable;
717 };
718 pins2 {
719 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
720 bias-disable;
721 };
722 };
724 sai2b_sleep_pins_a: sai2b-1 {
725 pins {
726 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
727 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
728 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
729 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
730 };
731 };
733 sai2b_pins_b: sai2b-2 {
734 pins {
735 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
736 bias-disable;
737 };
738 };
740 sai2b_sleep_pins_b: sai2b-3 {
741 pins {
742 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
743 };
744 };
746 sai4a_pins_a: sai4a-0 {
747 pins {
748 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
749 slew-rate = <0>;
750 drive-push-pull;
751 bias-disable;
752 };
753 };
755 sai4a_sleep_pins_a: sai4a-1 {
756 pins {
757 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
758 };
759 };
761 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
762 pins {
763 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
764 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
765 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
766 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
767 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
768 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
769 slew-rate = <3>;
770 drive-push-pull;
771 bias-disable;
772 };
773 };
775 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
776 pins1 {
777 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
778 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
779 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
780 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
781 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
782 slew-rate = <3>;
783 drive-push-pull;
784 bias-disable;
785 };
786 pins2{
787 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
788 slew-rate = <3>;
789 drive-open-drain;
790 bias-disable;
791 };
792 };
794 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
795 pins {
796 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
797 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
798 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
799 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
800 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
801 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
802 };
803 };
805 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
806 pins1 {
807 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
808 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
809 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
810 slew-rate = <3>;
811 drive-push-pull;
812 bias-pull-up;
813 };
814 pins2{
815 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
816 bias-pull-up;
817 };
818 };
820 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
821 pins {
822 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
823 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
824 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
825 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
826 };
827 };
829 spdifrx_pins_a: spdifrx-0 {
830 pins {
831 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
832 bias-disable;
833 };
834 };
836 spdifrx_sleep_pins_a: spdifrx-1 {
837 pins {
838 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
839 };
840 };
842 uart4_pins_a: uart4-0 {
843 pins1 {
844 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
845 bias-disable;
846 drive-push-pull;
847 slew-rate = <0>;
848 };
849 pins2 {
850 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
851 bias-disable;
852 };
853 };
855 uart4_pins_b: uart4-1 {
856 pins1 {
857 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
858 bias-disable;
859 drive-push-pull;
860 slew-rate = <0>;
861 };
862 pins2 {
863 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
864 bias-disable;
865 };
866 };
868 uart7_pins_a: uart7-0 {
869 pins1 {
870 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
871 bias-disable;
872 drive-push-pull;
873 slew-rate = <0>;
874 };
875 pins2 {
876 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
877 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
878 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
879 bias-disable;
880 };
881 };
882 };
884 pinctrl_z: pin-controller-z@54004000 {
885 #address-cells = <1>;
886 #size-cells = <1>;
887 compatible = "st,stm32mp157-z-pinctrl";
888 ranges = <0 0x54004000 0x400>;
889 pins-are-numbered;
890 interrupt-parent = <&exti>;
891 st,syscfg = <&exti 0x60 0xff>;
893 gpioz: gpio@54004000 {
894 gpio-controller;
895 #gpio-cells = <2>;
896 interrupt-controller;
897 #interrupt-cells = <2>;
898 reg = <0 0x400>;
899 clocks = <&rcc GPIOZ>;
900 st,bank-name = "GPIOZ";
901 st,bank-ioport = <11>;
902 status = "disabled";
903 };
905 i2c2_pins_b2: i2c2-0 {
906 pins {
907 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
908 bias-disable;
909 drive-open-drain;
910 slew-rate = <0>;
911 };
912 };
914 i2c2_pins_sleep_b2: i2c2-1 {
915 pins {
916 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
917 };
918 };
920 i2c4_pins_a: i2c4-0 {
921 pins {
922 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
923 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
924 bias-disable;
925 drive-open-drain;
926 slew-rate = <0>;
927 };
928 };
930 i2c4_pins_sleep_a: i2c4-1 {
931 pins {
932 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
933 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
934 };
935 };
937 spi1_pins_a: spi1-0 {
938 pins1 {
939 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
940 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
941 bias-disable;
942 drive-push-pull;
943 slew-rate = <1>;
944 };
946 pins2 {
947 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
948 bias-disable;
949 };
950 };
951 };
952 };
953 };