| blob | 4c268b70b73571e1ec6a79a8093217aa25342b89 |
1 /*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
49 / {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
54 aliases {
55 ethernet0 = &emac;
56 };
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
70 status = "disabled";
71 };
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
82 status = "disabled";
83 };
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
93 status = "disabled";
94 };
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
98 "simple-framebuffer";
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
105 status = "disabled";
106 };
107 };
109 cpus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 cpu0: cpu@0 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a8";
115 reg = <0x0>;
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
118 operating-points = <
119 /* kHz uV */
120 1008000 1400000
121 912000 1350000
122 864000 1300000
123 624000 1250000
124 >;
125 #cooling-cells = <2>;
126 };
127 };
129 thermal-zones {
130 cpu-thermal {
131 /* milliseconds */
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
136 cooling-maps {
137 map0 {
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 };
141 };
143 trips {
144 cpu_alert0: cpu-alert0 {
145 /* milliCelsius */
146 temperature = <850000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
151 cpu_crit: cpu-crit {
152 /* milliCelsius */
153 temperature = <100000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159 };
161 clocks {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
166 osc24M: clk-24M {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
171 };
173 osc32k: clk-32k {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <32768>;
177 clock-output-names = "osc32k";
178 };
179 };
181 de: display-engine {
182 compatible = "allwinner,sun4i-a10-display-engine";
183 allwinner,pipelines = <&fe0>, <&fe1>;
184 status = "disabled";
185 };
187 pmu {
188 compatible = "arm,cortex-a8-pmu";
189 interrupts = <3>;
190 };
192 reserved-memory {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges;
197 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
198 default-pool {
199 compatible = "shared-dma-pool";
200 size = <0x6000000>;
201 alloc-ranges = <0x4a000000 0x6000000>;
202 reusable;
203 linux,cma-default;
204 };
205 };
207 soc {
208 compatible = "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges;
213 system-control@1c00000 {
214 compatible = "allwinner,sun4i-a10-system-control";
215 reg = <0x01c00000 0x30>;
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges;
220 sram_a: sram@0 {
221 compatible = "mmio-sram";
222 reg = <0x00000000 0xc000>;
223 #address-cells = <1>;
224 #size-cells = <1>;
225 ranges = <0 0x00000000 0xc000>;
227 emac_sram: sram-section@8000 {
228 compatible = "allwinner,sun4i-a10-sram-a3-a4";
229 reg = <0x8000 0x4000>;
230 status = "disabled";
231 };
232 };
234 sram_d: sram@10000 {
235 compatible = "mmio-sram";
236 reg = <0x00010000 0x1000>;
237 #address-cells = <1>;
238 #size-cells = <1>;
239 ranges = <0 0x00010000 0x1000>;
241 otg_sram: sram-section@0 {
242 compatible = "allwinner,sun4i-a10-sram-d";
243 reg = <0x0000 0x1000>;
244 status = "disabled";
245 };
246 };
248 sram_c: sram@1d00000 {
249 compatible = "mmio-sram";
250 reg = <0x01d00000 0xd0000>;
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0 0x01d00000 0xd0000>;
255 ve_sram: sram-section@0 {
256 compatible = "allwinner,sun4i-a10-sram-c1";
257 reg = <0x000000 0x80000>;
258 };
259 };
260 };
262 dma: dma-controller@1c02000 {
263 compatible = "allwinner,sun4i-a10-dma";
264 reg = <0x01c02000 0x1000>;
265 interrupts = <27>;
266 clocks = <&ccu CLK_AHB_DMA>;
267 #dma-cells = <2>;
268 };
270 nfc: nand-controller@1c03000 {
271 compatible = "allwinner,sun4i-a10-nand";
272 reg = <0x01c03000 0x1000>;
273 interrupts = <37>;
274 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
275 clock-names = "ahb", "mod";
276 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
277 dma-names = "rxtx";
278 status = "disabled";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 };
283 spi0: spi@1c05000 {
284 compatible = "allwinner,sun4i-a10-spi";
285 reg = <0x01c05000 0x1000>;
286 interrupts = <10>;
287 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
288 clock-names = "ahb", "mod";
289 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
290 <&dma SUN4I_DMA_DEDICATED 26>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 };
297 spi1: spi@1c06000 {
298 compatible = "allwinner,sun4i-a10-spi";
299 reg = <0x01c06000 0x1000>;
300 interrupts = <11>;
301 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
302 clock-names = "ahb", "mod";
303 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
304 <&dma SUN4I_DMA_DEDICATED 8>;
305 dma-names = "rx", "tx";
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
308 status = "disabled";
309 #address-cells = <1>;
310 #size-cells = <0>;
311 };
313 emac: ethernet@1c0b000 {
314 compatible = "allwinner,sun4i-a10-emac";
315 reg = <0x01c0b000 0x1000>;
316 interrupts = <55>;
317 clocks = <&ccu CLK_AHB_EMAC>;
318 allwinner,sram = <&emac_sram 1>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&emac_pins>;
321 status = "disabled";
322 };
324 mdio: mdio@1c0b080 {
325 compatible = "allwinner,sun4i-a10-mdio";
326 reg = <0x01c0b080 0x14>;
327 status = "disabled";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 };
332 tcon0: lcd-controller@1c0c000 {
333 compatible = "allwinner,sun4i-a10-tcon";
334 reg = <0x01c0c000 0x1000>;
335 interrupts = <44>;
336 resets = <&ccu RST_TCON0>;
337 reset-names = "lcd";
338 clocks = <&ccu CLK_AHB_LCD0>,
339 <&ccu CLK_TCON0_CH0>,
340 <&ccu CLK_TCON0_CH1>;
341 clock-names = "ahb",
342 "tcon-ch0",
343 "tcon-ch1";
344 clock-output-names = "tcon0-pixel-clock";
345 #clock-cells = <0>;
346 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
348 ports {
349 #address-cells = <1>;
350 #size-cells = <0>;
352 tcon0_in: port@0 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <0>;
357 tcon0_in_be0: endpoint@0 {
358 reg = <0>;
359 remote-endpoint = <&be0_out_tcon0>;
360 };
362 tcon0_in_be1: endpoint@1 {
363 reg = <1>;
364 remote-endpoint = <&be1_out_tcon0>;
365 };
366 };
368 tcon0_out: port@1 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <1>;
373 tcon0_out_hdmi: endpoint@1 {
374 reg = <1>;
375 remote-endpoint = <&hdmi_in_tcon0>;
376 allwinner,tcon-channel = <1>;
377 };
378 };
379 };
380 };
382 tcon1: lcd-controller@1c0d000 {
383 compatible = "allwinner,sun4i-a10-tcon";
384 reg = <0x01c0d000 0x1000>;
385 interrupts = <45>;
386 resets = <&ccu RST_TCON1>;
387 reset-names = "lcd";
388 clocks = <&ccu CLK_AHB_LCD1>,
389 <&ccu CLK_TCON1_CH0>,
390 <&ccu CLK_TCON1_CH1>;
391 clock-names = "ahb",
392 "tcon-ch0",
393 "tcon-ch1";
394 clock-output-names = "tcon1-pixel-clock";
395 #clock-cells = <0>;
396 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
398 ports {
399 #address-cells = <1>;
400 #size-cells = <0>;
402 tcon1_in: port@0 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 reg = <0>;
407 tcon1_in_be0: endpoint@0 {
408 reg = <0>;
409 remote-endpoint = <&be0_out_tcon1>;
410 };
412 tcon1_in_be1: endpoint@1 {
413 reg = <1>;
414 remote-endpoint = <&be1_out_tcon1>;
415 };
416 };
418 tcon1_out: port@1 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <1>;
423 tcon1_out_hdmi: endpoint@1 {
424 reg = <1>;
425 remote-endpoint = <&hdmi_in_tcon1>;
426 allwinner,tcon-channel = <1>;
427 };
428 };
429 };
430 };
432 video-codec@1c0e000 {
433 compatible = "allwinner,sun4i-a10-video-engine";
434 reg = <0x01c0e000 0x1000>;
435 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
436 <&ccu CLK_DRAM_VE>;
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_VE>;
439 interrupts = <53>;
440 allwinner,sram = <&ve_sram 1>;
441 };
443 mmc0: mmc@1c0f000 {
444 compatible = "allwinner,sun4i-a10-mmc";
445 reg = <0x01c0f000 0x1000>;
446 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
447 clock-names = "ahb", "mmc";
448 interrupts = <32>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&mmc0_pins>;
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 };
456 mmc1: mmc@1c10000 {
457 compatible = "allwinner,sun4i-a10-mmc";
458 reg = <0x01c10000 0x1000>;
459 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
460 clock-names = "ahb", "mmc";
461 interrupts = <33>;
462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
467 mmc2: mmc@1c11000 {
468 compatible = "allwinner,sun4i-a10-mmc";
469 reg = <0x01c11000 0x1000>;
470 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
471 clock-names = "ahb", "mmc";
472 interrupts = <34>;
473 status = "disabled";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 };
478 mmc3: mmc@1c12000 {
479 compatible = "allwinner,sun4i-a10-mmc";
480 reg = <0x01c12000 0x1000>;
481 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
482 clock-names = "ahb", "mmc";
483 interrupts = <35>;
484 status = "disabled";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 };
489 usb_otg: usb@1c13000 {
490 compatible = "allwinner,sun4i-a10-musb";
491 reg = <0x01c13000 0x0400>;
492 clocks = <&ccu CLK_AHB_OTG>;
493 interrupts = <38>;
494 interrupt-names = "mc";
495 phys = <&usbphy 0>;
496 phy-names = "usb";
497 extcon = <&usbphy 0>;
498 allwinner,sram = <&otg_sram 1>;
499 dr_mode = "otg";
500 status = "disabled";
501 };
503 usbphy: phy@1c13400 {
504 #phy-cells = <1>;
505 compatible = "allwinner,sun4i-a10-usb-phy";
506 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
507 reg-names = "phy_ctrl", "pmu1", "pmu2";
508 clocks = <&ccu CLK_USB_PHY>;
509 clock-names = "usb_phy";
510 resets = <&ccu RST_USB_PHY0>,
511 <&ccu RST_USB_PHY1>,
512 <&ccu RST_USB_PHY2>;
513 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
514 status = "disabled";
515 };
517 ehci0: usb@1c14000 {
518 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
519 reg = <0x01c14000 0x100>;
520 interrupts = <39>;
521 clocks = <&ccu CLK_AHB_EHCI0>;
522 phys = <&usbphy 1>;
523 phy-names = "usb";
524 status = "disabled";
525 };
527 ohci0: usb@1c14400 {
528 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
529 reg = <0x01c14400 0x100>;
530 interrupts = <64>;
531 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
532 phys = <&usbphy 1>;
533 phy-names = "usb";
534 status = "disabled";
535 };
537 crypto: crypto-engine@1c15000 {
538 compatible = "allwinner,sun4i-a10-crypto";
539 reg = <0x01c15000 0x1000>;
540 interrupts = <86>;
541 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
542 clock-names = "ahb", "mod";
543 };
545 hdmi: hdmi@1c16000 {
546 compatible = "allwinner,sun4i-a10-hdmi";
547 reg = <0x01c16000 0x1000>;
548 interrupts = <58>;
549 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
550 <&ccu CLK_PLL_VIDEO0_2X>,
551 <&ccu CLK_PLL_VIDEO1_2X>;
552 clock-names = "ahb", "mod", "pll-0", "pll-1";
553 dmas = <&dma SUN4I_DMA_NORMAL 16>,
554 <&dma SUN4I_DMA_NORMAL 16>,
555 <&dma SUN4I_DMA_DEDICATED 24>;
556 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
557 status = "disabled";
559 ports {
560 #address-cells = <1>;
561 #size-cells = <0>;
563 hdmi_in: port@0 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 reg = <0>;
568 hdmi_in_tcon0: endpoint@0 {
569 reg = <0>;
570 remote-endpoint = <&tcon0_out_hdmi>;
571 };
573 hdmi_in_tcon1: endpoint@1 {
574 reg = <1>;
575 remote-endpoint = <&tcon1_out_hdmi>;
576 };
577 };
579 hdmi_out: port@1 {
580 reg = <1>;
581 };
582 };
583 };
585 spi2: spi@1c17000 {
586 compatible = "allwinner,sun4i-a10-spi";
587 reg = <0x01c17000 0x1000>;
588 interrupts = <12>;
589 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
590 clock-names = "ahb", "mod";
591 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
592 <&dma SUN4I_DMA_DEDICATED 28>;
593 dma-names = "rx", "tx";
594 status = "disabled";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 };
599 ahci: sata@1c18000 {
600 compatible = "allwinner,sun4i-a10-ahci";
601 reg = <0x01c18000 0x1000>;
602 interrupts = <56>;
603 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
604 status = "disabled";
605 };
607 ehci1: usb@1c1c000 {
608 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
609 reg = <0x01c1c000 0x100>;
610 interrupts = <40>;
611 clocks = <&ccu CLK_AHB_EHCI1>;
612 phys = <&usbphy 2>;
613 phy-names = "usb";
614 status = "disabled";
615 };
617 ohci1: usb@1c1c400 {
618 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
619 reg = <0x01c1c400 0x100>;
620 interrupts = <65>;
621 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
622 phys = <&usbphy 2>;
623 phy-names = "usb";
624 status = "disabled";
625 };
627 spi3: spi@1c1f000 {
628 compatible = "allwinner,sun4i-a10-spi";
629 reg = <0x01c1f000 0x1000>;
630 interrupts = <50>;
631 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
632 clock-names = "ahb", "mod";
633 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
634 <&dma SUN4I_DMA_DEDICATED 30>;
635 dma-names = "rx", "tx";
636 status = "disabled";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 };
641 ccu: clock@1c20000 {
642 compatible = "allwinner,sun4i-a10-ccu";
643 reg = <0x01c20000 0x400>;
644 clocks = <&osc24M>, <&osc32k>;
645 clock-names = "hosc", "losc";
646 #clock-cells = <1>;
647 #reset-cells = <1>;
648 };
650 intc: interrupt-controller@1c20400 {
651 compatible = "allwinner,sun4i-a10-ic";
652 reg = <0x01c20400 0x400>;
653 interrupt-controller;
654 #interrupt-cells = <1>;
655 };
657 pio: pinctrl@1c20800 {
658 compatible = "allwinner,sun4i-a10-pinctrl";
659 reg = <0x01c20800 0x400>;
660 interrupts = <28>;
661 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
662 clock-names = "apb", "hosc", "losc";
663 gpio-controller;
664 interrupt-controller;
665 #interrupt-cells = <3>;
666 #gpio-cells = <3>;
668 can0_ph_pins: can0-ph-pins {
669 pins = "PH20", "PH21";
670 function = "can";
671 };
673 emac_pins: emac0-pins {
674 pins = "PA0", "PA1", "PA2",
675 "PA3", "PA4", "PA5", "PA6",
676 "PA7", "PA8", "PA9", "PA10",
677 "PA11", "PA12", "PA13", "PA14",
678 "PA15", "PA16";
679 function = "emac";
680 };
682 i2c0_pins: i2c0-pins {
683 pins = "PB0", "PB1";
684 function = "i2c0";
685 };
687 i2c1_pins: i2c1-pins {
688 pins = "PB18", "PB19";
689 function = "i2c1";
690 };
692 i2c2_pins: i2c2-pins {
693 pins = "PB20", "PB21";
694 function = "i2c2";
695 };
697 ir0_rx_pins: ir0-rx-pin {
698 pins = "PB4";
699 function = "ir0";
700 };
702 ir0_tx_pins: ir0-tx-pin {
703 pins = "PB3";
704 function = "ir0";
705 };
707 ir1_rx_pins: ir1-rx-pin {
708 pins = "PB23";
709 function = "ir1";
710 };
712 ir1_tx_pins: ir1-tx-pin {
713 pins = "PB22";
714 function = "ir1";
715 };
717 mmc0_pins: mmc0-pins {
718 pins = "PF0", "PF1", "PF2",
719 "PF3", "PF4", "PF5";
720 function = "mmc0";
721 drive-strength = <30>;
722 bias-pull-up;
723 };
725 ps2_ch0_pins: ps2-ch0-pins {
726 pins = "PI20", "PI21";
727 function = "ps2";
728 };
730 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
731 pins = "PH12", "PH13";
732 function = "ps2";
733 };
735 pwm0_pin: pwm0-pin {
736 pins = "PB2";
737 function = "pwm";
738 };
740 pwm1_pin: pwm1-pin {
741 pins = "PI3";
742 function = "pwm";
743 };
745 spdif_tx_pin: spdif-tx-pin {
746 pins = "PB13";
747 function = "spdif";
748 bias-pull-up;
749 };
751 spi0_pi_pins: spi0-pi-pins {
752 pins = "PI11", "PI12", "PI13";
753 function = "spi0";
754 };
756 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
757 pins = "PI10";
758 function = "spi0";
759 };
761 spi1_pins: spi1-pins {
762 pins = "PI17", "PI18", "PI19";
763 function = "spi1";
764 };
766 spi1_cs0_pin: spi1-cs0-pin {
767 pins = "PI16";
768 function = "spi1";
769 };
771 spi2_pb_pins: spi2-pb-pins {
772 pins = "PB15", "PB16", "PB17";
773 function = "spi2";
774 };
776 spi2_pc_pins: spi2-pc-pins {
777 pins = "PC20", "PC21", "PC22";
778 function = "spi2";
779 };
781 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
782 pins = "PB14";
783 function = "spi2";
784 };
786 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
787 pins = "PC19";
788 function = "spi2";
789 };
791 uart0_pb_pins: uart0-pb-pins {
792 pins = "PB22", "PB23";
793 function = "uart0";
794 };
796 uart0_pf_pins: uart0-pf-pins {
797 pins = "PF2", "PF4";
798 function = "uart0";
799 };
801 uart1_pins: uart1-pins {
802 pins = "PA10", "PA11";
803 function = "uart1";
804 };
805 };
807 timer@1c20c00 {
808 compatible = "allwinner,sun4i-a10-timer";
809 reg = <0x01c20c00 0x90>;
810 interrupts = <22>,
811 <23>,
812 <24>,
813 <25>,
814 <67>,
815 <68>;
816 clocks = <&osc24M>;
817 };
819 wdt: watchdog@1c20c90 {
820 compatible = "allwinner,sun4i-a10-wdt";
821 reg = <0x01c20c90 0x10>;
822 interrupts = <24>;
823 clocks = <&osc24M>;
824 };
826 rtc: rtc@1c20d00 {
827 compatible = "allwinner,sun4i-a10-rtc";
828 reg = <0x01c20d00 0x20>;
829 interrupts = <24>;
830 };
832 pwm: pwm@1c20e00 {
833 compatible = "allwinner,sun4i-a10-pwm";
834 reg = <0x01c20e00 0xc>;
835 clocks = <&osc24M>;
836 #pwm-cells = <3>;
837 status = "disabled";
838 };
840 spdif: spdif@1c21000 {
841 #sound-dai-cells = <0>;
842 compatible = "allwinner,sun4i-a10-spdif";
843 reg = <0x01c21000 0x400>;
844 interrupts = <13>;
845 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
846 clock-names = "apb", "spdif";
847 dmas = <&dma SUN4I_DMA_NORMAL 2>,
848 <&dma SUN4I_DMA_NORMAL 2>;
849 dma-names = "rx", "tx";
850 status = "disabled";
851 };
853 ir0: ir@1c21800 {
854 compatible = "allwinner,sun4i-a10-ir";
855 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
856 clock-names = "apb", "ir";
857 interrupts = <5>;
858 reg = <0x01c21800 0x40>;
859 status = "disabled";
860 };
862 ir1: ir@1c21c00 {
863 compatible = "allwinner,sun4i-a10-ir";
864 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
865 clock-names = "apb", "ir";
866 interrupts = <6>;
867 reg = <0x01c21c00 0x40>;
868 status = "disabled";
869 };
871 i2s0: i2s@1c22400 {
872 #sound-dai-cells = <0>;
873 compatible = "allwinner,sun4i-a10-i2s";
874 reg = <0x01c22400 0x400>;
875 interrupts = <16>;
876 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
877 clock-names = "apb", "mod";
878 dmas = <&dma SUN4I_DMA_NORMAL 3>,
879 <&dma SUN4I_DMA_NORMAL 3>;
880 dma-names = "rx", "tx";
881 status = "disabled";
882 };
884 lradc: lradc@1c22800 {
885 compatible = "allwinner,sun4i-a10-lradc-keys";
886 reg = <0x01c22800 0x100>;
887 interrupts = <31>;
888 status = "disabled";
889 };
891 codec: codec@1c22c00 {
892 #sound-dai-cells = <0>;
893 compatible = "allwinner,sun4i-a10-codec";
894 reg = <0x01c22c00 0x40>;
895 interrupts = <30>;
896 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
897 clock-names = "apb", "codec";
898 dmas = <&dma SUN4I_DMA_NORMAL 19>,
899 <&dma SUN4I_DMA_NORMAL 19>;
900 dma-names = "rx", "tx";
901 status = "disabled";
902 };
904 sid: eeprom@1c23800 {
905 compatible = "allwinner,sun4i-a10-sid";
906 reg = <0x01c23800 0x10>;
907 };
909 rtp: rtp@1c25000 {
910 compatible = "allwinner,sun4i-a10-ts";
911 reg = <0x01c25000 0x100>;
912 interrupts = <29>;
913 #thermal-sensor-cells = <0>;
914 };
916 uart0: serial@1c28000 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c28000 0x400>;
919 interrupts = <1>;
920 reg-shift = <2>;
921 reg-io-width = <4>;
922 clocks = <&ccu CLK_APB1_UART0>;
923 status = "disabled";
924 };
926 uart1: serial@1c28400 {
927 compatible = "snps,dw-apb-uart";
928 reg = <0x01c28400 0x400>;
929 interrupts = <2>;
930 reg-shift = <2>;
931 reg-io-width = <4>;
932 clocks = <&ccu CLK_APB1_UART1>;
933 status = "disabled";
934 };
936 uart2: serial@1c28800 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c28800 0x400>;
939 interrupts = <3>;
940 reg-shift = <2>;
941 reg-io-width = <4>;
942 clocks = <&ccu CLK_APB1_UART2>;
943 status = "disabled";
944 };
946 uart3: serial@1c28c00 {
947 compatible = "snps,dw-apb-uart";
948 reg = <0x01c28c00 0x400>;
949 interrupts = <4>;
950 reg-shift = <2>;
951 reg-io-width = <4>;
952 clocks = <&ccu CLK_APB1_UART3>;
953 status = "disabled";
954 };
956 uart4: serial@1c29000 {
957 compatible = "snps,dw-apb-uart";
958 reg = <0x01c29000 0x400>;
959 interrupts = <17>;
960 reg-shift = <2>;
961 reg-io-width = <4>;
962 clocks = <&ccu CLK_APB1_UART4>;
963 status = "disabled";
964 };
966 uart5: serial@1c29400 {
967 compatible = "snps,dw-apb-uart";
968 reg = <0x01c29400 0x400>;
969 interrupts = <18>;
970 reg-shift = <2>;
971 reg-io-width = <4>;
972 clocks = <&ccu CLK_APB1_UART5>;
973 status = "disabled";
974 };
976 uart6: serial@1c29800 {
977 compatible = "snps,dw-apb-uart";
978 reg = <0x01c29800 0x400>;
979 interrupts = <19>;
980 reg-shift = <2>;
981 reg-io-width = <4>;
982 clocks = <&ccu CLK_APB1_UART6>;
983 status = "disabled";
984 };
986 uart7: serial@1c29c00 {
987 compatible = "snps,dw-apb-uart";
988 reg = <0x01c29c00 0x400>;
989 interrupts = <20>;
990 reg-shift = <2>;
991 reg-io-width = <4>;
992 clocks = <&ccu CLK_APB1_UART7>;
993 status = "disabled";
994 };
996 ps20: ps2@1c2a000 {
997 compatible = "allwinner,sun4i-a10-ps2";
998 reg = <0x01c2a000 0x400>;
999 interrupts = <62>;
1000 clocks = <&ccu CLK_APB1_PS20>;
1001 status = "disabled";
1002 };
1004 ps21: ps2@1c2a400 {
1005 compatible = "allwinner,sun4i-a10-ps2";
1006 reg = <0x01c2a400 0x400>;
1007 interrupts = <63>;
1008 clocks = <&ccu CLK_APB1_PS21>;
1009 status = "disabled";
1010 };
1012 i2c0: i2c@1c2ac00 {
1013 compatible = "allwinner,sun4i-a10-i2c";
1014 reg = <0x01c2ac00 0x400>;
1015 interrupts = <7>;
1016 clocks = <&ccu CLK_APB1_I2C0>;
1017 pinctrl-names = "default";
1018 pinctrl-0 = <&i2c0_pins>;
1019 status = "disabled";
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 };
1024 i2c1: i2c@1c2b000 {
1025 compatible = "allwinner,sun4i-a10-i2c";
1026 reg = <0x01c2b000 0x400>;
1027 interrupts = <8>;
1028 clocks = <&ccu CLK_APB1_I2C1>;
1029 pinctrl-names = "default";
1030 pinctrl-0 = <&i2c1_pins>;
1031 status = "disabled";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 };
1036 i2c2: i2c@1c2b400 {
1037 compatible = "allwinner,sun4i-a10-i2c";
1038 reg = <0x01c2b400 0x400>;
1039 interrupts = <9>;
1040 clocks = <&ccu CLK_APB1_I2C2>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&i2c2_pins>;
1043 status = "disabled";
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 };
1048 can0: can@1c2bc00 {
1049 compatible = "allwinner,sun4i-a10-can";
1050 reg = <0x01c2bc00 0x400>;
1051 interrupts = <26>;
1052 clocks = <&ccu CLK_APB1_CAN>;
1053 status = "disabled";
1054 };
1056 mali: gpu@1c40000 {
1057 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1058 reg = <0x01c40000 0x10000>;
1059 interrupts = <69>,
1060 <70>,
1061 <71>,
1062 <72>,
1063 <73>;
1064 interrupt-names = "gp",
1065 "gpmmu",
1066 "pp0",
1067 "ppmmu0",
1068 "pmu";
1069 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1070 clock-names = "bus", "core";
1071 resets = <&ccu RST_GPU>;
1073 assigned-clocks = <&ccu CLK_GPU>;
1074 assigned-clock-rates = <384000000>;
1075 };
1077 fe0: display-frontend@1e00000 {
1078 compatible = "allwinner,sun4i-a10-display-frontend";
1079 reg = <0x01e00000 0x20000>;
1080 interrupts = <47>;
1081 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1082 <&ccu CLK_DRAM_DE_FE0>;
1083 clock-names = "ahb", "mod",
1084 "ram";
1085 resets = <&ccu RST_DE_FE0>;
1087 ports {
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1091 fe0_out: port@1 {
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 reg = <1>;
1096 fe0_out_be0: endpoint@0 {
1097 reg = <0>;
1098 remote-endpoint = <&be0_in_fe0>;
1099 };
1101 fe0_out_be1: endpoint@1 {
1102 reg = <1>;
1103 remote-endpoint = <&be1_in_fe0>;
1104 };
1105 };
1106 };
1107 };
1109 fe1: display-frontend@1e20000 {
1110 compatible = "allwinner,sun4i-a10-display-frontend";
1111 reg = <0x01e20000 0x20000>;
1112 interrupts = <48>;
1113 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1114 <&ccu CLK_DRAM_DE_FE1>;
1115 clock-names = "ahb", "mod",
1116 "ram";
1117 resets = <&ccu RST_DE_FE1>;
1119 ports {
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1123 fe1_out: port@1 {
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1126 reg = <1>;
1128 fe1_out_be0: endpoint@0 {
1129 reg = <0>;
1130 remote-endpoint = <&be0_in_fe1>;
1131 };
1133 fe1_out_be1: endpoint@1 {
1134 reg = <1>;
1135 remote-endpoint = <&be1_in_fe1>;
1136 };
1137 };
1138 };
1139 };
1141 be1: display-backend@1e40000 {
1142 compatible = "allwinner,sun4i-a10-display-backend";
1143 reg = <0x01e40000 0x10000>;
1144 interrupts = <48>;
1145 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1146 <&ccu CLK_DRAM_DE_BE1>;
1147 clock-names = "ahb", "mod",
1148 "ram";
1149 resets = <&ccu RST_DE_BE1>;
1151 ports {
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1155 be1_in: port@0 {
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 reg = <0>;
1160 be1_in_fe0: endpoint@0 {
1161 reg = <0>;
1162 remote-endpoint = <&fe0_out_be1>;
1163 };
1165 be1_in_fe1: endpoint@1 {
1166 reg = <1>;
1167 remote-endpoint = <&fe1_out_be1>;
1168 };
1169 };
1171 be1_out: port@1 {
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 reg = <1>;
1176 be1_out_tcon0: endpoint@0 {
1177 reg = <0>;
1178 remote-endpoint = <&tcon0_in_be1>;
1179 };
1181 be1_out_tcon1: endpoint@1 {
1182 reg = <1>;
1183 remote-endpoint = <&tcon1_in_be1>;
1184 };
1185 };
1186 };
1187 };
1189 be0: display-backend@1e60000 {
1190 compatible = "allwinner,sun4i-a10-display-backend";
1191 reg = <0x01e60000 0x10000>;
1192 interrupts = <47>;
1193 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1194 <&ccu CLK_DRAM_DE_BE0>;
1195 clock-names = "ahb", "mod",
1196 "ram";
1197 resets = <&ccu RST_DE_BE0>;
1199 ports {
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1203 be0_in: port@0 {
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 reg = <0>;
1208 be0_in_fe0: endpoint@0 {
1209 reg = <0>;
1210 remote-endpoint = <&fe0_out_be0>;
1211 };
1213 be0_in_fe1: endpoint@1 {
1214 reg = <1>;
1215 remote-endpoint = <&fe1_out_be0>;
1216 };
1217 };
1219 be0_out: port@1 {
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 reg = <1>;
1224 be0_out_tcon0: endpoint@0 {
1225 reg = <0>;
1226 remote-endpoint = <&tcon0_in_be0>;
1227 };
1229 be0_out_tcon1: endpoint@1 {
1230 reg = <1>;
1231 remote-endpoint = <&tcon1_in_be0>;
1232 };
1233 };
1234 };
1235 };
1236 };
1237 };