| blob | 2cf34ae1c17b21450bfb929b6c26ff42fbf13733 |
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
51 / {
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 aliases {
57 ethernet0 = &gmac;
58 };
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
65 simplefb_hdmi: framebuffer-lcd0-hdmi {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
73 status = "disabled";
74 };
76 simplefb_lcd: framebuffer-lcd0 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
83 status = "disabled";
84 };
85 };
87 timer {
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
95 };
97 cpus {
98 enable-method = "allwinner,sun6i-a31";
99 #address-cells = <1>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 1008000 1200000
111 864000 1200000
112 720000 1100000
113 480000 1000000
114 >;
115 #cooling-cells = <2>;
116 };
118 cpu1: cpu@1 {
119 compatible = "arm,cortex-a7";
120 device_type = "cpu";
121 reg = <1>;
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
124 operating-points = <
125 /* kHz uV */
126 1008000 1200000
127 864000 1200000
128 720000 1100000
129 480000 1000000
130 >;
131 #cooling-cells = <2>;
132 };
134 cpu2: cpu@2 {
135 compatible = "arm,cortex-a7";
136 device_type = "cpu";
137 reg = <2>;
138 clocks = <&ccu CLK_CPU>;
139 clock-latency = <244144>; /* 8 32k periods */
140 operating-points = <
141 /* kHz uV */
142 1008000 1200000
143 864000 1200000
144 720000 1100000
145 480000 1000000
146 >;
147 #cooling-cells = <2>;
148 };
150 cpu3: cpu@3 {
151 compatible = "arm,cortex-a7";
152 device_type = "cpu";
153 reg = <3>;
154 clocks = <&ccu CLK_CPU>;
155 clock-latency = <244144>; /* 8 32k periods */
156 operating-points = <
157 /* kHz uV */
158 1008000 1200000
159 864000 1200000
160 720000 1100000
161 480000 1000000
162 >;
163 #cooling-cells = <2>;
164 };
165 };
167 thermal-zones {
168 cpu_thermal {
169 /* milliseconds */
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172 thermal-sensors = <&rtp>;
174 cooling-maps {
175 map0 {
176 trip = <&cpu_alert0>;
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
181 };
182 };
184 trips {
185 cpu_alert0: cpu_alert0 {
186 /* milliCelsius */
187 temperature = <70000>;
188 hysteresis = <2000>;
189 type = "passive";
190 };
192 cpu_crit: cpu_crit {
193 /* milliCelsius */
194 temperature = <100000>;
195 hysteresis = <2000>;
196 type = "critical";
197 };
198 };
199 };
200 };
202 pmu {
203 compatible = "arm,cortex-a7-pmu";
204 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
208 };
210 clocks {
211 #address-cells = <1>;
212 #size-cells = <1>;
213 ranges;
215 osc24M: clk-24M {
216 #clock-cells = <0>;
217 compatible = "fixed-clock";
218 clock-frequency = <24000000>;
219 clock-accuracy = <50000>;
220 clock-output-names = "osc24M";
221 };
223 osc32k: clk-32k {
224 #clock-cells = <0>;
225 compatible = "fixed-clock";
226 clock-frequency = <32768>;
227 clock-accuracy = <50000>;
228 clock-output-names = "ext_osc32k";
229 };
231 /*
232 * The following two are dummy clocks, placeholders
233 * used in the gmac_tx clock. The gmac driver will
234 * choose one parent depending on the PHY interface
235 * mode, using clk_set_rate auto-reparenting.
236 *
237 * The actual TX clock rate is not controlled by the
238 * gmac_tx clock.
239 */
240 mii_phy_tx_clk: clk-mii-phy-tx {
241 #clock-cells = <0>;
242 compatible = "fixed-clock";
243 clock-frequency = <25000000>;
244 clock-output-names = "mii_phy_tx";
245 };
247 gmac_int_tx_clk: clk-gmac-int-tx {
248 #clock-cells = <0>;
249 compatible = "fixed-clock";
250 clock-frequency = <125000000>;
251 clock-output-names = "gmac_int_tx";
252 };
254 gmac_tx_clk: clk@1c200d0 {
255 #clock-cells = <0>;
256 compatible = "allwinner,sun7i-a20-gmac-clk";
257 reg = <0x01c200d0 0x4>;
258 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
259 clock-output-names = "gmac_tx";
260 };
261 };
263 de: display-engine {
264 compatible = "allwinner,sun6i-a31-display-engine";
265 allwinner,pipelines = <&fe0>, <&fe1>;
266 status = "disabled";
267 };
269 soc {
270 compatible = "simple-bus";
271 #address-cells = <1>;
272 #size-cells = <1>;
273 ranges;
275 dma: dma-controller@1c02000 {
276 compatible = "allwinner,sun6i-a31-dma";
277 reg = <0x01c02000 0x1000>;
278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_AHB1_DMA>;
280 resets = <&ccu RST_AHB1_DMA>;
281 #dma-cells = <1>;
282 };
284 tcon0: lcd-controller@1c0c000 {
285 compatible = "allwinner,sun6i-a31-tcon";
286 reg = <0x01c0c000 0x1000>;
287 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
288 resets = <&ccu RST_AHB1_LCD0>;
289 reset-names = "lcd";
290 clocks = <&ccu CLK_AHB1_LCD0>,
291 <&ccu CLK_LCD0_CH0>,
292 <&ccu CLK_LCD0_CH1>;
293 clock-names = "ahb",
294 "tcon-ch0",
295 "tcon-ch1";
296 clock-output-names = "tcon0-pixel-clock";
297 #clock-cells = <0>;
299 ports {
300 #address-cells = <1>;
301 #size-cells = <0>;
303 tcon0_in: port@0 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <0>;
308 tcon0_in_drc0: endpoint@0 {
309 reg = <0>;
310 remote-endpoint = <&drc0_out_tcon0>;
311 };
313 tcon0_in_drc1: endpoint@1 {
314 reg = <1>;
315 remote-endpoint = <&drc1_out_tcon0>;
316 };
317 };
319 tcon0_out: port@1 {
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <1>;
324 tcon0_out_hdmi: endpoint@1 {
325 reg = <1>;
326 remote-endpoint = <&hdmi_in_tcon0>;
327 allwinner,tcon-channel = <1>;
328 };
329 };
330 };
331 };
333 tcon1: lcd-controller@1c0d000 {
334 compatible = "allwinner,sun6i-a31-tcon";
335 reg = <0x01c0d000 0x1000>;
336 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
337 resets = <&ccu RST_AHB1_LCD1>;
338 reset-names = "lcd";
339 clocks = <&ccu CLK_AHB1_LCD1>,
340 <&ccu CLK_LCD1_CH0>,
341 <&ccu CLK_LCD1_CH1>;
342 clock-names = "ahb",
343 "tcon-ch0",
344 "tcon-ch1";
345 clock-output-names = "tcon1-pixel-clock";
346 #clock-cells = <0>;
348 ports {
349 #address-cells = <1>;
350 #size-cells = <0>;
352 tcon1_in: port@0 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <0>;
357 tcon1_in_drc0: endpoint@0 {
358 reg = <0>;
359 remote-endpoint = <&drc0_out_tcon1>;
360 };
362 tcon1_in_drc1: endpoint@1 {
363 reg = <1>;
364 remote-endpoint = <&drc1_out_tcon1>;
365 };
366 };
368 tcon1_out: port@1 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <1>;
373 tcon1_out_hdmi: endpoint@1 {
374 reg = <1>;
375 remote-endpoint = <&hdmi_in_tcon1>;
376 allwinner,tcon-channel = <1>;
377 };
378 };
379 };
380 };
382 mmc0: mmc@1c0f000 {
383 compatible = "allwinner,sun7i-a20-mmc";
384 reg = <0x01c0f000 0x1000>;
385 clocks = <&ccu CLK_AHB1_MMC0>,
386 <&ccu CLK_MMC0>,
387 <&ccu CLK_MMC0_OUTPUT>,
388 <&ccu CLK_MMC0_SAMPLE>;
389 clock-names = "ahb",
390 "mmc",
391 "output",
392 "sample";
393 resets = <&ccu RST_AHB1_MMC0>;
394 reset-names = "ahb";
395 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&mmc0_pins>;
398 status = "disabled";
399 #address-cells = <1>;
400 #size-cells = <0>;
401 };
403 mmc1: mmc@1c10000 {
404 compatible = "allwinner,sun7i-a20-mmc";
405 reg = <0x01c10000 0x1000>;
406 clocks = <&ccu CLK_AHB1_MMC1>,
407 <&ccu CLK_MMC1>,
408 <&ccu CLK_MMC1_OUTPUT>,
409 <&ccu CLK_MMC1_SAMPLE>;
410 clock-names = "ahb",
411 "mmc",
412 "output",
413 "sample";
414 resets = <&ccu RST_AHB1_MMC1>;
415 reset-names = "ahb";
416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&mmc1_pins>;
419 status = "disabled";
420 #address-cells = <1>;
421 #size-cells = <0>;
422 };
424 mmc2: mmc@1c11000 {
425 compatible = "allwinner,sun7i-a20-mmc";
426 reg = <0x01c11000 0x1000>;
427 clocks = <&ccu CLK_AHB1_MMC2>,
428 <&ccu CLK_MMC2>,
429 <&ccu CLK_MMC2_OUTPUT>,
430 <&ccu CLK_MMC2_SAMPLE>;
431 clock-names = "ahb",
432 "mmc",
433 "output",
434 "sample";
435 resets = <&ccu RST_AHB1_MMC2>;
436 reset-names = "ahb";
437 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
438 status = "disabled";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 };
443 mmc3: mmc@1c12000 {
444 compatible = "allwinner,sun7i-a20-mmc";
445 reg = <0x01c12000 0x1000>;
446 clocks = <&ccu CLK_AHB1_MMC3>,
447 <&ccu CLK_MMC3>,
448 <&ccu CLK_MMC3_OUTPUT>,
449 <&ccu CLK_MMC3_SAMPLE>;
450 clock-names = "ahb",
451 "mmc",
452 "output",
453 "sample";
454 resets = <&ccu RST_AHB1_MMC3>;
455 reset-names = "ahb";
456 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
457 status = "disabled";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 };
462 hdmi: hdmi@1c16000 {
463 compatible = "allwinner,sun6i-a31-hdmi";
464 reg = <0x01c16000 0x1000>;
465 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
467 <&ccu CLK_HDMI_DDC>,
468 <&ccu CLK_PLL_VIDEO0_2X>,
469 <&ccu CLK_PLL_VIDEO1_2X>;
470 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
471 resets = <&ccu RST_AHB1_HDMI>;
472 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
473 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
474 status = "disabled";
476 ports {
477 #address-cells = <1>;
478 #size-cells = <0>;
480 hdmi_in: port@0 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 reg = <0>;
485 hdmi_in_tcon0: endpoint@0 {
486 reg = <0>;
487 remote-endpoint = <&tcon0_out_hdmi>;
488 };
490 hdmi_in_tcon1: endpoint@1 {
491 reg = <1>;
492 remote-endpoint = <&tcon1_out_hdmi>;
493 };
494 };
496 hdmi_out: port@1 {
497 reg = <1>;
498 };
499 };
500 };
502 usb_otg: usb@1c19000 {
503 compatible = "allwinner,sun6i-a31-musb";
504 reg = <0x01c19000 0x0400>;
505 clocks = <&ccu CLK_AHB1_OTG>;
506 resets = <&ccu RST_AHB1_OTG>;
507 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
508 interrupt-names = "mc";
509 phys = <&usbphy 0>;
510 phy-names = "usb";
511 extcon = <&usbphy 0>;
512 dr_mode = "otg";
513 status = "disabled";
514 };
516 usbphy: phy@1c19400 {
517 compatible = "allwinner,sun6i-a31-usb-phy";
518 reg = <0x01c19400 0x10>,
519 <0x01c1a800 0x4>,
520 <0x01c1b800 0x4>;
521 reg-names = "phy_ctrl",
522 "pmu1",
523 "pmu2";
524 clocks = <&ccu CLK_USB_PHY0>,
525 <&ccu CLK_USB_PHY1>,
526 <&ccu CLK_USB_PHY2>;
527 clock-names = "usb0_phy",
528 "usb1_phy",
529 "usb2_phy";
530 resets = <&ccu RST_USB_PHY0>,
531 <&ccu RST_USB_PHY1>,
532 <&ccu RST_USB_PHY2>;
533 reset-names = "usb0_reset",
534 "usb1_reset",
535 "usb2_reset";
536 status = "disabled";
537 #phy-cells = <1>;
538 };
540 ehci0: usb@1c1a000 {
541 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
542 reg = <0x01c1a000 0x100>;
543 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&ccu CLK_AHB1_EHCI0>;
545 resets = <&ccu RST_AHB1_EHCI0>;
546 phys = <&usbphy 1>;
547 phy-names = "usb";
548 status = "disabled";
549 };
551 ohci0: usb@1c1a400 {
552 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
553 reg = <0x01c1a400 0x100>;
554 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
556 resets = <&ccu RST_AHB1_OHCI0>;
557 phys = <&usbphy 1>;
558 phy-names = "usb";
559 status = "disabled";
560 };
562 ehci1: usb@1c1b000 {
563 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
564 reg = <0x01c1b000 0x100>;
565 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ccu CLK_AHB1_EHCI1>;
567 resets = <&ccu RST_AHB1_EHCI1>;
568 phys = <&usbphy 2>;
569 phy-names = "usb";
570 status = "disabled";
571 };
573 ohci1: usb@1c1b400 {
574 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
575 reg = <0x01c1b400 0x100>;
576 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
578 resets = <&ccu RST_AHB1_OHCI1>;
579 phys = <&usbphy 2>;
580 phy-names = "usb";
581 status = "disabled";
582 };
584 ohci2: usb@1c1c400 {
585 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
586 reg = <0x01c1c400 0x100>;
587 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
589 resets = <&ccu RST_AHB1_OHCI2>;
590 status = "disabled";
591 };
593 ccu: clock@1c20000 {
594 compatible = "allwinner,sun6i-a31-ccu";
595 reg = <0x01c20000 0x400>;
596 clocks = <&osc24M>, <&rtc 0>;
597 clock-names = "hosc", "losc";
598 #clock-cells = <1>;
599 #reset-cells = <1>;
600 };
602 pio: pinctrl@1c20800 {
603 compatible = "allwinner,sun6i-a31-pinctrl";
604 reg = <0x01c20800 0x400>;
605 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
610 clock-names = "apb", "hosc", "losc";
611 gpio-controller;
612 interrupt-controller;
613 #interrupt-cells = <3>;
614 #gpio-cells = <3>;
616 gmac_gmii_pins: gmac-gmii-pins {
617 pins = "PA0", "PA1", "PA2", "PA3",
618 "PA4", "PA5", "PA6", "PA7",
619 "PA8", "PA9", "PA10", "PA11",
620 "PA12", "PA13", "PA14", "PA15",
621 "PA16", "PA17", "PA18", "PA19",
622 "PA20", "PA21", "PA22", "PA23",
623 "PA24", "PA25", "PA26", "PA27";
624 function = "gmac";
625 /*
626 * data lines in GMII mode run at 125MHz and
627 * might need a higher signal drive strength
628 */
629 drive-strength = <30>;
630 };
632 gmac_mii_pins: gmac-mii-pins {
633 pins = "PA0", "PA1", "PA2", "PA3",
634 "PA8", "PA9", "PA11",
635 "PA12", "PA13", "PA14", "PA19",
636 "PA20", "PA21", "PA22", "PA23",
637 "PA24", "PA26", "PA27";
638 function = "gmac";
639 };
641 gmac_rgmii_pins: gmac-rgmii-pins {
642 pins = "PA0", "PA1", "PA2", "PA3",
643 "PA9", "PA10", "PA11",
644 "PA12", "PA13", "PA14", "PA19",
645 "PA20", "PA25", "PA26", "PA27";
646 function = "gmac";
647 /*
648 * data lines in RGMII mode use DDR mode
649 * and need a higher signal drive strength
650 */
651 drive-strength = <40>;
652 };
654 i2c0_pins: i2c0-pins {
655 pins = "PH14", "PH15";
656 function = "i2c0";
657 };
659 i2c1_pins: i2c1-pins {
660 pins = "PH16", "PH17";
661 function = "i2c1";
662 };
664 i2c2_pins: i2c2-pins {
665 pins = "PH18", "PH19";
666 function = "i2c2";
667 };
669 lcd0_rgb888_pins: lcd0-rgb888-pins {
670 pins = "PD0", "PD1", "PD2", "PD3",
671 "PD4", "PD5", "PD6", "PD7",
672 "PD8", "PD9", "PD10", "PD11",
673 "PD12", "PD13", "PD14", "PD15",
674 "PD16", "PD17", "PD18", "PD19",
675 "PD20", "PD21", "PD22", "PD23",
676 "PD24", "PD25", "PD26", "PD27";
677 function = "lcd0";
678 };
680 mmc0_pins: mmc0-pins {
681 pins = "PF0", "PF1", "PF2",
682 "PF3", "PF4", "PF5";
683 function = "mmc0";
684 drive-strength = <30>;
685 bias-pull-up;
686 };
688 mmc1_pins: mmc1-pins {
689 pins = "PG0", "PG1", "PG2", "PG3",
690 "PG4", "PG5";
691 function = "mmc1";
692 drive-strength = <30>;
693 bias-pull-up;
694 };
696 mmc2_4bit_pins: mmc2-4bit-pins {
697 pins = "PC6", "PC7", "PC8", "PC9",
698 "PC10", "PC11";
699 function = "mmc2";
700 drive-strength = <30>;
701 bias-pull-up;
702 };
704 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
705 pins = "PC6", "PC7", "PC8", "PC9",
706 "PC10", "PC11", "PC12",
707 "PC13", "PC14", "PC15",
708 "PC24";
709 function = "mmc2";
710 drive-strength = <30>;
711 bias-pull-up;
712 };
714 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
715 pins = "PC6", "PC7", "PC8", "PC9",
716 "PC10", "PC11", "PC12",
717 "PC13", "PC14", "PC15",
718 "PC24";
719 function = "mmc3";
720 drive-strength = <40>;
721 bias-pull-up;
722 };
724 spdif_tx_pin: spdif-tx-pin {
725 pins = "PH28";
726 function = "spdif";
727 };
729 uart0_ph_pins: uart0-ph-pins {
730 pins = "PH20", "PH21";
731 function = "uart0";
732 };
733 };
735 timer@1c20c00 {
736 compatible = "allwinner,sun4i-a10-timer";
737 reg = <0x01c20c00 0xa0>;
738 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&osc24M>;
745 };
747 wdt1: watchdog@1c20ca0 {
748 compatible = "allwinner,sun6i-a31-wdt";
749 reg = <0x01c20ca0 0x20>;
750 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&osc24M>;
752 };
754 spdif: spdif@1c21000 {
755 #sound-dai-cells = <0>;
756 compatible = "allwinner,sun6i-a31-spdif";
757 reg = <0x01c21000 0x400>;
758 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
760 resets = <&ccu RST_APB1_SPDIF>;
761 clock-names = "apb", "spdif";
762 dmas = <&dma 2>, <&dma 2>;
763 dma-names = "rx", "tx";
764 status = "disabled";
765 };
767 i2s0: i2s@1c22000 {
768 #sound-dai-cells = <0>;
769 compatible = "allwinner,sun6i-a31-i2s";
770 reg = <0x01c22000 0x400>;
771 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
773 resets = <&ccu RST_APB1_DAUDIO0>;
774 clock-names = "apb", "mod";
775 dmas = <&dma 3>, <&dma 3>;
776 dma-names = "rx", "tx";
777 status = "disabled";
778 };
780 i2s1: i2s@1c22400 {
781 #sound-dai-cells = <0>;
782 compatible = "allwinner,sun6i-a31-i2s";
783 reg = <0x01c22400 0x400>;
784 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
786 resets = <&ccu RST_APB1_DAUDIO1>;
787 clock-names = "apb", "mod";
788 dmas = <&dma 4>, <&dma 4>;
789 dma-names = "rx", "tx";
790 status = "disabled";
791 };
793 lradc: lradc@1c22800 {
794 compatible = "allwinner,sun4i-a10-lradc-keys";
795 reg = <0x01c22800 0x100>;
796 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
797 status = "disabled";
798 };
800 rtp: rtp@1c25000 {
801 compatible = "allwinner,sun6i-a31-ts";
802 reg = <0x01c25000 0x100>;
803 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
804 #thermal-sensor-cells = <0>;
805 };
807 uart0: serial@1c28000 {
808 compatible = "snps,dw-apb-uart";
809 reg = <0x01c28000 0x400>;
810 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
811 reg-shift = <2>;
812 reg-io-width = <4>;
813 clocks = <&ccu CLK_APB2_UART0>;
814 resets = <&ccu RST_APB2_UART0>;
815 dmas = <&dma 6>, <&dma 6>;
816 dma-names = "rx", "tx";
817 status = "disabled";
818 };
820 uart1: serial@1c28400 {
821 compatible = "snps,dw-apb-uart";
822 reg = <0x01c28400 0x400>;
823 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
824 reg-shift = <2>;
825 reg-io-width = <4>;
826 clocks = <&ccu CLK_APB2_UART1>;
827 resets = <&ccu RST_APB2_UART1>;
828 dmas = <&dma 7>, <&dma 7>;
829 dma-names = "rx", "tx";
830 status = "disabled";
831 };
833 uart2: serial@1c28800 {
834 compatible = "snps,dw-apb-uart";
835 reg = <0x01c28800 0x400>;
836 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
837 reg-shift = <2>;
838 reg-io-width = <4>;
839 clocks = <&ccu CLK_APB2_UART2>;
840 resets = <&ccu RST_APB2_UART2>;
841 dmas = <&dma 8>, <&dma 8>;
842 dma-names = "rx", "tx";
843 status = "disabled";
844 };
846 uart3: serial@1c28c00 {
847 compatible = "snps,dw-apb-uart";
848 reg = <0x01c28c00 0x400>;
849 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
850 reg-shift = <2>;
851 reg-io-width = <4>;
852 clocks = <&ccu CLK_APB2_UART3>;
853 resets = <&ccu RST_APB2_UART3>;
854 dmas = <&dma 9>, <&dma 9>;
855 dma-names = "rx", "tx";
856 status = "disabled";
857 };
859 uart4: serial@1c29000 {
860 compatible = "snps,dw-apb-uart";
861 reg = <0x01c29000 0x400>;
862 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
863 reg-shift = <2>;
864 reg-io-width = <4>;
865 clocks = <&ccu CLK_APB2_UART4>;
866 resets = <&ccu RST_APB2_UART4>;
867 dmas = <&dma 10>, <&dma 10>;
868 dma-names = "rx", "tx";
869 status = "disabled";
870 };
872 uart5: serial@1c29400 {
873 compatible = "snps,dw-apb-uart";
874 reg = <0x01c29400 0x400>;
875 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
876 reg-shift = <2>;
877 reg-io-width = <4>;
878 clocks = <&ccu CLK_APB2_UART5>;
879 resets = <&ccu RST_APB2_UART5>;
880 dmas = <&dma 22>, <&dma 22>;
881 dma-names = "rx", "tx";
882 status = "disabled";
883 };
885 i2c0: i2c@1c2ac00 {
886 compatible = "allwinner,sun6i-a31-i2c";
887 reg = <0x01c2ac00 0x400>;
888 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&ccu CLK_APB2_I2C0>;
890 resets = <&ccu RST_APB2_I2C0>;
891 pinctrl-names = "default";
892 pinctrl-0 = <&i2c0_pins>;
893 status = "disabled";
894 #address-cells = <1>;
895 #size-cells = <0>;
896 };
898 i2c1: i2c@1c2b000 {
899 compatible = "allwinner,sun6i-a31-i2c";
900 reg = <0x01c2b000 0x400>;
901 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&ccu CLK_APB2_I2C1>;
903 resets = <&ccu RST_APB2_I2C1>;
904 pinctrl-names = "default";
905 pinctrl-0 = <&i2c1_pins>;
906 status = "disabled";
907 #address-cells = <1>;
908 #size-cells = <0>;
909 };
911 i2c2: i2c@1c2b400 {
912 compatible = "allwinner,sun6i-a31-i2c";
913 reg = <0x01c2b400 0x400>;
914 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&ccu CLK_APB2_I2C2>;
916 resets = <&ccu RST_APB2_I2C2>;
917 pinctrl-names = "default";
918 pinctrl-0 = <&i2c2_pins>;
919 status = "disabled";
920 #address-cells = <1>;
921 #size-cells = <0>;
922 };
924 i2c3: i2c@1c2b800 {
925 compatible = "allwinner,sun6i-a31-i2c";
926 reg = <0x01c2b800 0x400>;
927 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&ccu CLK_APB2_I2C3>;
929 resets = <&ccu RST_APB2_I2C3>;
930 status = "disabled";
931 #address-cells = <1>;
932 #size-cells = <0>;
933 };
935 gmac: ethernet@1c30000 {
936 compatible = "allwinner,sun7i-a20-gmac";
937 reg = <0x01c30000 0x1054>;
938 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "macirq";
940 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
941 clock-names = "stmmaceth", "allwinner_gmac_tx";
942 resets = <&ccu RST_AHB1_EMAC>;
943 reset-names = "stmmaceth";
944 snps,pbl = <2>;
945 snps,fixed-burst;
946 snps,force_sf_dma_mode;
947 status = "disabled";
949 mdio: mdio {
950 compatible = "snps,dwmac-mdio";
951 #address-cells = <1>;
952 #size-cells = <0>;
953 };
954 };
956 crypto: crypto-engine@1c15000 {
957 compatible = "allwinner,sun6i-a31-crypto",
958 "allwinner,sun4i-a10-crypto";
959 reg = <0x01c15000 0x1000>;
960 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
962 clock-names = "ahb", "mod";
963 resets = <&ccu RST_AHB1_SS>;
964 reset-names = "ahb";
965 };
967 codec: codec@1c22c00 {
968 #sound-dai-cells = <0>;
969 compatible = "allwinner,sun6i-a31-codec";
970 reg = <0x01c22c00 0x400>;
971 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
973 clock-names = "apb", "codec";
974 resets = <&ccu RST_APB1_CODEC>;
975 dmas = <&dma 15>, <&dma 15>;
976 dma-names = "rx", "tx";
977 status = "disabled";
978 };
980 timer@1c60000 {
981 compatible = "allwinner,sun6i-a31-hstimer",
982 "allwinner,sun7i-a20-hstimer";
983 reg = <0x01c60000 0x1000>;
984 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&ccu CLK_AHB1_HSTIMER>;
989 resets = <&ccu RST_AHB1_HSTIMER>;
990 };
992 spi0: spi@1c68000 {
993 compatible = "allwinner,sun6i-a31-spi";
994 reg = <0x01c68000 0x1000>;
995 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
997 clock-names = "ahb", "mod";
998 dmas = <&dma 23>, <&dma 23>;
999 dma-names = "rx", "tx";
1000 resets = <&ccu RST_AHB1_SPI0>;
1001 status = "disabled";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 };
1006 spi1: spi@1c69000 {
1007 compatible = "allwinner,sun6i-a31-spi";
1008 reg = <0x01c69000 0x1000>;
1009 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1011 clock-names = "ahb", "mod";
1012 dmas = <&dma 24>, <&dma 24>;
1013 dma-names = "rx", "tx";
1014 resets = <&ccu RST_AHB1_SPI1>;
1015 status = "disabled";
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 };
1020 spi2: spi@1c6a000 {
1021 compatible = "allwinner,sun6i-a31-spi";
1022 reg = <0x01c6a000 0x1000>;
1023 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1025 clock-names = "ahb", "mod";
1026 dmas = <&dma 25>, <&dma 25>;
1027 dma-names = "rx", "tx";
1028 resets = <&ccu RST_AHB1_SPI2>;
1029 status = "disabled";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 };
1034 spi3: spi@1c6b000 {
1035 compatible = "allwinner,sun6i-a31-spi";
1036 reg = <0x01c6b000 0x1000>;
1037 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1039 clock-names = "ahb", "mod";
1040 dmas = <&dma 26>, <&dma 26>;
1041 dma-names = "rx", "tx";
1042 resets = <&ccu RST_AHB1_SPI3>;
1043 status = "disabled";
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 };
1048 gic: interrupt-controller@1c81000 {
1049 compatible = "arm,gic-400";
1050 reg = <0x01c81000 0x1000>,
1051 <0x01c82000 0x2000>,
1052 <0x01c84000 0x2000>,
1053 <0x01c86000 0x2000>;
1054 interrupt-controller;
1055 #interrupt-cells = <3>;
1056 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1057 };
1059 fe0: display-frontend@1e00000 {
1060 compatible = "allwinner,sun6i-a31-display-frontend";
1061 reg = <0x01e00000 0x20000>;
1062 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1064 <&ccu CLK_DRAM_FE0>;
1065 clock-names = "ahb", "mod",
1066 "ram";
1067 resets = <&ccu RST_AHB1_FE0>;
1069 ports {
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1073 fe0_out: port@1 {
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076 reg = <1>;
1078 fe0_out_be0: endpoint@0 {
1079 reg = <0>;
1080 remote-endpoint = <&be0_in_fe0>;
1081 };
1083 fe0_out_be1: endpoint@1 {
1084 reg = <1>;
1085 remote-endpoint = <&be1_in_fe0>;
1086 };
1087 };
1088 };
1089 };
1091 fe1: display-frontend@1e20000 {
1092 compatible = "allwinner,sun6i-a31-display-frontend";
1093 reg = <0x01e20000 0x20000>;
1094 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1096 <&ccu CLK_DRAM_FE1>;
1097 clock-names = "ahb", "mod",
1098 "ram";
1099 resets = <&ccu RST_AHB1_FE1>;
1101 ports {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1105 fe1_out: port@1 {
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 reg = <1>;
1110 fe1_out_be0: endpoint@0 {
1111 reg = <0>;
1112 remote-endpoint = <&be0_in_fe1>;
1113 };
1115 fe1_out_be1: endpoint@1 {
1116 reg = <1>;
1117 remote-endpoint = <&be1_in_fe1>;
1118 };
1119 };
1120 };
1121 };
1123 be1: display-backend@1e40000 {
1124 compatible = "allwinner,sun6i-a31-display-backend";
1125 reg = <0x01e40000 0x10000>;
1126 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1128 <&ccu CLK_DRAM_BE1>;
1129 clock-names = "ahb", "mod",
1130 "ram";
1131 resets = <&ccu RST_AHB1_BE1>;
1133 assigned-clocks = <&ccu CLK_BE1>;
1134 assigned-clock-rates = <300000000>;
1136 ports {
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1140 be1_in: port@0 {
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 reg = <0>;
1145 be1_in_fe0: endpoint@0 {
1146 reg = <0>;
1147 remote-endpoint = <&fe0_out_be1>;
1148 };
1150 be1_in_fe1: endpoint@1 {
1151 reg = <1>;
1152 remote-endpoint = <&fe1_out_be1>;
1153 };
1154 };
1156 be1_out: port@1 {
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 reg = <1>;
1161 be1_out_drc1: endpoint@1 {
1162 reg = <1>;
1163 remote-endpoint = <&drc1_in_be1>;
1164 };
1165 };
1166 };
1167 };
1169 drc1: drc@1e50000 {
1170 compatible = "allwinner,sun6i-a31-drc";
1171 reg = <0x01e50000 0x10000>;
1172 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1173 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1174 <&ccu CLK_DRAM_DRC1>;
1175 clock-names = "ahb", "mod",
1176 "ram";
1177 resets = <&ccu RST_AHB1_DRC1>;
1179 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1180 assigned-clock-rates = <300000000>;
1182 ports {
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1186 drc1_in: port@0 {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 reg = <0>;
1191 drc1_in_be1: endpoint@1 {
1192 reg = <1>;
1193 remote-endpoint = <&be1_out_drc1>;
1194 };
1195 };
1197 drc1_out: port@1 {
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 reg = <1>;
1202 drc1_out_tcon0: endpoint@0 {
1203 reg = <0>;
1204 remote-endpoint = <&tcon0_in_drc1>;
1205 };
1207 drc1_out_tcon1: endpoint@1 {
1208 reg = <1>;
1209 remote-endpoint = <&tcon1_in_drc1>;
1210 };
1211 };
1212 };
1213 };
1215 be0: display-backend@1e60000 {
1216 compatible = "allwinner,sun6i-a31-display-backend";
1217 reg = <0x01e60000 0x10000>;
1218 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1220 <&ccu CLK_DRAM_BE0>;
1221 clock-names = "ahb", "mod",
1222 "ram";
1223 resets = <&ccu RST_AHB1_BE0>;
1225 assigned-clocks = <&ccu CLK_BE0>;
1226 assigned-clock-rates = <300000000>;
1228 ports {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1232 be0_in: port@0 {
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1235 reg = <0>;
1237 be0_in_fe0: endpoint@0 {
1238 reg = <0>;
1239 remote-endpoint = <&fe0_out_be0>;
1240 };
1242 be0_in_fe1: endpoint@1 {
1243 reg = <1>;
1244 remote-endpoint = <&fe1_out_be0>;
1245 };
1246 };
1248 be0_out: port@1 {
1249 reg = <1>;
1251 be0_out_drc0: endpoint {
1252 remote-endpoint = <&drc0_in_be0>;
1253 };
1254 };
1255 };
1256 };
1258 drc0: drc@1e70000 {
1259 compatible = "allwinner,sun6i-a31-drc";
1260 reg = <0x01e70000 0x10000>;
1261 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263 <&ccu CLK_DRAM_DRC0>;
1264 clock-names = "ahb", "mod",
1265 "ram";
1266 resets = <&ccu RST_AHB1_DRC0>;
1268 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1269 assigned-clock-rates = <300000000>;
1271 ports {
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1275 drc0_in: port@0 {
1276 reg = <0>;
1278 drc0_in_be0: endpoint {
1279 remote-endpoint = <&be0_out_drc0>;
1280 };
1281 };
1283 drc0_out: port@1 {
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1286 reg = <1>;
1288 drc0_out_tcon0: endpoint@0 {
1289 reg = <0>;
1290 remote-endpoint = <&tcon0_in_drc0>;
1291 };
1293 drc0_out_tcon1: endpoint@1 {
1294 reg = <1>;
1295 remote-endpoint = <&tcon1_in_drc0>;
1296 };
1297 };
1298 };
1299 };
1301 rtc: rtc@1f00000 {
1302 #clock-cells = <1>;
1303 compatible = "allwinner,sun6i-a31-rtc";
1304 reg = <0x01f00000 0x54>;
1305 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&osc32k>;
1308 clock-output-names = "osc32k";
1309 };
1311 nmi_intc: interrupt-controller@1f00c00 {
1312 compatible = "allwinner,sun6i-a31-r-intc";
1313 interrupt-controller;
1314 #interrupt-cells = <2>;
1315 reg = <0x01f00c00 0x400>;
1316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1317 };
1319 prcm@1f01400 {
1320 compatible = "allwinner,sun6i-a31-prcm";
1321 reg = <0x01f01400 0x200>;
1323 ar100: ar100_clk {
1324 compatible = "allwinner,sun6i-a31-ar100-clk";
1325 #clock-cells = <0>;
1326 clocks = <&rtc 0>, <&osc24M>,
1327 <&ccu CLK_PLL_PERIPH>,
1328 <&ccu CLK_PLL_PERIPH>;
1329 clock-output-names = "ar100";
1330 };
1332 ahb0: ahb0_clk {
1333 compatible = "fixed-factor-clock";
1334 #clock-cells = <0>;
1335 clock-div = <1>;
1336 clock-mult = <1>;
1337 clocks = <&ar100>;
1338 clock-output-names = "ahb0";
1339 };
1341 apb0: apb0_clk {
1342 compatible = "allwinner,sun6i-a31-apb0-clk";
1343 #clock-cells = <0>;
1344 clocks = <&ahb0>;
1345 clock-output-names = "apb0";
1346 };
1348 apb0_gates: apb0_gates_clk {
1349 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1350 #clock-cells = <1>;
1351 clocks = <&apb0>;
1352 clock-output-names = "apb0_pio", "apb0_ir",
1353 "apb0_timer", "apb0_p2wi",
1354 "apb0_uart", "apb0_1wire",
1355 "apb0_i2c";
1356 };
1358 ir_clk: ir_clk {
1359 #clock-cells = <0>;
1360 compatible = "allwinner,sun4i-a10-mod0-clk";
1361 clocks = <&rtc 0>, <&osc24M>;
1362 clock-output-names = "ir";
1363 };
1365 apb0_rst: apb0_rst {
1366 compatible = "allwinner,sun6i-a31-clock-reset";
1367 #reset-cells = <1>;
1368 };
1369 };
1371 cpucfg@1f01c00 {
1372 compatible = "allwinner,sun6i-a31-cpuconfig";
1373 reg = <0x01f01c00 0x300>;
1374 };
1376 ir: ir@1f02000 {
1377 compatible = "allwinner,sun6i-a31-ir";
1378 clocks = <&apb0_gates 1>, <&ir_clk>;
1379 clock-names = "apb", "ir";
1380 resets = <&apb0_rst 1>;
1381 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1382 reg = <0x01f02000 0x40>;
1383 status = "disabled";
1384 };
1386 r_pio: pinctrl@1f02c00 {
1387 compatible = "allwinner,sun6i-a31-r-pinctrl";
1388 reg = <0x01f02c00 0x400>;
1389 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1391 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1392 clock-names = "apb", "hosc", "losc";
1393 resets = <&apb0_rst 0>;
1394 gpio-controller;
1395 interrupt-controller;
1396 #interrupt-cells = <3>;
1397 #gpio-cells = <3>;
1399 s_ir_rx_pin: s-ir-rx-pin {
1400 pins = "PL4";
1401 function = "s_ir";
1402 };
1404 s_p2wi_pins: s-p2wi-pins {
1405 pins = "PL0", "PL1";
1406 function = "s_p2wi";
1407 };
1408 };
1410 p2wi: i2c@1f03400 {
1411 compatible = "allwinner,sun6i-a31-p2wi";
1412 reg = <0x01f03400 0x400>;
1413 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1414 clocks = <&apb0_gates 3>;
1415 clock-frequency = <100000>;
1416 resets = <&apb0_rst 3>;
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&s_p2wi_pins>;
1419 status = "disabled";
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1422 };
1423 };
1424 };