arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56         #address-cells = <1>;
  57         #size-cells = <1>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         clocks = <&ccu CLK_C0CPUX>;
  67                         operating-points-v2 = <&cpu0_opp_table>;
  68                         cci-control-port = <&cci_control0>;
  69                         enable-method = "allwinner,sun8i-a83t-smp";
  70                         reg = <0>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu@1 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         clocks = <&ccu CLK_C0CPUX>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                         cci-control-port = <&cci_control0>;
  80                         enable-method = "allwinner,sun8i-a83t-smp";
  81                         reg = <1>;
  82                         #cooling-cells = <2>;
  83                 };
  84
  85                 cpu@2 {
  86                         compatible = "arm,cortex-a7";
  87                         device_type = "cpu";
  88                         clocks = <&ccu CLK_C0CPUX>;
  89                         operating-points-v2 = <&cpu0_opp_table>;
  90                         cci-control-port = <&cci_control0>;
  91                         enable-method = "allwinner,sun8i-a83t-smp";
  92                         reg = <2>;
  93                         #cooling-cells = <2>;
  94                 };
  95
  96                 cpu@3 {
  97                         compatible = "arm,cortex-a7";
  98                         device_type = "cpu";
  99                         clocks = <&ccu CLK_C0CPUX>;
 100                         operating-points-v2 = <&cpu0_opp_table>;
 101                         cci-control-port = <&cci_control0>;
 102                         enable-method = "allwinner,sun8i-a83t-smp";
 103                         reg = <3>;
 104                         #cooling-cells = <2>;
 105                 };
 106
 107                 cpu100: cpu@100 {
 108                         compatible = "arm,cortex-a7";
 109                         device_type = "cpu";
 110                         clocks = <&ccu CLK_C1CPUX>;
 111                         operating-points-v2 = <&cpu1_opp_table>;
 112                         cci-control-port = <&cci_control1>;
 113                         enable-method = "allwinner,sun8i-a83t-smp";
 114                         reg = <0x100>;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu@101 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         clocks = <&ccu CLK_C1CPUX>;
 122                         operating-points-v2 = <&cpu1_opp_table>;
 123                         cci-control-port = <&cci_control1>;
 124                         enable-method = "allwinner,sun8i-a83t-smp";
 125                         reg = <0x101>;
 126                         #cooling-cells = <2>;
 127                 };
 128
 129                 cpu@102 {
 130                         compatible = "arm,cortex-a7";
 131                         device_type = "cpu";
 132                         clocks = <&ccu CLK_C1CPUX>;
 133                         operating-points-v2 = <&cpu1_opp_table>;
 134                         cci-control-port = <&cci_control1>;
 135                         enable-method = "allwinner,sun8i-a83t-smp";
 136                         reg = <0x102>;
 137                         #cooling-cells = <2>;
 138                 };
 139
 140                 cpu@103 {
 141                         compatible = "arm,cortex-a7";
 142                         device_type = "cpu";
 143                         clocks = <&ccu CLK_C1CPUX>;
 144                         operating-points-v2 = <&cpu1_opp_table>;
 145                         cci-control-port = <&cci_control1>;
 146                         enable-method = "allwinner,sun8i-a83t-smp";
 147                         reg = <0x103>;
 148                         #cooling-cells = <2>;
 149                 };
 150         };
 151
 152         timer {
 153                 compatible = "arm,armv7-timer";
 154                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 158         };
 159
 160         clocks {
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 ranges;
 164
 165                 /* TODO: PRCM block has a mux for this. */
 166                 osc24M: osc24M_clk {
 167                         #clock-cells = <0>;
 168                         compatible = "fixed-clock";
 169                         clock-frequency = <24000000>;
 170                         clock-accuracy = <50000>;
 171                         clock-output-names = "osc24M";
 172                 };
 173
 174                 /*
 175                  * This is called "internal OSC" in some places.
 176                  * It is an internal RC-based oscillator.
 177                  * TODO: Its controls are in the PRCM block.
 178                  */
 179                 osc16M: osc16M_clk {
 180                         #clock-cells = <0>;
 181                         compatible = "fixed-clock";
 182                         clock-frequency = <16000000>;
 183                         clock-output-names = "osc16M";
 184                 };
 185
 186                 osc16Md512: osc16Md512_clk {
 187                         #clock-cells = <0>;
 188                         compatible = "fixed-factor-clock";
 189                         clock-div = <512>;
 190                         clock-mult = <1>;
 191                         clocks = <&osc16M>;
 192                         clock-output-names = "osc16M-d512";
 193                 };
 194         };
 195
 196         de: display-engine {
 197                 compatible = "allwinner,sun8i-a83t-display-engine";
 198                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 199                 status = "disabled";
 200         };
 201
 202         cpu0_opp_table: opp_table0 {
 203                 compatible = "operating-points-v2";
 204                 opp-shared;
 205
 206                 opp-480000000 {
 207                         opp-hz = /bits/ 64 <480000000>;
 208                         opp-microvolt = <840000>;
 209                         clock-latency-ns = <244144>; /* 8 32k periods */
 210                 };
 211
 212                 opp-600000000 {
 213                         opp-hz = /bits/ 64 <600000000>;
 214                         opp-microvolt = <840000>;
 215                         clock-latency-ns = <244144>; /* 8 32k periods */
 216                 };
 217
 218                 opp-720000000 {
 219                         opp-hz = /bits/ 64 <720000000>;
 220                         opp-microvolt = <840000>;
 221                         clock-latency-ns = <244144>; /* 8 32k periods */
 222                 };
 223
 224                 opp-864000000 {
 225                         opp-hz = /bits/ 64 <864000000>;
 226                         opp-microvolt = <840000>;
 227                         clock-latency-ns = <244144>; /* 8 32k periods */
 228                 };
 229
 230                 opp-912000000 {
 231                         opp-hz = /bits/ 64 <912000000>;
 232                         opp-microvolt = <840000>;
 233                         clock-latency-ns = <244144>; /* 8 32k periods */
 234                 };
 235
 236                 opp-1008000000 {
 237                         opp-hz = /bits/ 64 <1008000000>;
 238                         opp-microvolt = <840000>;
 239                         clock-latency-ns = <244144>; /* 8 32k periods */
 240                 };
 241
 242                 opp-1128000000 {
 243                         opp-hz = /bits/ 64 <1128000000>;
 244                         opp-microvolt = <840000>;
 245                         clock-latency-ns = <244144>; /* 8 32k periods */
 246                 };
 247
 248                 opp-1200000000 {
 249                         opp-hz = /bits/ 64 <1200000000>;
 250                         opp-microvolt = <840000>;
 251                         clock-latency-ns = <244144>; /* 8 32k periods */
 252                 };
 253         };
 254
 255         cpu1_opp_table: opp_table1 {
 256                 compatible = "operating-points-v2";
 257                 opp-shared;
 258
 259                 opp-480000000 {
 260                         opp-hz = /bits/ 64 <480000000>;
 261                         opp-microvolt = <840000>;
 262                         clock-latency-ns = <244144>; /* 8 32k periods */
 263                 };
 264
 265                 opp-600000000 {
 266                         opp-hz = /bits/ 64 <600000000>;
 267                         opp-microvolt = <840000>;
 268                         clock-latency-ns = <244144>; /* 8 32k periods */
 269                 };
 270
 271                 opp-720000000 {
 272                         opp-hz = /bits/ 64 <720000000>;
 273                         opp-microvolt = <840000>;
 274                         clock-latency-ns = <244144>; /* 8 32k periods */
 275                 };
 276
 277                 opp-864000000 {
 278                         opp-hz = /bits/ 64 <864000000>;
 279                         opp-microvolt = <840000>;
 280                         clock-latency-ns = <244144>; /* 8 32k periods */
 281                 };
 282
 283                 opp-912000000 {
 284                         opp-hz = /bits/ 64 <912000000>;
 285                         opp-microvolt = <840000>;
 286                         clock-latency-ns = <244144>; /* 8 32k periods */
 287                 };
 288
 289                 opp-1008000000 {
 290                         opp-hz = /bits/ 64 <1008000000>;
 291                         opp-microvolt = <840000>;
 292                         clock-latency-ns = <244144>; /* 8 32k periods */
 293                 };
 294
 295                 opp-1128000000 {
 296                         opp-hz = /bits/ 64 <1128000000>;
 297                         opp-microvolt = <840000>;
 298                         clock-latency-ns = <244144>; /* 8 32k periods */
 299                 };
 300
 301                 opp-1200000000 {
 302                         opp-hz = /bits/ 64 <1200000000>;
 303                         opp-microvolt = <840000>;
 304                         clock-latency-ns = <244144>; /* 8 32k periods */
 305                 };
 306         };
 307
 308         soc {
 309                 compatible = "simple-bus";
 310                 #address-cells = <1>;
 311                 #size-cells = <1>;
 312                 ranges;
 313
 314                 display_clocks: clock@1000000 {
 315                         compatible = "allwinner,sun8i-a83t-de2-clk";
 316                         reg = <0x01000000 0x100000>;
 317                         clocks = <&ccu CLK_BUS_DE>,
 318                                  <&ccu CLK_PLL_DE>;
 319                         clock-names = "bus",
 320                                       "mod";
 321                         resets = <&ccu RST_BUS_DE>;
 322                         #clock-cells = <1>;
 323                         #reset-cells = <1>;
 324                 };
 325
 326                 mixer0: mixer@1100000 {
 327                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 328                         reg = <0x01100000 0x100000>;
 329                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 330                                  <&display_clocks CLK_MIXER0>;
 331                         clock-names = "bus",
 332                                       "mod";
 333                         resets = <&display_clocks RST_MIXER0>;
 334
 335                         ports {
 336                                 #address-cells = <1>;
 337                                 #size-cells = <0>;
 338
 339                                 mixer0_out: port@1 {
 340                                         #address-cells = <1>;
 341                                         #size-cells = <0>;
 342                                         reg = <1>;
 343
 344                                         mixer0_out_tcon0: endpoint@0 {
 345                                                 reg = <0>;
 346                                                 remote-endpoint = <&tcon0_in_mixer0>;
 347                                         };
 348
 349                                         mixer0_out_tcon1: endpoint@1 {
 350                                                 reg = <1>;
 351                                                 remote-endpoint = <&tcon1_in_mixer0>;
 352                                         };
 353                                 };
 354                         };
 355                 };
 356
 357                 mixer1: mixer@1200000 {
 358                         compatible = "allwinner,sun8i-a83t-de2-mixer-1";
 359                         reg = <0x01200000 0x100000>;
 360                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 361                                  <&display_clocks CLK_MIXER1>;
 362                         clock-names = "bus",
 363                                       "mod";
 364                         resets = <&display_clocks RST_WB>;
 365
 366                         ports {
 367                                 #address-cells = <1>;
 368                                 #size-cells = <0>;
 369
 370                                 mixer1_out: port@1 {
 371                                         #address-cells = <1>;
 372                                         #size-cells = <0>;
 373                                         reg = <1>;
 374
 375                                         mixer1_out_tcon0: endpoint@0 {
 376                                                 reg = <0>;
 377                                                 remote-endpoint = <&tcon0_in_mixer1>;
 378                                         };
 379
 380                                         mixer1_out_tcon1: endpoint@1 {
 381                                                 reg = <1>;
 382                                                 remote-endpoint = <&tcon1_in_mixer1>;
 383                                         };
 384                                 };
 385                         };
 386                 };
 387
 388                 cpucfg@1700000 {
 389                         compatible = "allwinner,sun8i-a83t-cpucfg";
 390                         reg = <0x01700000 0x400>;
 391                 };
 392
 393                 cci@1790000 {
 394                         compatible = "arm,cci-400";
 395                         #address-cells = <1>;
 396                         #size-cells = <1>;
 397                         reg = <0x01790000 0x10000>;
 398                         ranges = <0x0 0x01790000 0x10000>;
 399
 400                         cci_control0: slave-if@4000 {
 401                                 compatible = "arm,cci-400-ctrl-if";
 402                                 interface-type = "ace";
 403                                 reg = <0x4000 0x1000>;
 404                         };
 405
 406                         cci_control1: slave-if@5000 {
 407                                 compatible = "arm,cci-400-ctrl-if";
 408                                 interface-type = "ace";
 409                                 reg = <0x5000 0x1000>;
 410                         };
 411
 412                         pmu@9000 {
 413                                 compatible = "arm,cci-400-pmu,r1";
 414                                 reg = <0x9000 0x5000>;
 415                                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 416                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 418                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 419                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 420                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 423                         };
 424                 };
 425
 426                 syscon: syscon@1c00000 {
 427                         compatible = "allwinner,sun8i-a83t-system-controller",
 428                                 "syscon";
 429                         reg = <0x01c00000 0x1000>;
 430                 };
 431
 432                 dma: dma-controller@1c02000 {
 433                         compatible = "allwinner,sun8i-a83t-dma";
 434                         reg = <0x01c02000 0x1000>;
 435                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&ccu CLK_BUS_DMA>;
 437                         resets = <&ccu RST_BUS_DMA>;
 438                         #dma-cells = <1>;
 439                 };
 440
 441                 tcon0: lcd-controller@1c0c000 {
 442                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 443                         reg = <0x01c0c000 0x1000>;
 444                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 446                         clock-names = "ahb", "tcon-ch0";
 447                         clock-output-names = "tcon-pixel-clock";
 448                         #clock-cells = <0>;
 449                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 450                         reset-names = "lcd", "lvds";
 451
 452                         ports {
 453                                 #address-cells = <1>;
 454                                 #size-cells = <0>;
 455
 456                                 tcon0_in: port@0 {
 457                                         #address-cells = <1>;
 458                                         #size-cells = <0>;
 459                                         reg = <0>;
 460
 461                                         tcon0_in_mixer0: endpoint@0 {
 462                                                 reg = <0>;
 463                                                 remote-endpoint = <&mixer0_out_tcon0>;
 464                                         };
 465
 466                                         tcon0_in_mixer1: endpoint@1 {
 467                                                 reg = <1>;
 468                                                 remote-endpoint = <&mixer1_out_tcon0>;
 469                                         };
 470                                 };
 471
 472                                 tcon0_out: port@1 {
 473                                         reg = <1>;
 474                                 };
 475                         };
 476                 };
 477
 478                 tcon1: lcd-controller@1c0d000 {
 479                         compatible = "allwinner,sun8i-a83t-tcon-tv";
 480                         reg = <0x01c0d000 0x1000>;
 481                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 483                         clock-names = "ahb", "tcon-ch1";
 484                         resets = <&ccu RST_BUS_TCON1>;
 485                         reset-names = "lcd";
 486
 487                         ports {
 488                                 #address-cells = <1>;
 489                                 #size-cells = <0>;
 490
 491                                 tcon1_in: port@0 {
 492                                         #address-cells = <1>;
 493                                         #size-cells = <0>;
 494                                         reg = <0>;
 495
 496                                         tcon1_in_mixer0: endpoint@0 {
 497                                                 reg = <0>;
 498                                                 remote-endpoint = <&mixer0_out_tcon1>;
 499                                         };
 500
 501                                         tcon1_in_mixer1: endpoint@1 {
 502                                                 reg = <1>;
 503                                                 remote-endpoint = <&mixer1_out_tcon1>;
 504                                         };
 505                                 };
 506
 507                                 tcon1_out: port@1 {
 508                                         #address-cells = <1>;
 509                                         #size-cells = <0>;
 510                                         reg = <1>;
 511
 512                                         tcon1_out_hdmi: endpoint@1 {
 513                                                 reg = <1>;
 514                                                 remote-endpoint = <&hdmi_in_tcon1>;
 515                                         };
 516                                 };
 517                         };
 518                 };
 519
 520                 mmc0: mmc@1c0f000 {
 521                         compatible = "allwinner,sun8i-a83t-mmc",
 522                                      "allwinner,sun7i-a20-mmc";
 523                         reg = <0x01c0f000 0x1000>;
 524                         clocks = <&ccu CLK_BUS_MMC0>,
 525                                  <&ccu CLK_MMC0>,
 526                                  <&ccu CLK_MMC0_OUTPUT>,
 527                                  <&ccu CLK_MMC0_SAMPLE>;
 528                         clock-names = "ahb",
 529                                       "mmc",
 530                                       "output",
 531                                       "sample";
 532                         resets = <&ccu RST_BUS_MMC0>;
 533                         reset-names = "ahb";
 534                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 535                         status = "disabled";
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                 };
 539
 540                 mmc1: mmc@1c10000 {
 541                         compatible = "allwinner,sun8i-a83t-mmc",
 542                                      "allwinner,sun7i-a20-mmc";
 543                         reg = <0x01c10000 0x1000>;
 544                         clocks = <&ccu CLK_BUS_MMC1>,
 545                                  <&ccu CLK_MMC1>,
 546                                  <&ccu CLK_MMC1_OUTPUT>,
 547                                  <&ccu CLK_MMC1_SAMPLE>;
 548                         clock-names = "ahb",
 549                                       "mmc",
 550                                       "output",
 551                                       "sample";
 552                         resets = <&ccu RST_BUS_MMC1>;
 553                         reset-names = "ahb";
 554                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 555                         pinctrl-names = "default";
 556                         pinctrl-0 = <&mmc1_pins>;
 557                         status = "disabled";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                 };
 561
 562                 mmc2: mmc@1c11000 {
 563                         compatible = "allwinner,sun8i-a83t-emmc";
 564                         reg = <0x01c11000 0x1000>;
 565                         clocks = <&ccu CLK_BUS_MMC2>,
 566                                  <&ccu CLK_MMC2>,
 567                                  <&ccu CLK_MMC2_OUTPUT>,
 568                                  <&ccu CLK_MMC2_SAMPLE>;
 569                         clock-names = "ahb",
 570                                       "mmc",
 571                                       "output",
 572                                       "sample";
 573                         resets = <&ccu RST_BUS_MMC2>;
 574                         reset-names = "ahb";
 575                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 576                         status = "disabled";
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                 };
 580
 581                 sid: eeprom@1c14000 {
 582                         compatible = "allwinner,sun8i-a83t-sid";
 583                         reg = <0x1c14000 0x400>;
 584                 };
 585
 586                 crypto: crypto@1c15000 {
 587                         compatible = "allwinner,sun8i-a83t-crypto";
 588                         reg = <0x01c15000 0x1000>;
 589                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 590                         resets = <&ccu RST_BUS_SS>;
 591                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 592                         clock-names = "bus", "mod";
 593                 };
 594
 595                 usb_otg: usb@1c19000 {
 596                         compatible = "allwinner,sun8i-a83t-musb",
 597                                      "allwinner,sun8i-a33-musb";
 598                         reg = <0x01c19000 0x0400>;
 599                         clocks = <&ccu CLK_BUS_OTG>;
 600                         resets = <&ccu RST_BUS_OTG>;
 601                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 602                         interrupt-names = "mc";
 603                         phys = <&usbphy 0>;
 604                         phy-names = "usb";
 605                         extcon = <&usbphy 0>;
 606                         dr_mode = "otg";
 607                         status = "disabled";
 608                 };
 609
 610                 usbphy: phy@1c19400 {
 611                         compatible = "allwinner,sun8i-a83t-usb-phy";
 612                         reg = <0x01c19400 0x10>,
 613                               <0x01c1a800 0x14>,
 614                               <0x01c1b800 0x14>;
 615                         reg-names = "phy_ctrl",
 616                                     "pmu1",
 617                                     "pmu2";
 618                         clocks = <&ccu CLK_USB_PHY0>,
 619                                  <&ccu CLK_USB_PHY1>,
 620                                  <&ccu CLK_USB_HSIC>,
 621                                  <&ccu CLK_USB_HSIC_12M>;
 622                         clock-names = "usb0_phy",
 623                                       "usb1_phy",
 624                                       "usb2_phy",
 625                                       "usb2_hsic_12M";
 626                         resets = <&ccu RST_USB_PHY0>,
 627                                  <&ccu RST_USB_PHY1>,
 628                                  <&ccu RST_USB_HSIC>;
 629                         reset-names = "usb0_reset",
 630                                       "usb1_reset",
 631                                       "usb2_reset";
 632                         status = "disabled";
 633                         #phy-cells = <1>;
 634                 };
 635
 636                 ehci0: usb@1c1a000 {
 637                         compatible = "allwinner,sun8i-a83t-ehci",
 638                                      "generic-ehci";
 639                         reg = <0x01c1a000 0x100>;
 640                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 641                         clocks = <&ccu CLK_BUS_EHCI0>;
 642                         resets = <&ccu RST_BUS_EHCI0>;
 643                         phys = <&usbphy 1>;
 644                         phy-names = "usb";
 645                         status = "disabled";
 646                 };
 647
 648                 ohci0: usb@1c1a400 {
 649                         compatible = "allwinner,sun8i-a83t-ohci",
 650                                      "generic-ohci";
 651                         reg = <0x01c1a400 0x100>;
 652                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 654                         resets = <&ccu RST_BUS_OHCI0>;
 655                         phys = <&usbphy 1>;
 656                         phy-names = "usb";
 657                         status = "disabled";
 658                 };
 659
 660                 ehci1: usb@1c1b000 {
 661                         compatible = "allwinner,sun8i-a83t-ehci",
 662                                      "generic-ehci";
 663                         reg = <0x01c1b000 0x100>;
 664                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&ccu CLK_BUS_EHCI1>;
 666                         resets = <&ccu RST_BUS_EHCI1>;
 667                         phys = <&usbphy 2>;
 668                         phy-names = "usb";
 669                         status = "disabled";
 670                 };
 671
 672                 ccu: clock@1c20000 {
 673                         compatible = "allwinner,sun8i-a83t-ccu";
 674                         reg = <0x01c20000 0x400>;
 675                         clocks = <&osc24M>, <&osc16Md512>;
 676                         clock-names = "hosc", "losc";
 677                         #clock-cells = <1>;
 678                         #reset-cells = <1>;
 679                 };
 680
 681                 pio: pinctrl@1c20800 {
 682                         compatible = "allwinner,sun8i-a83t-pinctrl";
 683                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 686                         reg = <0x01c20800 0x400>;
 687                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 688                         clock-names = "apb", "hosc", "losc";
 689                         gpio-controller;
 690                         interrupt-controller;
 691                         #interrupt-cells = <3>;
 692                         #gpio-cells = <3>;
 693
 694                         /omit-if-no-ref/
 695                         csi_8bit_parallel_pins: csi-8bit-parallel-pins {
 696                                 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
 697                                        "PE8", "PE9", "PE10", "PE11",
 698                                        "PE12", "PE13";
 699                                 function = "csi";
 700                         };
 701
 702                         /omit-if-no-ref/
 703                         csi_mclk_pin: csi-mclk-pin {
 704                                 pins = "PE1";
 705                                 function = "csi";
 706                         };
 707
 708                         emac_rgmii_pins: emac-rgmii-pins {
 709                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 710                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 711                                        "PD19", "PD21", "PD22", "PD23";
 712                                 function = "gmac";
 713                                 /*
 714                                  * data lines in RGMII mode use DDR mode
 715                                  * and need a higher signal drive strength
 716                                  */
 717                                 drive-strength = <40>;
 718                         };
 719
 720                         hdmi_pins: hdmi-pins {
 721                                 pins = "PH6", "PH7", "PH8";
 722                                 function = "hdmi";
 723                         };
 724
 725                         i2c0_pins: i2c0-pins {
 726                                 pins = "PH0", "PH1";
 727                                 function = "i2c0";
 728                         };
 729
 730                         i2c1_pins: i2c1-pins {
 731                                 pins = "PH2", "PH3";
 732                                 function = "i2c1";
 733                         };
 734
 735                         /omit-if-no-ref/
 736                         i2c2_pe_pins: i2c2-pe-pins {
 737                                 pins = "PE14", "PE15";
 738                                 function = "i2c2";
 739                         };
 740
 741                         i2c2_ph_pins: i2c2-ph-pins {
 742                                 pins = "PH4", "PH5";
 743                                 function = "i2c2";
 744                         };
 745
 746                         i2s1_pins: i2s1-pins {
 747                                 /* I2S1 does not have external MCLK pin */
 748                                 pins = "PG10", "PG11", "PG12", "PG13";
 749                                 function = "i2s1";
 750                         };
 751
 752                         lcd_lvds_pins: lcd-lvds-pins {
 753                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 754                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 755                                 function = "lvds0";
 756                         };
 757
 758                         mmc0_pins: mmc0-pins {
 759                                 pins = "PF0", "PF1", "PF2",
 760                                        "PF3", "PF4", "PF5";
 761                                 function = "mmc0";
 762                                 drive-strength = <30>;
 763                                 bias-pull-up;
 764                         };
 765
 766                         mmc1_pins: mmc1-pins {
 767                                 pins = "PG0", "PG1", "PG2",
 768                                        "PG3", "PG4", "PG5";
 769                                 function = "mmc1";
 770                                 drive-strength = <30>;
 771                                 bias-pull-up;
 772                         };
 773
 774                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 775                                 pins = "PC5", "PC6", "PC8", "PC9",
 776                                        "PC10", "PC11", "PC12", "PC13",
 777                                        "PC14", "PC15", "PC16";
 778                                 function = "mmc2";
 779                                 drive-strength = <30>;
 780                                 bias-pull-up;
 781                         };
 782
 783                         pwm_pin: pwm-pin {
 784                                 pins = "PD28";
 785                                 function = "pwm";
 786                         };
 787
 788                         spdif_tx_pin: spdif-tx-pin {
 789                                 pins = "PE18";
 790                                 function = "spdif";
 791                         };
 792
 793                         uart0_pb_pins: uart0-pb-pins {
 794                                 pins = "PB9", "PB10";
 795                                 function = "uart0";
 796                         };
 797
 798                         uart0_pf_pins: uart0-pf-pins {
 799                                 pins = "PF2", "PF4";
 800                                 function = "uart0";
 801                         };
 802
 803                         uart1_pins: uart1-pins {
 804                                 pins = "PG6", "PG7";
 805                                 function = "uart1";
 806                         };
 807
 808                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 809                                 pins = "PG8", "PG9";
 810                                 function = "uart1";
 811                         };
 812
 813                         /omit-if-no-ref/
 814                         uart2_pb_pins: uart2-pb-pins {
 815                                 pins = "PB0", "PB1";
 816                                 function = "uart2";
 817                         };
 818                 };
 819
 820                 timer@1c20c00 {
 821                         compatible = "allwinner,sun8i-a23-timer";
 822                         reg = <0x01c20c00 0xa0>;
 823                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 824                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 825                         clocks = <&osc24M>;
 826                 };
 827
 828                 watchdog@1c20ca0 {
 829                         compatible = "allwinner,sun6i-a31-wdt";
 830                         reg = <0x01c20ca0 0x20>;
 831                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&osc24M>;
 833                 };
 834
 835                 spdif: spdif@1c21000 {
 836                         #sound-dai-cells = <0>;
 837                         compatible = "allwinner,sun8i-a83t-spdif",
 838                                      "allwinner,sun8i-h3-spdif";
 839                         reg = <0x01c21000 0x400>;
 840                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 841                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 842                         resets = <&ccu RST_BUS_SPDIF>;
 843                         clock-names = "apb", "spdif";
 844                         dmas = <&dma 2>;
 845                         dma-names = "tx";
 846                         pinctrl-names = "default";
 847                         pinctrl-0 = <&spdif_tx_pin>;
 848                         status = "disabled";
 849                 };
 850
 851                 i2s0: i2s@1c22000 {
 852                         #sound-dai-cells = <0>;
 853                         compatible = "allwinner,sun8i-a83t-i2s";
 854                         reg = <0x01c22000 0x400>;
 855                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 856                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 857                         clock-names = "apb", "mod";
 858                         dmas = <&dma 3>, <&dma 3>;
 859                         resets = <&ccu RST_BUS_I2S0>;
 860                         dma-names = "rx", "tx";
 861                         status = "disabled";
 862                 };
 863
 864                 i2s1: i2s@1c22400 {
 865                         #sound-dai-cells = <0>;
 866                         compatible = "allwinner,sun8i-a83t-i2s";
 867                         reg = <0x01c22400 0x400>;
 868                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 870                         clock-names = "apb", "mod";
 871                         dmas = <&dma 4>, <&dma 4>;
 872                         resets = <&ccu RST_BUS_I2S1>;
 873                         dma-names = "rx", "tx";
 874                         pinctrl-names = "default";
 875                         pinctrl-0 = <&i2s1_pins>;
 876                         status = "disabled";
 877                 };
 878
 879                 i2s2: i2s@1c22800 {
 880                         #sound-dai-cells = <0>;
 881                         compatible = "allwinner,sun8i-a83t-i2s";
 882                         reg = <0x01c22800 0x400>;
 883                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 884                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 885                         clock-names = "apb", "mod";
 886                         dmas = <&dma 27>;
 887                         resets = <&ccu RST_BUS_I2S2>;
 888                         dma-names = "tx";
 889                         status = "disabled";
 890                 };
 891
 892                 pwm: pwm@1c21400 {
 893                         compatible = "allwinner,sun8i-a83t-pwm",
 894                                      "allwinner,sun8i-h3-pwm";
 895                         reg = <0x01c21400 0x400>;
 896                         clocks = <&osc24M>;
 897                         #pwm-cells = <3>;
 898                         status = "disabled";
 899                 };
 900
 901                 uart0: serial@1c28000 {
 902                         compatible = "snps,dw-apb-uart";
 903                         reg = <0x01c28000 0x400>;
 904                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 905                         reg-shift = <2>;
 906                         reg-io-width = <4>;
 907                         clocks = <&ccu CLK_BUS_UART0>;
 908                         resets = <&ccu RST_BUS_UART0>;
 909                         status = "disabled";
 910                 };
 911
 912                 uart1: serial@1c28400 {
 913                         compatible = "snps,dw-apb-uart";
 914                         reg = <0x01c28400 0x400>;
 915                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 916                         reg-shift = <2>;
 917                         reg-io-width = <4>;
 918                         clocks = <&ccu CLK_BUS_UART1>;
 919                         resets = <&ccu RST_BUS_UART1>;
 920                         status = "disabled";
 921                 };
 922
 923                 uart2: serial@1c28800 {
 924                         compatible = "snps,dw-apb-uart";
 925                         reg = <0x01c28800 0x400>;
 926                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 927                         reg-shift = <2>;
 928                         reg-io-width = <4>;
 929                         clocks = <&ccu CLK_BUS_UART2>;
 930                         resets = <&ccu RST_BUS_UART2>;
 931                         status = "disabled";
 932                 };
 933
 934                 uart3: serial@1c28c00 {
 935                         compatible = "snps,dw-apb-uart";
 936                         reg = <0x01c28c00 0x400>;
 937                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 938                         reg-shift = <2>;
 939                         reg-io-width = <4>;
 940                         clocks = <&ccu CLK_BUS_UART3>;
 941                         resets = <&ccu RST_BUS_UART3>;
 942                         status = "disabled";
 943                 };
 944
 945                 uart4: serial@1c29000 {
 946                         compatible = "snps,dw-apb-uart";
 947                         reg = <0x01c29000 0x400>;
 948                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 949                         reg-shift = <2>;
 950                         reg-io-width = <4>;
 951                         clocks = <&ccu CLK_BUS_UART4>;
 952                         resets = <&ccu RST_BUS_UART4>;
 953                         status = "disabled";
 954                 };
 955
 956                 i2c0: i2c@1c2ac00 {
 957                         compatible = "allwinner,sun8i-a83t-i2c",
 958                                      "allwinner,sun6i-a31-i2c";
 959                         reg = <0x01c2ac00 0x400>;
 960                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&ccu CLK_BUS_I2C0>;
 962                         resets = <&ccu RST_BUS_I2C0>;
 963                         pinctrl-names = "default";
 964                         pinctrl-0 = <&i2c0_pins>;
 965                         status = "disabled";
 966                         #address-cells = <1>;
 967                         #size-cells = <0>;
 968                 };
 969
 970                 i2c1: i2c@1c2b000 {
 971                         compatible = "allwinner,sun8i-a83t-i2c",
 972                                      "allwinner,sun6i-a31-i2c";
 973                         reg = <0x01c2b000 0x400>;
 974                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 975                         clocks = <&ccu CLK_BUS_I2C1>;
 976                         resets = <&ccu RST_BUS_I2C1>;
 977                         pinctrl-names = "default";
 978                         pinctrl-0 = <&i2c1_pins>;
 979                         status = "disabled";
 980                         #address-cells = <1>;
 981                         #size-cells = <0>;
 982                 };
 983
 984                 i2c2: i2c@1c2b400 {
 985                         compatible = "allwinner,sun8i-a83t-i2c",
 986                                      "allwinner,sun6i-a31-i2c";
 987                         reg = <0x01c2b400 0x400>;
 988                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 989                         clocks = <&ccu CLK_BUS_I2C2>;
 990                         resets = <&ccu RST_BUS_I2C2>;
 991                         status = "disabled";
 992                         #address-cells = <1>;
 993                         #size-cells = <0>;
 994                 };
 995
 996                 emac: ethernet@1c30000 {
 997                         compatible = "allwinner,sun8i-a83t-emac";
 998                         syscon = <&syscon>;
 999                         reg = <0x01c30000 0x104>;
1000                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1001                         interrupt-names = "macirq";
1002                         resets = <&ccu 13>;
1003                         reset-names = "stmmaceth";
1004                         clocks = <&ccu 27>;
1005                         clock-names = "stmmaceth";
1006                         status = "disabled";
1007
1008                         mdio: mdio {
1009                                 compatible = "snps,dwmac-mdio";
1010                                 #address-cells = <1>;
1011                                 #size-cells = <0>;
1012                         };
1013                 };
1014
1015                 gic: interrupt-controller@1c81000 {
1016                         compatible = "arm,gic-400";
1017                         reg = <0x01c81000 0x1000>,
1018                               <0x01c82000 0x2000>,
1019                               <0x01c84000 0x2000>,
1020                               <0x01c86000 0x2000>;
1021                         interrupt-controller;
1022                         #interrupt-cells = <3>;
1023                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1024                 };
1025
1026                 csi: camera@1cb0000 {
1027                         compatible = "allwinner,sun8i-a83t-csi";
1028                         reg = <0x01cb0000 0x1000>;
1029                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1030                         clocks = <&ccu CLK_BUS_CSI>,
1031                                  <&ccu CLK_CSI_SCLK>,
1032                                  <&ccu CLK_DRAM_CSI>;
1033                         clock-names = "bus", "mod", "ram";
1034                         resets = <&ccu RST_BUS_CSI>;
1035                         status = "disabled";
1036
1037                         csi_in: port {
1038                         };
1039                 };
1040
1041                 hdmi: hdmi@1ee0000 {
1042                         compatible = "allwinner,sun8i-a83t-dw-hdmi";
1043                         reg = <0x01ee0000 0x10000>;
1044                         reg-io-width = <1>;
1045                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1046                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1047                                  <&ccu CLK_HDMI>;
1048                         clock-names = "iahb", "isfr", "tmds";
1049                         resets = <&ccu RST_BUS_HDMI1>;
1050                         reset-names = "ctrl";
1051                         phys = <&hdmi_phy>;
1052                         phy-names = "phy";
1053                         pinctrl-names = "default";
1054                         pinctrl-0 = <&hdmi_pins>;
1055                         status = "disabled";
1056
1057                         ports {
1058                                 #address-cells = <1>;
1059                                 #size-cells = <0>;
1060
1061                                 hdmi_in: port@0 {
1062                                         reg = <0>;
1063
1064                                         hdmi_in_tcon1: endpoint {
1065                                                 remote-endpoint = <&tcon1_out_hdmi>;
1066                                         };
1067                                 };
1068
1069                                 hdmi_out: port@1 {
1070                                         reg = <1>;
1071                                 };
1072                         };
1073                 };
1074
1075                 hdmi_phy: hdmi-phy@1ef0000 {
1076                         compatible = "allwinner,sun8i-a83t-hdmi-phy";
1077                         reg = <0x01ef0000 0x10000>;
1078                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1079                         clock-names = "bus", "mod";
1080                         resets = <&ccu RST_BUS_HDMI0>;
1081                         reset-names = "phy";
1082                         #phy-cells = <0>;
1083                 };
1084
1085                 r_intc: interrupt-controller@1f00c00 {
1086                         compatible = "allwinner,sun8i-a83t-r-intc",
1087                                      "allwinner,sun6i-a31-r-intc";
1088                         interrupt-controller;
1089                         #interrupt-cells = <2>;
1090                         reg = <0x01f00c00 0x400>;
1091                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1092                 };
1093
1094                 r_ccu: clock@1f01400 {
1095                         compatible = "allwinner,sun8i-a83t-r-ccu";
1096                         reg = <0x01f01400 0x400>;
1097                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1098                                  <&ccu 6>;
1099                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1100                         #clock-cells = <1>;
1101                         #reset-cells = <1>;
1102                 };
1103
1104                 r_cpucfg@1f01c00 {
1105                         compatible = "allwinner,sun8i-a83t-r-cpucfg";
1106                         reg = <0x1f01c00 0x400>;
1107                 };
1108
1109                 r_cir: ir@1f02000 {
1110                         compatible = "allwinner,sun8i-a83t-ir",
1111                                 "allwinner,sun6i-a31-ir";
1112                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1113                         clock-names = "apb", "ir";
1114                         resets = <&r_ccu RST_APB0_IR>;
1115                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1116                         reg = <0x01f02000 0x400>;
1117                         pinctrl-names = "default";
1118                         pinctrl-0 = <&r_cir_pin>;
1119                         status = "disabled";
1120                 };
1121
1122                 r_lradc: lradc@1f03c00 {
1123                         compatible = "allwinner,sun8i-a83t-r-lradc";
1124                         reg = <0x01f03c00 0x100>;
1125                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1126                         status = "disabled";
1127                 };
1128
1129                 r_pio: pinctrl@1f02c00 {
1130                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
1131                         reg = <0x01f02c00 0x400>;
1132                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1133                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1134                                  <&osc16Md512>;
1135                         clock-names = "apb", "hosc", "losc";
1136                         gpio-controller;
1137                         #gpio-cells = <3>;
1138                         interrupt-controller;
1139                         #interrupt-cells = <3>;
1140
1141                         r_cir_pin: r-cir-pin {
1142                                 pins = "PL12";
1143                                 function = "s_cir_rx";
1144                         };
1145
1146                         r_rsb_pins: r-rsb-pins {
1147                                 pins = "PL0", "PL1";
1148                                 function = "s_rsb";
1149                                 drive-strength = <20>;
1150                                 bias-pull-up;
1151                         };
1152                 };
1153
1154                 r_rsb: rsb@1f03400 {
1155                         compatible = "allwinner,sun8i-a83t-rsb",
1156                                      "allwinner,sun8i-a23-rsb";
1157                         reg = <0x01f03400 0x400>;
1158                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1159                         clocks = <&r_ccu CLK_APB0_RSB>;
1160                         clock-frequency = <3000000>;
1161                         resets = <&r_ccu RST_APB0_RSB>;
1162                         pinctrl-names = "default";
1163                         pinctrl-0 = <&r_rsb_pins>;
1164                         status = "disabled";
1165                         #address-cells = <1>;
1166                         #size-cells = <0>;
1167                 };
1168         };
1169 };