arch/arm/boot/dts/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun8i-de2.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  48 #include <dt-bindings/reset/sun8i-de2.h>
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         clocks {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 osc24M: osc24M {
  61                         #clock-cells = <0>;
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <24000000>;
  64                         clock-accuracy = <50000>;
  65                         clock-output-names = "osc24M";
  66                 };
  67
  68                 osc32k: osc32k {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                         clock-accuracy = <20000>;
  73                         clock-output-names = "ext-osc32k";
  74                 };
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 cpu@0 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0>;
  85                 };
  86
  87                 cpu@1 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <1>;
  91                 };
  92
  93                 cpu@2 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                 };
  98
  99                 cpu@3 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <3>;
 103                 };
 104         };
 105
 106         de: display-engine {
 107                 compatible = "allwinner,sun8i-r40-display-engine";
 108                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 109                 status = "disabled";
 110         };
 111
 112         soc {
 113                 compatible = "simple-bus";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 ranges;
 117
 118                 display_clocks: clock@1000000 {
 119                         compatible = "allwinner,sun8i-r40-de2-clk",
 120                                      "allwinner,sun8i-h3-de2-clk";
 121                         reg = <0x01000000 0x100000>;
 122                         clocks = <&ccu CLK_BUS_DE>,
 123                                  <&ccu CLK_DE>;
 124                         clock-names = "bus",
 125                                       "mod";
 126                         resets = <&ccu RST_BUS_DE>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                 };
 130
 131                 mixer0: mixer@1100000 {
 132                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
 133                         reg = <0x01100000 0x100000>;
 134                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 135                                  <&display_clocks CLK_MIXER0>;
 136                         clock-names = "bus",
 137                                       "mod";
 138                         resets = <&display_clocks RST_MIXER0>;
 139
 140                         ports {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 mixer0_out: port@1 {
 145                                         reg = <1>;
 146                                         mixer0_out_tcon_top: endpoint {
 147                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 148                                         };
 149                                 };
 150                         };
 151                 };
 152
 153                 mixer1: mixer@1200000 {
 154                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
 155                         reg = <0x01200000 0x100000>;
 156                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 157                                  <&display_clocks CLK_MIXER1>;
 158                         clock-names = "bus",
 159                                       "mod";
 160                         resets = <&display_clocks RST_WB>;
 161
 162                         ports {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165
 166                                 mixer1_out: port@1 {
 167                                         reg = <1>;
 168                                         mixer1_out_tcon_top: endpoint {
 169                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
 170                                         };
 171                                 };
 172                         };
 173                 };
 174
 175                 nmi_intc: interrupt-controller@1c00030 {
 176                         compatible = "allwinner,sun7i-a20-sc-nmi";
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                         reg = <0x01c00030 0x0c>;
 180                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 181                 };
 182
 183                 mmc0: mmc@1c0f000 {
 184                         compatible = "allwinner,sun8i-r40-mmc",
 185                                      "allwinner,sun50i-a64-mmc";
 186                         reg = <0x01c0f000 0x1000>;
 187                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 188                         clock-names = "ahb", "mmc";
 189                         resets = <&ccu RST_BUS_MMC0>;
 190                         reset-names = "ahb";
 191                         pinctrl-0 = <&mmc0_pins>;
 192                         pinctrl-names = "default";
 193                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 194                         status = "disabled";
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                 };
 198
 199                 mmc1: mmc@1c10000 {
 200                         compatible = "allwinner,sun8i-r40-mmc",
 201                                      "allwinner,sun50i-a64-mmc";
 202                         reg = <0x01c10000 0x1000>;
 203                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 204                         clock-names = "ahb", "mmc";
 205                         resets = <&ccu RST_BUS_MMC1>;
 206                         reset-names = "ahb";
 207                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 208                         status = "disabled";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                 };
 212
 213                 mmc2: mmc@1c11000 {
 214                         compatible = "allwinner,sun8i-r40-emmc",
 215                                      "allwinner,sun50i-a64-emmc";
 216                         reg = <0x01c11000 0x1000>;
 217                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 218                         clock-names = "ahb", "mmc";
 219                         resets = <&ccu RST_BUS_MMC2>;
 220                         reset-names = "ahb";
 221                         pinctrl-0 = <&mmc2_pins>;
 222                         pinctrl-names = "default";
 223                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 224                         status = "disabled";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                 };
 228
 229                 mmc3: mmc@1c12000 {
 230                         compatible = "allwinner,sun8i-r40-mmc",
 231                                      "allwinner,sun50i-a64-mmc";
 232                         reg = <0x01c12000 0x1000>;
 233                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
 234                         clock-names = "ahb", "mmc";
 235                         resets = <&ccu RST_BUS_MMC3>;
 236                         reset-names = "ahb";
 237                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 238                         status = "disabled";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                 };
 242
 243                 usbphy: phy@1c13400 {
 244                         compatible = "allwinner,sun8i-r40-usb-phy";
 245                         reg = <0x01c13400 0x14>,
 246                               <0x01c14800 0x4>,
 247                               <0x01c19800 0x4>,
 248                               <0x01c1c800 0x4>;
 249                         reg-names = "phy_ctrl",
 250                                     "pmu0",
 251                                     "pmu1",
 252                                     "pmu2";
 253                         clocks = <&ccu CLK_USB_PHY0>,
 254                                  <&ccu CLK_USB_PHY1>,
 255                                  <&ccu CLK_USB_PHY2>;
 256                         clock-names = "usb0_phy",
 257                                       "usb1_phy",
 258                                       "usb2_phy";
 259                         resets = <&ccu RST_USB_PHY0>,
 260                                  <&ccu RST_USB_PHY1>,
 261                                  <&ccu RST_USB_PHY2>;
 262                         reset-names = "usb0_reset",
 263                                       "usb1_reset",
 264                                       "usb2_reset";
 265                         status = "disabled";
 266                         #phy-cells = <1>;
 267                 };
 268
 269                 crypto: crypto@1c15000 {
 270                         compatible = "allwinner,sun8i-r40-crypto";
 271                         reg = <0x01c15000 0x1000>;
 272                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 273                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 274                         clock-names = "bus", "mod";
 275                         resets = <&ccu RST_BUS_CE>;
 276                 };
 277
 278                 ehci1: usb@1c19000 {
 279                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 280                         reg = <0x01c19000 0x100>;
 281                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 282                         clocks = <&ccu CLK_BUS_EHCI1>;
 283                         resets = <&ccu RST_BUS_EHCI1>;
 284                         phys = <&usbphy 1>;
 285                         phy-names = "usb";
 286                         status = "disabled";
 287                 };
 288
 289                 ohci1: usb@1c19400 {
 290                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 291                         reg = <0x01c19400 0x100>;
 292                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&ccu CLK_BUS_OHCI1>,
 294                                  <&ccu CLK_USB_OHCI1>;
 295                         resets = <&ccu RST_BUS_OHCI1>;
 296                         phys = <&usbphy 1>;
 297                         phy-names = "usb";
 298                         status = "disabled";
 299                 };
 300
 301                 ehci2: usb@1c1c000 {
 302                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 303                         reg = <0x01c1c000 0x100>;
 304                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&ccu CLK_BUS_EHCI2>;
 306                         resets = <&ccu RST_BUS_EHCI2>;
 307                         phys = <&usbphy 2>;
 308                         phy-names = "usb";
 309                         status = "disabled";
 310                 };
 311
 312                 ohci2: usb@1c1c400 {
 313                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 314                         reg = <0x01c1c400 0x100>;
 315                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&ccu CLK_BUS_OHCI2>,
 317                                  <&ccu CLK_USB_OHCI2>;
 318                         resets = <&ccu RST_BUS_OHCI2>;
 319                         phys = <&usbphy 2>;
 320                         phy-names = "usb";
 321                         status = "disabled";
 322                 };
 323
 324                 ccu: clock@1c20000 {
 325                         compatible = "allwinner,sun8i-r40-ccu";
 326                         reg = <0x01c20000 0x400>;
 327                         clocks = <&osc24M>, <&rtc 0>;
 328                         clock-names = "hosc", "losc";
 329                         #clock-cells = <1>;
 330                         #reset-cells = <1>;
 331                 };
 332
 333                 rtc: rtc@1c20400 {
 334                         compatible = "allwinner,sun8i-r40-rtc";
 335                         reg = <0x01c20400 0x400>;
 336                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 337                         clock-output-names = "osc32k", "osc32k-out";
 338                         clocks = <&osc32k>;
 339                         #clock-cells = <1>;
 340                 };
 341
 342                 pio: pinctrl@1c20800 {
 343                         compatible = "allwinner,sun8i-r40-pinctrl";
 344                         reg = <0x01c20800 0x400>;
 345                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 347                         clock-names = "apb", "hosc", "losc";
 348                         gpio-controller;
 349                         interrupt-controller;
 350                         #interrupt-cells = <3>;
 351                         #gpio-cells = <3>;
 352
 353                         clk_out_a_pin: clk-out-a-pin {
 354                                 pins = "PI12";
 355                                 function = "clk_out_a";
 356                         };
 357
 358                         gmac_rgmii_pins: gmac-rgmii-pins {
 359                                 pins = "PA0", "PA1", "PA2", "PA3",
 360                                        "PA4", "PA5", "PA6", "PA7",
 361                                        "PA8", "PA10", "PA11", "PA12",
 362                                        "PA13", "PA15", "PA16";
 363                                 function = "gmac";
 364                                 /*
 365                                  * data lines in RGMII mode use DDR mode
 366                                  * and need a higher signal drive strength
 367                                  */
 368                                 drive-strength = <40>;
 369                         };
 370
 371                         i2c0_pins: i2c0-pins {
 372                                 pins = "PB0", "PB1";
 373                                 function = "i2c0";
 374                         };
 375
 376                         mmc0_pins: mmc0-pins {
 377                                 pins = "PF0", "PF1", "PF2",
 378                                        "PF3", "PF4", "PF5";
 379                                 function = "mmc0";
 380                                 drive-strength = <30>;
 381                                 bias-pull-up;
 382                         };
 383
 384                         mmc1_pg_pins: mmc1-pg-pins {
 385                                 pins = "PG0", "PG1", "PG2",
 386                                        "PG3", "PG4", "PG5";
 387                                 function = "mmc1";
 388                                 drive-strength = <30>;
 389                                 bias-pull-up;
 390                         };
 391
 392                         mmc2_pins: mmc2-pins {
 393                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
 394                                        "PC10", "PC11", "PC12", "PC13", "PC14",
 395                                        "PC15", "PC24";
 396                                 function = "mmc2";
 397                                 drive-strength = <30>;
 398                                 bias-pull-up;
 399                         };
 400
 401                         uart0_pb_pins: uart0-pb-pins {
 402                                 pins = "PB22", "PB23";
 403                                 function = "uart0";
 404                         };
 405
 406                         uart3_pg_pins: uart3-pg-pins {
 407                                 pins = "PG6", "PG7";
 408                                 function = "uart3";
 409                         };
 410
 411                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 412                                 pins = "PG8", "PG9";
 413                                 function = "uart3";
 414                         };
 415                 };
 416
 417                 wdt: watchdog@1c20c90 {
 418                         compatible = "allwinner,sun4i-a10-wdt";
 419                         reg = <0x01c20c90 0x10>;
 420                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&osc24M>;
 422                 };
 423
 424                 uart0: serial@1c28000 {
 425                         compatible = "snps,dw-apb-uart";
 426                         reg = <0x01c28000 0x400>;
 427                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 428                         reg-shift = <2>;
 429                         reg-io-width = <4>;
 430                         clocks = <&ccu CLK_BUS_UART0>;
 431                         resets = <&ccu RST_BUS_UART0>;
 432                         status = "disabled";
 433                 };
 434
 435                 uart1: serial@1c28400 {
 436                         compatible = "snps,dw-apb-uart";
 437                         reg = <0x01c28400 0x400>;
 438                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 439                         reg-shift = <2>;
 440                         reg-io-width = <4>;
 441                         clocks = <&ccu CLK_BUS_UART1>;
 442                         resets = <&ccu RST_BUS_UART1>;
 443                         status = "disabled";
 444                 };
 445
 446                 uart2: serial@1c28800 {
 447                         compatible = "snps,dw-apb-uart";
 448                         reg = <0x01c28800 0x400>;
 449                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 450                         reg-shift = <2>;
 451                         reg-io-width = <4>;
 452                         clocks = <&ccu CLK_BUS_UART2>;
 453                         resets = <&ccu RST_BUS_UART2>;
 454                         status = "disabled";
 455                 };
 456
 457                 uart3: serial@1c28c00 {
 458                         compatible = "snps,dw-apb-uart";
 459                         reg = <0x01c28c00 0x400>;
 460                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 461                         reg-shift = <2>;
 462                         reg-io-width = <4>;
 463                         clocks = <&ccu CLK_BUS_UART3>;
 464                         resets = <&ccu RST_BUS_UART3>;
 465                         status = "disabled";
 466                 };
 467
 468                 uart4: serial@1c29000 {
 469                         compatible = "snps,dw-apb-uart";
 470                         reg = <0x01c29000 0x400>;
 471                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 472                         reg-shift = <2>;
 473                         reg-io-width = <4>;
 474                         clocks = <&ccu CLK_BUS_UART4>;
 475                         resets = <&ccu RST_BUS_UART4>;
 476                         status = "disabled";
 477                 };
 478
 479                 uart5: serial@1c29400 {
 480                         compatible = "snps,dw-apb-uart";
 481                         reg = <0x01c29400 0x400>;
 482                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 483                         reg-shift = <2>;
 484                         reg-io-width = <4>;
 485                         clocks = <&ccu CLK_BUS_UART5>;
 486                         resets = <&ccu RST_BUS_UART5>;
 487                         status = "disabled";
 488                 };
 489
 490                 uart6: serial@1c29800 {
 491                         compatible = "snps,dw-apb-uart";
 492                         reg = <0x01c29800 0x400>;
 493                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 494                         reg-shift = <2>;
 495                         reg-io-width = <4>;
 496                         clocks = <&ccu CLK_BUS_UART6>;
 497                         resets = <&ccu RST_BUS_UART6>;
 498                         status = "disabled";
 499                 };
 500
 501                 uart7: serial@1c29c00 {
 502                         compatible = "snps,dw-apb-uart";
 503                         reg = <0x01c29c00 0x400>;
 504                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 505                         reg-shift = <2>;
 506                         reg-io-width = <4>;
 507                         clocks = <&ccu CLK_BUS_UART7>;
 508                         resets = <&ccu RST_BUS_UART7>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c0: i2c@1c2ac00 {
 513                         compatible = "allwinner,sun6i-a31-i2c";
 514                         reg = <0x01c2ac00 0x400>;
 515                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&ccu CLK_BUS_I2C0>;
 517                         resets = <&ccu RST_BUS_I2C0>;
 518                         pinctrl-0 = <&i2c0_pins>;
 519                         pinctrl-names = "default";
 520                         status = "disabled";
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                 };
 524
 525                 i2c1: i2c@1c2b000 {
 526                         compatible = "allwinner,sun6i-a31-i2c";
 527                         reg = <0x01c2b000 0x400>;
 528                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&ccu CLK_BUS_I2C1>;
 530                         resets = <&ccu RST_BUS_I2C1>;
 531                         status = "disabled";
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                 };
 535
 536                 i2c2: i2c@1c2b400 {
 537                         compatible = "allwinner,sun6i-a31-i2c";
 538                         reg = <0x01c2b400 0x400>;
 539                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&ccu CLK_BUS_I2C2>;
 541                         resets = <&ccu RST_BUS_I2C2>;
 542                         status = "disabled";
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                 };
 546
 547                 i2c3: i2c@1c2b800 {
 548                         compatible = "allwinner,sun6i-a31-i2c";
 549                         reg = <0x01c2b800 0x400>;
 550                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&ccu CLK_BUS_I2C3>;
 552                         resets = <&ccu RST_BUS_I2C3>;
 553                         status = "disabled";
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                 };
 557
 558                 i2c4: i2c@1c2c000 {
 559                         compatible = "allwinner,sun6i-a31-i2c";
 560                         reg = <0x01c2c000 0x400>;
 561                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&ccu CLK_BUS_I2C4>;
 563                         resets = <&ccu RST_BUS_I2C4>;
 564                         status = "disabled";
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                 };
 568
 569                 ahci: sata@1c18000 {
 570                         compatible = "allwinner,sun8i-r40-ahci";
 571                         reg = <0x01c18000 0x1000>;
 572                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 573                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
 574                         resets = <&ccu RST_BUS_SATA>;
 575                         reset-names = "ahci";
 576                         status = "disabled";
 577
 578                 };
 579
 580                 gmac: ethernet@1c50000 {
 581                         compatible = "allwinner,sun8i-r40-gmac";
 582                         syscon = <&ccu>;
 583                         reg = <0x01c50000 0x10000>;
 584                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 585                         interrupt-names = "macirq";
 586                         resets = <&ccu RST_BUS_GMAC>;
 587                         reset-names = "stmmaceth";
 588                         clocks = <&ccu CLK_BUS_GMAC>;
 589                         clock-names = "stmmaceth";
 590                         status = "disabled";
 591
 592                         gmac_mdio: mdio {
 593                                 compatible = "snps,dwmac-mdio";
 594                                 #address-cells = <1>;
 595                                 #size-cells = <0>;
 596                         };
 597                 };
 598
 599                 tcon_top: tcon-top@1c70000 {
 600                         compatible = "allwinner,sun8i-r40-tcon-top";
 601                         reg = <0x01c70000 0x1000>;
 602                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 603                                  <&ccu CLK_TCON_TV0>,
 604                                  <&ccu CLK_TVE0>,
 605                                  <&ccu CLK_TCON_TV1>,
 606                                  <&ccu CLK_TVE1>,
 607                                  <&ccu CLK_DSI_DPHY>;
 608                         clock-names = "bus",
 609                                       "tcon-tv0",
 610                                       "tve0",
 611                                       "tcon-tv1",
 612                                       "tve1",
 613                                       "dsi";
 614                         clock-output-names = "tcon-top-tv0",
 615                                              "tcon-top-tv1",
 616                                              "tcon-top-dsi";
 617                         resets = <&ccu RST_BUS_TCON_TOP>;
 618                         #clock-cells = <1>;
 619
 620                         ports {
 621                                 #address-cells = <1>;
 622                                 #size-cells = <0>;
 623
 624                                 tcon_top_mixer0_in: port@0 {
 625                                         reg = <0>;
 626
 627                                         tcon_top_mixer0_in_mixer0: endpoint {
 628                                                 remote-endpoint = <&mixer0_out_tcon_top>;
 629                                         };
 630                                 };
 631
 632                                 tcon_top_mixer0_out: port@1 {
 633                                         #address-cells = <1>;
 634                                         #size-cells = <0>;
 635                                         reg = <1>;
 636
 637                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
 638                                                 reg = <0>;
 639                                         };
 640
 641                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
 642                                                 reg = <1>;
 643                                         };
 644
 645                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
 646                                                 reg = <2>;
 647                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
 648                                         };
 649
 650                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
 651                                                 reg = <3>;
 652                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
 653                                         };
 654                                 };
 655
 656                                 tcon_top_mixer1_in: port@2 {
 657                                         #address-cells = <1>;
 658                                         #size-cells = <0>;
 659                                         reg = <2>;
 660
 661                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
 662                                                 reg = <1>;
 663                                                 remote-endpoint = <&mixer1_out_tcon_top>;
 664                                         };
 665                                 };
 666
 667                                 tcon_top_mixer1_out: port@3 {
 668                                         #address-cells = <1>;
 669                                         #size-cells = <0>;
 670                                         reg = <3>;
 671
 672                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
 673                                                 reg = <0>;
 674                                         };
 675
 676                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
 677                                                 reg = <1>;
 678                                         };
 679
 680                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
 681                                                 reg = <2>;
 682                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
 683                                         };
 684
 685                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
 686                                                 reg = <3>;
 687                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
 688                                         };
 689                                 };
 690
 691                                 tcon_top_hdmi_in: port@4 {
 692                                         #address-cells = <1>;
 693                                         #size-cells = <0>;
 694                                         reg = <4>;
 695
 696                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
 697                                                 reg = <0>;
 698                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
 699                                         };
 700
 701                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
 702                                                 reg = <1>;
 703                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
 704                                         };
 705                                 };
 706
 707                                 tcon_top_hdmi_out: port@5 {
 708                                         reg = <5>;
 709
 710                                         tcon_top_hdmi_out_hdmi: endpoint {
 711                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 712                                         };
 713                                 };
 714                         };
 715                 };
 716
 717                 tcon_tv0: lcd-controller@1c73000 {
 718                         compatible = "allwinner,sun8i-r40-tcon-tv";
 719                         reg = <0x01c73000 0x1000>;
 720                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 721                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
 722                         clock-names = "ahb", "tcon-ch1";
 723                         resets = <&ccu RST_BUS_TCON_TV0>;
 724                         reset-names = "lcd";
 725                         status = "disabled";
 726
 727                         ports {
 728                                 #address-cells = <1>;
 729                                 #size-cells = <0>;
 730
 731                                 tcon_tv0_in: port@0 {
 732                                         #address-cells = <1>;
 733                                         #size-cells = <0>;
 734                                         reg = <0>;
 735
 736                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
 737                                                 reg = <0>;
 738                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
 739                                         };
 740
 741                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
 742                                                 reg = <1>;
 743                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
 744                                         };
 745                                 };
 746
 747                                 tcon_tv0_out: port@1 {
 748                                         #address-cells = <1>;
 749                                         #size-cells = <0>;
 750                                         reg = <1>;
 751
 752                                         tcon_tv0_out_tcon_top: endpoint@1 {
 753                                                 reg = <1>;
 754                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
 755                                         };
 756                                 };
 757                         };
 758                 };
 759
 760                 tcon_tv1: lcd-controller@1c74000 {
 761                         compatible = "allwinner,sun8i-r40-tcon-tv";
 762                         reg = <0x01c74000 0x1000>;
 763                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
 765                         clock-names = "ahb", "tcon-ch1";
 766                         resets = <&ccu RST_BUS_TCON_TV1>;
 767                         reset-names = "lcd";
 768                         status = "disabled";
 769
 770                         ports {
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773
 774                                 tcon_tv1_in: port@0 {
 775                                         #address-cells = <1>;
 776                                         #size-cells = <0>;
 777                                         reg = <0>;
 778
 779                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
 780                                                 reg = <0>;
 781                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
 782                                         };
 783
 784                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
 785                                                 reg = <1>;
 786                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
 787                                         };
 788                                 };
 789
 790                                 tcon_tv1_out: port@1 {
 791                                         #address-cells = <1>;
 792                                         #size-cells = <0>;
 793                                         reg = <1>;
 794
 795                                         tcon_tv1_out_tcon_top: endpoint@1 {
 796                                                 reg = <1>;
 797                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
 798                                         };
 799                                 };
 800                         };
 801                 };
 802
 803                 gic: interrupt-controller@1c81000 {
 804                         compatible = "arm,gic-400";
 805                         reg = <0x01c81000 0x1000>,
 806                               <0x01c82000 0x1000>,
 807                               <0x01c84000 0x2000>,
 808                               <0x01c86000 0x2000>;
 809                         interrupt-controller;
 810                         #interrupt-cells = <3>;
 811                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 812                 };
 813
 814                 hdmi: hdmi@1ee0000 {
 815                         compatible = "allwinner,sun8i-r40-dw-hdmi",
 816                                      "allwinner,sun8i-a83t-dw-hdmi";
 817                         reg = <0x01ee0000 0x10000>;
 818                         reg-io-width = <1>;
 819                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 820                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
 821                                  <&ccu CLK_HDMI>;
 822                         clock-names = "iahb", "isfr", "tmds";
 823                         resets = <&ccu RST_BUS_HDMI1>;
 824                         reset-names = "ctrl";
 825                         phys = <&hdmi_phy>;
 826                         phy-names = "phy";
 827                         status = "disabled";
 828
 829                         ports {
 830                                 #address-cells = <1>;
 831                                 #size-cells = <0>;
 832
 833                                 hdmi_in: port@0 {
 834                                         reg = <0>;
 835
 836                                         hdmi_in_tcon_top: endpoint {
 837                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 838                                         };
 839                                 };
 840
 841                                 hdmi_out: port@1 {
 842                                         reg = <1>;
 843                                 };
 844                         };
 845                 };
 846
 847                 hdmi_phy: hdmi-phy@1ef0000 {
 848                         compatible = "allwinner,sun8i-r40-hdmi-phy";
 849                         reg = <0x01ef0000 0x10000>;
 850                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
 851                                  <&ccu 7>, <&ccu 16>;
 852                         clock-names = "bus", "mod", "pll-0", "pll-1";
 853                         resets = <&ccu RST_BUS_HDMI0>;
 854                         reset-names = "phy";
 855                         #phy-cells = <0>;
 856                 };
 857         };
 858
 859         timer {
 860                 compatible = "arm,armv7-timer";
 861                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 862                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 863                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 864                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 865         };
 866 };