| blob | 23ba56df38f7341ac9caa3d0af0daa6f191108ee |
1 /*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
47 / {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 interrupt-parent = <&gic>;
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
56 cpu@0 {
57 compatible = "arm,cortex-a7";
58 device_type = "cpu";
59 reg = <0>;
60 clocks = <&ccu CLK_CPU>;
61 };
62 };
64 de: display-engine {
65 compatible = "allwinner,sun8i-v3s-display-engine";
66 allwinner,pipelines = <&mixer0>;
67 status = "disabled";
68 };
70 timer {
71 compatible = "arm,armv7-timer";
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
76 };
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
83 osc24M: osc24M_clk {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 clock-accuracy = <50000>;
88 clock-output-names = "osc24M";
89 };
91 osc32k: osc32k_clk {
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 clock-accuracy = <50000>;
96 clock-output-names = "ext-osc32k";
97 };
98 };
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
106 display_clocks: clock@1000000 {
107 compatible = "allwinner,sun8i-v3s-de2-clk";
108 reg = <0x01000000 0x100000>;
109 clocks = <&ccu CLK_BUS_DE>,
110 <&ccu CLK_DE>;
111 clock-names = "bus",
112 "mod";
113 resets = <&ccu RST_BUS_DE>;
114 #clock-cells = <1>;
115 #reset-cells = <1>;
116 };
118 mixer0: mixer@1100000 {
119 compatible = "allwinner,sun8i-v3s-de2-mixer";
120 reg = <0x01100000 0x100000>;
121 clocks = <&display_clocks 0>,
122 <&display_clocks 6>;
123 clock-names = "bus",
124 "mod";
125 resets = <&display_clocks 0>;
126 assigned-clocks = <&display_clocks 6>;
127 assigned-clock-rates = <150000000>;
129 ports {
130 #address-cells = <1>;
131 #size-cells = <0>;
133 mixer0_out: port@1 {
134 reg = <1>;
136 mixer0_out_tcon0: endpoint {
137 remote-endpoint = <&tcon0_in_mixer0>;
138 };
139 };
140 };
141 };
143 tcon0: lcd-controller@1c0c000 {
144 compatible = "allwinner,sun8i-v3s-tcon";
145 reg = <0x01c0c000 0x1000>;
146 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&ccu CLK_BUS_TCON0>,
148 <&ccu CLK_TCON0>;
149 clock-names = "ahb",
150 "tcon-ch0";
151 clock-output-names = "tcon-pixel-clock";
152 #clock-cells = <0>;
153 resets = <&ccu RST_BUS_TCON0>;
154 reset-names = "lcd";
155 status = "disabled";
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
161 tcon0_in: port@0 {
162 reg = <0>;
164 tcon0_in_mixer0: endpoint {
165 remote-endpoint = <&mixer0_out_tcon0>;
166 };
167 };
169 tcon0_out: port@1 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg = <1>;
173 };
174 };
175 };
178 mmc0: mmc@1c0f000 {
179 compatible = "allwinner,sun7i-a20-mmc";
180 reg = <0x01c0f000 0x1000>;
181 clocks = <&ccu CLK_BUS_MMC0>,
182 <&ccu CLK_MMC0>,
183 <&ccu CLK_MMC0_OUTPUT>,
184 <&ccu CLK_MMC0_SAMPLE>;
185 clock-names = "ahb",
186 "mmc",
187 "output",
188 "sample";
189 resets = <&ccu RST_BUS_MMC0>;
190 reset-names = "ahb";
191 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&mmc0_pins>;
194 status = "disabled";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
199 mmc1: mmc@1c10000 {
200 compatible = "allwinner,sun7i-a20-mmc";
201 reg = <0x01c10000 0x1000>;
202 clocks = <&ccu CLK_BUS_MMC1>,
203 <&ccu CLK_MMC1>,
204 <&ccu CLK_MMC1_OUTPUT>,
205 <&ccu CLK_MMC1_SAMPLE>;
206 clock-names = "ahb",
207 "mmc",
208 "output",
209 "sample";
210 resets = <&ccu RST_BUS_MMC1>;
211 reset-names = "ahb";
212 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&mmc1_pins>;
215 status = "disabled";
216 #address-cells = <1>;
217 #size-cells = <0>;
218 };
220 mmc2: mmc@1c11000 {
221 compatible = "allwinner,sun7i-a20-mmc";
222 reg = <0x01c11000 0x1000>;
223 clocks = <&ccu CLK_BUS_MMC2>,
224 <&ccu CLK_MMC2>,
225 <&ccu CLK_MMC2_OUTPUT>,
226 <&ccu CLK_MMC2_SAMPLE>;
227 clock-names = "ahb",
228 "mmc",
229 "output",
230 "sample";
231 resets = <&ccu RST_BUS_MMC2>;
232 reset-names = "ahb";
233 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
234 status = "disabled";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 };
239 usb_otg: usb@1c19000 {
240 compatible = "allwinner,sun8i-h3-musb";
241 reg = <0x01c19000 0x0400>;
242 clocks = <&ccu CLK_BUS_OTG>;
243 resets = <&ccu RST_BUS_OTG>;
244 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
245 interrupt-names = "mc";
246 phys = <&usbphy 0>;
247 phy-names = "usb";
248 extcon = <&usbphy 0>;
249 status = "disabled";
250 };
252 usbphy: phy@1c19400 {
253 compatible = "allwinner,sun8i-v3s-usb-phy";
254 reg = <0x01c19400 0x2c>,
255 <0x01c1a800 0x4>;
256 reg-names = "phy_ctrl",
257 "pmu0";
258 clocks = <&ccu CLK_USB_PHY0>;
259 clock-names = "usb0_phy";
260 resets = <&ccu RST_USB_PHY0>;
261 reset-names = "usb0_reset";
262 status = "disabled";
263 #phy-cells = <1>;
264 };
266 ccu: clock@1c20000 {
267 compatible = "allwinner,sun8i-v3s-ccu";
268 reg = <0x01c20000 0x400>;
269 clocks = <&osc24M>, <&rtc 0>;
270 clock-names = "hosc", "losc";
271 #clock-cells = <1>;
272 #reset-cells = <1>;
273 };
275 rtc: rtc@1c20400 {
276 #clock-cells = <1>;
277 compatible = "allwinner,sun8i-v3-rtc";
278 reg = <0x01c20400 0x54>;
279 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&osc32k>;
282 clock-output-names = "osc32k", "osc32k-out";
283 };
285 pio: pinctrl@1c20800 {
286 compatible = "allwinner,sun8i-v3s-pinctrl";
287 reg = <0x01c20800 0x400>;
288 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
291 clock-names = "apb", "hosc", "losc";
292 gpio-controller;
293 #gpio-cells = <3>;
294 interrupt-controller;
295 #interrupt-cells = <3>;
297 i2c0_pins: i2c0-pins {
298 pins = "PB6", "PB7";
299 function = "i2c0";
300 };
302 uart0_pb_pins: uart0-pb-pins {
303 pins = "PB8", "PB9";
304 function = "uart0";
305 };
307 mmc0_pins: mmc0-pins {
308 pins = "PF0", "PF1", "PF2", "PF3",
309 "PF4", "PF5";
310 function = "mmc0";
311 drive-strength = <30>;
312 bias-pull-up;
313 };
315 mmc1_pins: mmc1-pins {
316 pins = "PG0", "PG1", "PG2", "PG3",
317 "PG4", "PG5";
318 function = "mmc1";
319 drive-strength = <30>;
320 bias-pull-up;
321 };
323 spi0_pins: spi0-pins {
324 pins = "PC0", "PC1", "PC2", "PC3";
325 function = "spi0";
326 };
327 };
329 timer@1c20c00 {
330 compatible = "allwinner,sun8i-v3s-timer";
331 reg = <0x01c20c00 0xa0>;
332 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&osc24M>;
336 };
338 wdt0: watchdog@1c20ca0 {
339 compatible = "allwinner,sun6i-a31-wdt";
340 reg = <0x01c20ca0 0x20>;
341 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&osc24M>;
343 };
345 lradc: lradc@1c22800 {
346 compatible = "allwinner,sun4i-a10-lradc-keys";
347 reg = <0x01c22800 0x400>;
348 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
349 status = "disabled";
350 };
352 uart0: serial@1c28000 {
353 compatible = "snps,dw-apb-uart";
354 reg = <0x01c28000 0x400>;
355 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
356 reg-shift = <2>;
357 reg-io-width = <4>;
358 clocks = <&ccu CLK_BUS_UART0>;
359 resets = <&ccu RST_BUS_UART0>;
360 status = "disabled";
361 };
363 uart1: serial@1c28400 {
364 compatible = "snps,dw-apb-uart";
365 reg = <0x01c28400 0x400>;
366 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
367 reg-shift = <2>;
368 reg-io-width = <4>;
369 clocks = <&ccu CLK_BUS_UART1>;
370 resets = <&ccu RST_BUS_UART1>;
371 status = "disabled";
372 };
374 uart2: serial@1c28800 {
375 compatible = "snps,dw-apb-uart";
376 reg = <0x01c28800 0x400>;
377 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
378 reg-shift = <2>;
379 reg-io-width = <4>;
380 clocks = <&ccu CLK_BUS_UART2>;
381 resets = <&ccu RST_BUS_UART2>;
382 status = "disabled";
383 };
385 i2c0: i2c@1c2ac00 {
386 compatible = "allwinner,sun6i-a31-i2c";
387 reg = <0x01c2ac00 0x400>;
388 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&ccu CLK_BUS_I2C0>;
390 resets = <&ccu RST_BUS_I2C0>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c0_pins>;
393 status = "disabled";
394 #address-cells = <1>;
395 #size-cells = <0>;
396 };
398 i2c1: i2c@1c2b000 {
399 compatible = "allwinner,sun6i-a31-i2c";
400 reg = <0x01c2b000 0x400>;
401 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&ccu CLK_BUS_I2C1>;
403 resets = <&ccu RST_BUS_I2C1>;
404 status = "disabled";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 };
409 spi0: spi@1c68000 {
410 compatible = "allwinner,sun8i-h3-spi";
411 reg = <0x01c68000 0x1000>;
412 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
414 clock-names = "ahb", "mod";
415 pinctrl-names = "default";
416 pinctrl-0 = <&spi0_pins>;
417 resets = <&ccu RST_BUS_SPI0>;
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
423 gic: interrupt-controller@1c81000 {
424 compatible = "arm,gic-400";
425 reg = <0x01c81000 0x1000>,
426 <0x01c82000 0x1000>,
427 <0x01c84000 0x2000>,
428 <0x01c86000 0x2000>;
429 interrupt-controller;
430 #interrupt-cells = <3>;
431 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
432 };
433 };
434 };