arch/arm/boot/dts/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-de2.h>
  44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45 #include <dt-bindings/clock/sun8i-r-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/reset/sun8i-de2.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49 #include <dt-bindings/reset/sun8i-r-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         chosen {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 framebuffer-hdmi {
  62                         compatible = "allwinner,simple-framebuffer",
  63                                      "simple-framebuffer";
  64                         allwinner,pipeline = "mixer0-lcd0-hdmi";
  65                         clocks = <&display_clocks CLK_MIXER0>,
  66                                  <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  67                         status = "disabled";
  68                 };
  69
  70                 framebuffer-tve {
  71                         compatible = "allwinner,simple-framebuffer",
  72                                      "simple-framebuffer";
  73                         allwinner,pipeline = "mixer1-lcd1-tve";
  74                         clocks = <&display_clocks CLK_MIXER1>,
  75                                  <&ccu CLK_TVE>;
  76                         status = "disabled";
  77                 };
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 osc24M: osc24M_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <24000000>;
  89                         clock-accuracy = <50000>;
  90                         clock-output-names = "osc24M";
  91                 };
  92
  93                 osc32k: osc32k_clk {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <32768>;
  97                         clock-accuracy = <50000>;
  98                         clock-output-names = "ext_osc32k";
  99                 };
 100         };
 101
 102         de: display-engine {
 103                 compatible = "allwinner,sun8i-h3-display-engine";
 104                 allwinner,pipelines = <&mixer0>;
 105                 status = "disabled";
 106         };
 107
 108         soc {
 109                 compatible = "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 dma-ranges;
 113                 ranges;
 114
 115                 display_clocks: clock@1000000 {
 116                         /* compatible is in per SoC .dtsi file */
 117                         reg = <0x01000000 0x100000>;
 118                         clocks = <&ccu CLK_BUS_DE>,
 119                                  <&ccu CLK_DE>;
 120                         clock-names = "bus",
 121                                       "mod";
 122                         resets = <&ccu RST_BUS_DE>;
 123                         #clock-cells = <1>;
 124                         #reset-cells = <1>;
 125                 };
 126
 127                 mixer0: mixer@1100000 {
 128                         compatible = "allwinner,sun8i-h3-de2-mixer-0";
 129                         reg = <0x01100000 0x100000>;
 130                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 131                                  <&display_clocks CLK_MIXER0>;
 132                         clock-names = "bus",
 133                                       "mod";
 134                         resets = <&display_clocks RST_MIXER0>;
 135
 136                         ports {
 137                                 #address-cells = <1>;
 138                                 #size-cells = <0>;
 139
 140                                 mixer0_out: port@1 {
 141                                         reg = <1>;
 142
 143                                         mixer0_out_tcon0: endpoint {
 144                                                 remote-endpoint = <&tcon0_in_mixer0>;
 145                                         };
 146                                 };
 147                         };
 148                 };
 149
 150                 dma: dma-controller@1c02000 {
 151                         compatible = "allwinner,sun8i-h3-dma";
 152                         reg = <0x01c02000 0x1000>;
 153                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 154                         clocks = <&ccu CLK_BUS_DMA>;
 155                         resets = <&ccu RST_BUS_DMA>;
 156                         #dma-cells = <1>;
 157                 };
 158
 159                 tcon0: lcd-controller@1c0c000 {
 160                         compatible = "allwinner,sun8i-h3-tcon-tv",
 161                                      "allwinner,sun8i-a83t-tcon-tv";
 162                         reg = <0x01c0c000 0x1000>;
 163                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 165                         clock-names = "ahb", "tcon-ch1";
 166                         resets = <&ccu RST_BUS_TCON0>;
 167                         reset-names = "lcd";
 168
 169                         ports {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172
 173                                 tcon0_in: port@0 {
 174                                         reg = <0>;
 175
 176                                         tcon0_in_mixer0: endpoint {
 177                                                 remote-endpoint = <&mixer0_out_tcon0>;
 178                                         };
 179                                 };
 180
 181                                 tcon0_out: port@1 {
 182                                         #address-cells = <1>;
 183                                         #size-cells = <0>;
 184                                         reg = <1>;
 185
 186                                         tcon0_out_hdmi: endpoint@1 {
 187                                                 reg = <1>;
 188                                                 remote-endpoint = <&hdmi_in_tcon0>;
 189                                         };
 190                                 };
 191                         };
 192                 };
 193
 194                 mmc0: mmc@1c0f000 {
 195                         /* compatible and clocks are in per SoC .dtsi file */
 196                         reg = <0x01c0f000 0x1000>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&mmc0_pins>;
 199                         resets = <&ccu RST_BUS_MMC0>;
 200                         reset-names = "ahb";
 201                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 202                         status = "disabled";
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                 };
 206
 207                 mmc1: mmc@1c10000 {
 208                         /* compatible and clocks are in per SoC .dtsi file */
 209                         reg = <0x01c10000 0x1000>;
 210                         pinctrl-names = "default";
 211                         pinctrl-0 = <&mmc1_pins>;
 212                         resets = <&ccu RST_BUS_MMC1>;
 213                         reset-names = "ahb";
 214                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 215                         status = "disabled";
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                 };
 219
 220                 mmc2: mmc@1c11000 {
 221                         /* compatible and clocks are in per SoC .dtsi file */
 222                         reg = <0x01c11000 0x1000>;
 223                         resets = <&ccu RST_BUS_MMC2>;
 224                         reset-names = "ahb";
 225                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 226                         status = "disabled";
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                 };
 230
 231                 sid: eeprom@1c14000 {
 232                         /* compatible is in per SoC .dtsi file */
 233                         reg = <0x1c14000 0x400>;
 234                 };
 235
 236                 usb_otg: usb@1c19000 {
 237                         compatible = "allwinner,sun8i-h3-musb";
 238                         reg = <0x01c19000 0x400>;
 239                         clocks = <&ccu CLK_BUS_OTG>;
 240                         resets = <&ccu RST_BUS_OTG>;
 241                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 242                         interrupt-names = "mc";
 243                         phys = <&usbphy 0>;
 244                         phy-names = "usb";
 245                         extcon = <&usbphy 0>;
 246                         dr_mode = "otg";
 247                         status = "disabled";
 248                 };
 249
 250                 usbphy: phy@1c19400 {
 251                         compatible = "allwinner,sun8i-h3-usb-phy";
 252                         reg = <0x01c19400 0x2c>,
 253                               <0x01c1a800 0x4>,
 254                               <0x01c1b800 0x4>,
 255                               <0x01c1c800 0x4>,
 256                               <0x01c1d800 0x4>;
 257                         reg-names = "phy_ctrl",
 258                                     "pmu0",
 259                                     "pmu1",
 260                                     "pmu2",
 261                                     "pmu3";
 262                         clocks = <&ccu CLK_USB_PHY0>,
 263                                  <&ccu CLK_USB_PHY1>,
 264                                  <&ccu CLK_USB_PHY2>,
 265                                  <&ccu CLK_USB_PHY3>;
 266                         clock-names = "usb0_phy",
 267                                       "usb1_phy",
 268                                       "usb2_phy",
 269                                       "usb3_phy";
 270                         resets = <&ccu RST_USB_PHY0>,
 271                                  <&ccu RST_USB_PHY1>,
 272                                  <&ccu RST_USB_PHY2>,
 273                                  <&ccu RST_USB_PHY3>;
 274                         reset-names = "usb0_reset",
 275                                       "usb1_reset",
 276                                       "usb2_reset",
 277                                       "usb3_reset";
 278                         status = "disabled";
 279                         #phy-cells = <1>;
 280                 };
 281
 282                 ehci0: usb@1c1a000 {
 283                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 284                         reg = <0x01c1a000 0x100>;
 285                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 286                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 287                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 288                         status = "disabled";
 289                 };
 290
 291                 ohci0: usb@1c1a400 {
 292                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 293                         reg = <0x01c1a400 0x100>;
 294                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 296                                  <&ccu CLK_USB_OHCI0>;
 297                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 298                         status = "disabled";
 299                 };
 300
 301                 ehci1: usb@1c1b000 {
 302                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 303                         reg = <0x01c1b000 0x100>;
 304                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 306                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 307                         phys = <&usbphy 1>;
 308                         phy-names = "usb";
 309                         status = "disabled";
 310                 };
 311
 312                 ohci1: usb@1c1b400 {
 313                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 314                         reg = <0x01c1b400 0x100>;
 315                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 317                                  <&ccu CLK_USB_OHCI1>;
 318                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 319                         phys = <&usbphy 1>;
 320                         phy-names = "usb";
 321                         status = "disabled";
 322                 };
 323
 324                 ehci2: usb@1c1c000 {
 325                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 326                         reg = <0x01c1c000 0x100>;
 327                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 329                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 330                         phys = <&usbphy 2>;
 331                         phy-names = "usb";
 332                         status = "disabled";
 333                 };
 334
 335                 ohci2: usb@1c1c400 {
 336                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 337                         reg = <0x01c1c400 0x100>;
 338                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 340                                  <&ccu CLK_USB_OHCI2>;
 341                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 342                         phys = <&usbphy 2>;
 343                         phy-names = "usb";
 344                         status = "disabled";
 345                 };
 346
 347                 ehci3: usb@1c1d000 {
 348                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 349                         reg = <0x01c1d000 0x100>;
 350                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 351                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 352                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 353                         phys = <&usbphy 3>;
 354                         phy-names = "usb";
 355                         status = "disabled";
 356                 };
 357
 358                 ohci3: usb@1c1d400 {
 359                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 360                         reg = <0x01c1d400 0x100>;
 361                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 363                                  <&ccu CLK_USB_OHCI3>;
 364                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 365                         phys = <&usbphy 3>;
 366                         phy-names = "usb";
 367                         status = "disabled";
 368                 };
 369
 370                 ccu: clock@1c20000 {
 371                         /* compatible is in per SoC .dtsi file */
 372                         reg = <0x01c20000 0x400>;
 373                         clocks = <&osc24M>, <&rtc 0>;
 374                         clock-names = "hosc", "losc";
 375                         #clock-cells = <1>;
 376                         #reset-cells = <1>;
 377                 };
 378
 379                 pio: pinctrl@1c20800 {
 380                         /* compatible is in per SoC .dtsi file */
 381                         reg = <0x01c20800 0x400>;
 382                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 383                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 385                         clock-names = "apb", "hosc", "losc";
 386                         gpio-controller;
 387                         #gpio-cells = <3>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <3>;
 390
 391                         csi_pins: csi-pins {
 392                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 393                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 394                                        "PE11";
 395                                 function = "csi";
 396                         };
 397
 398                         emac_rgmii_pins: emac-rgmii-pins {
 399                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 400                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 401                                        "PD12", "PD13", "PD15", "PD16", "PD17";
 402                                 function = "emac";
 403                                 drive-strength = <40>;
 404                         };
 405
 406                         i2c0_pins: i2c0-pins {
 407                                 pins = "PA11", "PA12";
 408                                 function = "i2c0";
 409                         };
 410
 411                         i2c1_pins: i2c1-pins {
 412                                 pins = "PA18", "PA19";
 413                                 function = "i2c1";
 414                         };
 415
 416                         i2c2_pins: i2c2-pins {
 417                                 pins = "PE12", "PE13";
 418                                 function = "i2c2";
 419                         };
 420
 421                         mmc0_pins: mmc0-pins {
 422                                 pins = "PF0", "PF1", "PF2", "PF3",
 423                                        "PF4", "PF5";
 424                                 function = "mmc0";
 425                                 drive-strength = <30>;
 426                                 bias-pull-up;
 427                         };
 428
 429                         mmc1_pins: mmc1-pins {
 430                                 pins = "PG0", "PG1", "PG2", "PG3",
 431                                        "PG4", "PG5";
 432                                 function = "mmc1";
 433                                 drive-strength = <30>;
 434                                 bias-pull-up;
 435                         };
 436
 437                         mmc2_8bit_pins: mmc2-8bit-pins {
 438                                 pins = "PC5", "PC6", "PC8",
 439                                        "PC9", "PC10", "PC11",
 440                                        "PC12", "PC13", "PC14",
 441                                        "PC15", "PC16";
 442                                 function = "mmc2";
 443                                 drive-strength = <30>;
 444                                 bias-pull-up;
 445                         };
 446
 447                         spdif_tx_pin: spdif-tx-pin {
 448                                 pins = "PA17";
 449                                 function = "spdif";
 450                         };
 451
 452                         spi0_pins: spi0-pins {
 453                                 pins = "PC0", "PC1", "PC2", "PC3";
 454                                 function = "spi0";
 455                         };
 456
 457                         spi1_pins: spi1-pins {
 458                                 pins = "PA15", "PA16", "PA14", "PA13";
 459                                 function = "spi1";
 460                         };
 461
 462                         uart0_pa_pins: uart0-pa-pins {
 463                                 pins = "PA4", "PA5";
 464                                 function = "uart0";
 465                         };
 466
 467                         uart1_pins: uart1-pins {
 468                                 pins = "PG6", "PG7";
 469                                 function = "uart1";
 470                         };
 471
 472                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 473                                 pins = "PG8", "PG9";
 474                                 function = "uart1";
 475                         };
 476
 477                         uart2_pins: uart2-pins {
 478                                 pins = "PA0", "PA1";
 479                                 function = "uart2";
 480                         };
 481
 482                         uart2_rts_cts_pins: uart2-rts-cts-pins {
 483                                 pins = "PA2", "PA3";
 484                                 function = "uart2";
 485                         };
 486
 487                         uart3_pins: uart3-pins {
 488                                 pins = "PA13", "PA14";
 489                                 function = "uart3";
 490                         };
 491
 492                         uart3_rts_cts_pins: uart3-rts-cts-pins {
 493                                 pins = "PA15", "PA16";
 494                                 function = "uart3";
 495                         };
 496                 };
 497
 498                 timer@1c20c00 {
 499                         compatible = "allwinner,sun8i-a23-timer";
 500                         reg = <0x01c20c00 0xa0>;
 501                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 502                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&osc24M>;
 504                 };
 505
 506                 emac: ethernet@1c30000 {
 507                         compatible = "allwinner,sun8i-h3-emac";
 508                         syscon = <&syscon>;
 509                         reg = <0x01c30000 0x10000>;
 510                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 511                         interrupt-names = "macirq";
 512                         resets = <&ccu RST_BUS_EMAC>;
 513                         reset-names = "stmmaceth";
 514                         clocks = <&ccu CLK_BUS_EMAC>;
 515                         clock-names = "stmmaceth";
 516                         status = "disabled";
 517
 518                         mdio: mdio {
 519                                 #address-cells = <1>;
 520                                 #size-cells = <0>;
 521                                 compatible = "snps,dwmac-mdio";
 522                         };
 523
 524                         mdio-mux {
 525                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 526                                 #address-cells = <1>;
 527                                 #size-cells = <0>;
 528
 529                                 mdio-parent-bus = <&mdio>;
 530                                 /* Only one MDIO is usable at the time */
 531                                 internal_mdio: mdio@1 {
 532                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 533                                         reg = <1>;
 534                                         #address-cells = <1>;
 535                                         #size-cells = <0>;
 536
 537                                         int_mii_phy: ethernet-phy@1 {
 538                                                 compatible = "ethernet-phy-ieee802.3-c22";
 539                                                 reg = <1>;
 540                                                 clocks = <&ccu CLK_BUS_EPHY>;
 541                                                 resets = <&ccu RST_BUS_EPHY>;
 542                                         };
 543                                 };
 544
 545                                 external_mdio: mdio@2 {
 546                                         reg = <2>;
 547                                         #address-cells = <1>;
 548                                         #size-cells = <0>;
 549                                 };
 550                         };
 551                 };
 552
 553                 mbus: dram-controller@1c62000 {
 554                         compatible = "allwinner,sun8i-h3-mbus";
 555                         reg = <0x01c62000 0x1000>;
 556                         clocks = <&ccu 113>;
 557                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
 558                         #interconnect-cells = <1>;
 559                 };
 560
 561                 spi0: spi@1c68000 {
 562                         compatible = "allwinner,sun8i-h3-spi";
 563                         reg = <0x01c68000 0x1000>;
 564                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 566                         clock-names = "ahb", "mod";
 567                         dmas = <&dma 23>, <&dma 23>;
 568                         dma-names = "rx", "tx";
 569                         pinctrl-names = "default";
 570                         pinctrl-0 = <&spi0_pins>;
 571                         resets = <&ccu RST_BUS_SPI0>;
 572                         status = "disabled";
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                 };
 576
 577                 spi1: spi@1c69000 {
 578                         compatible = "allwinner,sun8i-h3-spi";
 579                         reg = <0x01c69000 0x1000>;
 580                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 581                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 582                         clock-names = "ahb", "mod";
 583                         dmas = <&dma 24>, <&dma 24>;
 584                         dma-names = "rx", "tx";
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&spi1_pins>;
 587                         resets = <&ccu RST_BUS_SPI1>;
 588                         status = "disabled";
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591                 };
 592
 593                 wdt0: watchdog@1c20ca0 {
 594                         compatible = "allwinner,sun6i-a31-wdt";
 595                         reg = <0x01c20ca0 0x20>;
 596                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&osc24M>;
 598                 };
 599
 600                 spdif: spdif@1c21000 {
 601                         #sound-dai-cells = <0>;
 602                         compatible = "allwinner,sun8i-h3-spdif";
 603                         reg = <0x01c21000 0x400>;
 604                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 606                         resets = <&ccu RST_BUS_SPDIF>;
 607                         clock-names = "apb", "spdif";
 608                         dmas = <&dma 2>;
 609                         dma-names = "tx";
 610                         status = "disabled";
 611                 };
 612
 613                 pwm: pwm@1c21400 {
 614                         compatible = "allwinner,sun8i-h3-pwm";
 615                         reg = <0x01c21400 0x8>;
 616                         clocks = <&osc24M>;
 617                         #pwm-cells = <3>;
 618                         status = "disabled";
 619                 };
 620
 621                 i2s0: i2s@1c22000 {
 622                         #sound-dai-cells = <0>;
 623                         compatible = "allwinner,sun8i-h3-i2s";
 624                         reg = <0x01c22000 0x400>;
 625                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 626                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 627                         clock-names = "apb", "mod";
 628                         dmas = <&dma 3>, <&dma 3>;
 629                         resets = <&ccu RST_BUS_I2S0>;
 630                         dma-names = "rx", "tx";
 631                         status = "disabled";
 632                 };
 633
 634                 i2s1: i2s@1c22400 {
 635                         #sound-dai-cells = <0>;
 636                         compatible = "allwinner,sun8i-h3-i2s";
 637                         reg = <0x01c22400 0x400>;
 638                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 639                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 640                         clock-names = "apb", "mod";
 641                         dmas = <&dma 4>, <&dma 4>;
 642                         resets = <&ccu RST_BUS_I2S1>;
 643                         dma-names = "rx", "tx";
 644                         status = "disabled";
 645                 };
 646
 647                 codec: codec@1c22c00 {
 648                         #sound-dai-cells = <0>;
 649                         compatible = "allwinner,sun8i-h3-codec";
 650                         reg = <0x01c22c00 0x400>;
 651                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 652                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 653                         clock-names = "apb", "codec";
 654                         resets = <&ccu RST_BUS_CODEC>;
 655                         dmas = <&dma 15>, <&dma 15>;
 656                         dma-names = "rx", "tx";
 657                         allwinner,codec-analog-controls = <&codec_analog>;
 658                         status = "disabled";
 659                 };
 660
 661                 uart0: serial@1c28000 {
 662                         compatible = "snps,dw-apb-uart";
 663                         reg = <0x01c28000 0x400>;
 664                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 665                         reg-shift = <2>;
 666                         reg-io-width = <4>;
 667                         clocks = <&ccu CLK_BUS_UART0>;
 668                         resets = <&ccu RST_BUS_UART0>;
 669                         dmas = <&dma 6>, <&dma 6>;
 670                         dma-names = "rx", "tx";
 671                         status = "disabled";
 672                 };
 673
 674                 uart1: serial@1c28400 {
 675                         compatible = "snps,dw-apb-uart";
 676                         reg = <0x01c28400 0x400>;
 677                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 678                         reg-shift = <2>;
 679                         reg-io-width = <4>;
 680                         clocks = <&ccu CLK_BUS_UART1>;
 681                         resets = <&ccu RST_BUS_UART1>;
 682                         dmas = <&dma 7>, <&dma 7>;
 683                         dma-names = "rx", "tx";
 684                         status = "disabled";
 685                 };
 686
 687                 uart2: serial@1c28800 {
 688                         compatible = "snps,dw-apb-uart";
 689                         reg = <0x01c28800 0x400>;
 690                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 691                         reg-shift = <2>;
 692                         reg-io-width = <4>;
 693                         clocks = <&ccu CLK_BUS_UART2>;
 694                         resets = <&ccu RST_BUS_UART2>;
 695                         dmas = <&dma 8>, <&dma 8>;
 696                         dma-names = "rx", "tx";
 697                         status = "disabled";
 698                 };
 699
 700                 uart3: serial@1c28c00 {
 701                         compatible = "snps,dw-apb-uart";
 702                         reg = <0x01c28c00 0x400>;
 703                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 704                         reg-shift = <2>;
 705                         reg-io-width = <4>;
 706                         clocks = <&ccu CLK_BUS_UART3>;
 707                         resets = <&ccu RST_BUS_UART3>;
 708                         dmas = <&dma 9>, <&dma 9>;
 709                         dma-names = "rx", "tx";
 710                         status = "disabled";
 711                 };
 712
 713                 i2c0: i2c@1c2ac00 {
 714                         compatible = "allwinner,sun6i-a31-i2c";
 715                         reg = <0x01c2ac00 0x400>;
 716                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&ccu CLK_BUS_I2C0>;
 718                         resets = <&ccu RST_BUS_I2C0>;
 719                         pinctrl-names = "default";
 720                         pinctrl-0 = <&i2c0_pins>;
 721                         status = "disabled";
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                 };
 725
 726                 i2c1: i2c@1c2b000 {
 727                         compatible = "allwinner,sun6i-a31-i2c";
 728                         reg = <0x01c2b000 0x400>;
 729                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&ccu CLK_BUS_I2C1>;
 731                         resets = <&ccu RST_BUS_I2C1>;
 732                         pinctrl-names = "default";
 733                         pinctrl-0 = <&i2c1_pins>;
 734                         status = "disabled";
 735                         #address-cells = <1>;
 736                         #size-cells = <0>;
 737                 };
 738
 739                 i2c2: i2c@1c2b400 {
 740                         compatible = "allwinner,sun6i-a31-i2c";
 741                         reg = <0x01c2b400 0x400>;
 742                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 743                         clocks = <&ccu CLK_BUS_I2C2>;
 744                         resets = <&ccu RST_BUS_I2C2>;
 745                         pinctrl-names = "default";
 746                         pinctrl-0 = <&i2c2_pins>;
 747                         status = "disabled";
 748                         #address-cells = <1>;
 749                         #size-cells = <0>;
 750                 };
 751
 752                 gic: interrupt-controller@1c81000 {
 753                         compatible = "arm,gic-400";
 754                         reg = <0x01c81000 0x1000>,
 755                               <0x01c82000 0x2000>,
 756                               <0x01c84000 0x2000>,
 757                               <0x01c86000 0x2000>;
 758                         interrupt-controller;
 759                         #interrupt-cells = <3>;
 760                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 761                 };
 762
 763                 csi: camera@1cb0000 {
 764                         compatible = "allwinner,sun8i-h3-csi";
 765                         reg = <0x01cb0000 0x1000>;
 766                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 767                         clocks = <&ccu CLK_BUS_CSI>,
 768                                  <&ccu CLK_CSI_SCLK>,
 769                                  <&ccu CLK_DRAM_CSI>;
 770                         clock-names = "bus", "mod", "ram";
 771                         resets = <&ccu RST_BUS_CSI>;
 772                         pinctrl-names = "default";
 773                         pinctrl-0 = <&csi_pins>;
 774                         status = "disabled";
 775                 };
 776
 777                 hdmi: hdmi@1ee0000 {
 778                         compatible = "allwinner,sun8i-h3-dw-hdmi",
 779                                      "allwinner,sun8i-a83t-dw-hdmi";
 780                         reg = <0x01ee0000 0x10000>;
 781                         reg-io-width = <1>;
 782                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 784                                  <&ccu CLK_HDMI>;
 785                         clock-names = "iahb", "isfr", "tmds";
 786                         resets = <&ccu RST_BUS_HDMI1>;
 787                         reset-names = "ctrl";
 788                         phys = <&hdmi_phy>;
 789                         phy-names = "phy";
 790                         status = "disabled";
 791
 792                         ports {
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795
 796                                 hdmi_in: port@0 {
 797                                         reg = <0>;
 798
 799                                         hdmi_in_tcon0: endpoint {
 800                                                 remote-endpoint = <&tcon0_out_hdmi>;
 801                                         };
 802                                 };
 803
 804                                 hdmi_out: port@1 {
 805                                         reg = <1>;
 806                                 };
 807                         };
 808                 };
 809
 810                 hdmi_phy: hdmi-phy@1ef0000 {
 811                         compatible = "allwinner,sun8i-h3-hdmi-phy";
 812                         reg = <0x01ef0000 0x10000>;
 813                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 814                                  <&ccu 6>;
 815                         clock-names = "bus", "mod", "pll-0";
 816                         resets = <&ccu RST_BUS_HDMI0>;
 817                         reset-names = "phy";
 818                         #phy-cells = <0>;
 819                 };
 820
 821                 rtc: rtc@1f00000 {
 822                         /* compatible is in per SoC .dtsi file */
 823                         reg = <0x01f00000 0x400>;
 824                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 825                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 826                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 827                         clocks = <&osc32k>;
 828                         #clock-cells = <1>;
 829                 };
 830
 831                 r_ccu: clock@1f01400 {
 832                         compatible = "allwinner,sun8i-h3-r-ccu";
 833                         reg = <0x01f01400 0x100>;
 834                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
 835                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 836                         #clock-cells = <1>;
 837                         #reset-cells = <1>;
 838                 };
 839
 840                 codec_analog: codec-analog@1f015c0 {
 841                         compatible = "allwinner,sun8i-h3-codec-analog";
 842                         reg = <0x01f015c0 0x4>;
 843                 };
 844
 845                 ir: ir@1f02000 {
 846                         compatible = "allwinner,sun6i-a31-ir";
 847                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 848                         clock-names = "apb", "ir";
 849                         resets = <&r_ccu RST_APB0_IR>;
 850                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 851                         reg = <0x01f02000 0x400>;
 852                         status = "disabled";
 853                 };
 854
 855                 r_i2c: i2c@1f02400 {
 856                         compatible = "allwinner,sun6i-a31-i2c";
 857                         reg = <0x01f02400 0x400>;
 858                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 859                         pinctrl-names = "default";
 860                         pinctrl-0 = <&r_i2c_pins>;
 861                         clocks = <&r_ccu CLK_APB0_I2C>;
 862                         resets = <&r_ccu RST_APB0_I2C>;
 863                         status = "disabled";
 864                         #address-cells = <1>;
 865                         #size-cells = <0>;
 866                 };
 867
 868                 r_pio: pinctrl@1f02c00 {
 869                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 870                         reg = <0x01f02c00 0x400>;
 871                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 872                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
 873                         clock-names = "apb", "hosc", "losc";
 874                         gpio-controller;
 875                         #gpio-cells = <3>;
 876                         interrupt-controller;
 877                         #interrupt-cells = <3>;
 878
 879                         r_ir_rx_pin: r-ir-rx-pin {
 880                                 pins = "PL11";
 881                                 function = "s_cir_rx";
 882                         };
 883
 884                         r_i2c_pins: r-i2c-pins {
 885                                 pins = "PL0", "PL1";
 886                                 function = "s_i2c";
 887                         };
 888                 };
 889         };
 890 };