arch/arm/boot/dts/tegra124.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra124-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra124-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 / {
  11         compatible = "nvidia,tegra124";
  12         interrupt-parent = <&lic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x0 0x80000000 0x0 0x0>;
  19         };
  20
  21         pcie@1003000 {
  22                 compatible = "nvidia,tegra124-pcie";
  23                 device_type = "pci";
  24                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  25                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  26                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  27                 reg-names = "pads", "afi", "cs";
  28                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  29                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  30                 interrupt-names = "intr", "msi";
  31
  32                 #interrupt-cells = <1>;
  33                 interrupt-map-mask = <0 0 0 0>;
  34                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 bus-range = <0x00 0xff>;
  37                 #address-cells = <3>;
  38                 #size-cells = <2>;
  39
  40                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  41                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  42                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  43                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  44                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  45
  46                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  47                          <&tegra_car TEGRA124_CLK_AFI>,
  48                          <&tegra_car TEGRA124_CLK_PLL_E>,
  49                          <&tegra_car TEGRA124_CLK_CML0>;
  50                 clock-names = "pex", "afi", "pll_e", "cml";
  51                 resets = <&tegra_car 70>,
  52                          <&tegra_car 72>,
  53                          <&tegra_car 74>;
  54                 reset-names = "pex", "afi", "pcie_x";
  55                 status = "disabled";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         bus-range = <0x00 0xff>;
  62                         status = "disabled";
  63
  64                         #address-cells = <3>;
  65                         #size-cells = <2>;
  66                         ranges;
  67
  68                         nvidia,num-lanes = <2>;
  69                 };
  70
  71                 pci@2,0 {
  72                         device_type = "pci";
  73                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  74                         reg = <0x001000 0 0 0 0>;
  75                         bus-range = <0x00 0xff>;
  76                         status = "disabled";
  77
  78                         #address-cells = <3>;
  79                         #size-cells = <2>;
  80                         ranges;
  81
  82                         nvidia,num-lanes = <1>;
  83                 };
  84         };
  85
  86         host1x@50000000 {
  87                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  88                 reg = <0x0 0x50000000 0x0 0x00034000>;
  89                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  90                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  91                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  92                 resets = <&tegra_car 28>;
  93                 reset-names = "host1x";
  94                 iommus = <&mc TEGRA_SWGROUP_HC>;
  95
  96                 #address-cells = <2>;
  97                 #size-cells = <2>;
  98
  99                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 100
 101                 dc@54200000 {
 102                         compatible = "nvidia,tegra124-dc";
 103                         reg = <0x0 0x54200000 0x0 0x00040000>;
 104                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 106                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 107                         clock-names = "dc", "parent";
 108                         resets = <&tegra_car 27>;
 109                         reset-names = "dc";
 110
 111                         iommus = <&mc TEGRA_SWGROUP_DC>;
 112
 113                         nvidia,head = <0>;
 114                 };
 115
 116                 dc@54240000 {
 117                         compatible = "nvidia,tegra124-dc";
 118                         reg = <0x0 0x54240000 0x0 0x00040000>;
 119                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 121                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 122                         clock-names = "dc", "parent";
 123                         resets = <&tegra_car 26>;
 124                         reset-names = "dc";
 125
 126                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 127
 128                         nvidia,head = <1>;
 129                 };
 130
 131                 hdmi: hdmi@54280000 {
 132                         compatible = "nvidia,tegra124-hdmi";
 133                         reg = <0x0 0x54280000 0x0 0x00040000>;
 134                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 136                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 137                         clock-names = "hdmi", "parent";
 138                         resets = <&tegra_car 51>;
 139                         reset-names = "hdmi";
 140                         status = "disabled";
 141                 };
 142
 143                 vic@54340000 {
 144                         compatible = "nvidia,tegra124-vic";
 145                         reg = <0x0 0x54340000 0x0 0x00040000>;
 146                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&tegra_car TEGRA124_CLK_VIC03>;
 148                         clock-names = "vic";
 149                         resets = <&tegra_car 178>;
 150                         reset-names = "vic";
 151
 152                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 153                 };
 154
 155                 sor@54540000 {
 156                         compatible = "nvidia,tegra124-sor";
 157                         reg = <0x0 0x54540000 0x0 0x00040000>;
 158                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 160                                  <&tegra_car TEGRA124_CLK_SOR0_OUT>,
 161                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 162                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 163                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 164                         clock-names = "sor", "out", "parent", "dp", "safe";
 165                         resets = <&tegra_car 182>;
 166                         reset-names = "sor";
 167                         status = "disabled";
 168                 };
 169
 170                 dpaux: dpaux@545c0000 {
 171                         compatible = "nvidia,tegra124-dpaux";
 172                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 173                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 175                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 176                         clock-names = "dpaux", "parent";
 177                         resets = <&tegra_car 181>;
 178                         reset-names = "dpaux";
 179                         status = "disabled";
 180                 };
 181         };
 182
 183         gic: interrupt-controller@50041000 {
 184                 compatible = "arm,cortex-a15-gic";
 185                 #interrupt-cells = <3>;
 186                 interrupt-controller;
 187                 reg = <0x0 0x50041000 0x0 0x1000>,
 188                       <0x0 0x50042000 0x0 0x1000>,
 189                       <0x0 0x50044000 0x0 0x2000>,
 190                       <0x0 0x50046000 0x0 0x2000>;
 191                 interrupts = <GIC_PPI 9
 192                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 193                 interrupt-parent = <&gic>;
 194         };
 195
 196         /*
 197          * Please keep the following 0, notation in place as a former mainline
 198          * U-Boot version was looking for that particular notation in order to
 199          * perform required fix-ups on that GPU node.
 200          */
 201         gpu@0,57000000 {
 202                 compatible = "nvidia,gk20a";
 203                 reg = <0x0 0x57000000 0x0 0x01000000>,
 204                       <0x0 0x58000000 0x0 0x01000000>;
 205                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 207                 interrupt-names = "stall", "nonstall";
 208                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 209                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 210                 clock-names = "gpu", "pwr";
 211                 resets = <&tegra_car 184>;
 212                 reset-names = "gpu";
 213
 214                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 215
 216                 status = "disabled";
 217         };
 218
 219         lic: interrupt-controller@60004000 {
 220                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 221                 reg = <0x0 0x60004000 0x0 0x100>,
 222                       <0x0 0x60004100 0x0 0x100>,
 223                       <0x0 0x60004200 0x0 0x100>,
 224                       <0x0 0x60004300 0x0 0x100>,
 225                       <0x0 0x60004400 0x0 0x100>;
 226                 interrupt-controller;
 227                 #interrupt-cells = <3>;
 228                 interrupt-parent = <&gic>;
 229         };
 230
 231         timer@60005000 {
 232                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 233                 reg = <0x0 0x60005000 0x0 0x400>;
 234                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 241         };
 242
 243         tegra_car: clock@60006000 {
 244                 compatible = "nvidia,tegra124-car";
 245                 reg = <0x0 0x60006000 0x0 0x1000>;
 246                 #clock-cells = <1>;
 247                 #reset-cells = <1>;
 248                 nvidia,external-memory-controller = <&emc>;
 249         };
 250
 251         flow-controller@60007000 {
 252                 compatible = "nvidia,tegra124-flowctrl";
 253                 reg = <0x0 0x60007000 0x0 0x1000>;
 254         };
 255
 256         actmon@6000c800 {
 257                 compatible = "nvidia,tegra124-actmon";
 258                 reg = <0x0 0x6000c800 0x0 0x400>;
 259                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 261                          <&tegra_car TEGRA124_CLK_EMC>;
 262                 clock-names = "actmon", "emc";
 263                 resets = <&tegra_car 119>;
 264                 reset-names = "actmon";
 265         };
 266
 267         gpio: gpio@6000d000 {
 268                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 269                 reg = <0x0 0x6000d000 0x0 0x1000>;
 270                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 278                 #gpio-cells = <2>;
 279                 gpio-controller;
 280                 #interrupt-cells = <2>;
 281                 interrupt-controller;
 282                 /*
 283                 gpio-ranges = <&pinmux 0 0 251>;
 284                 */
 285         };
 286
 287         apbdma: dma@60020000 {
 288                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 289                 reg = <0x0 0x60020000 0x0 0x1400>;
 290                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 323                 resets = <&tegra_car 34>;
 324                 reset-names = "dma";
 325                 #dma-cells = <1>;
 326         };
 327
 328         apbmisc@70000800 {
 329                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 330                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 331                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 332         };
 333
 334         pinmux: pinmux@70000868 {
 335                 compatible = "nvidia,tegra124-pinmux";
 336                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 337                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 338                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 339         };
 340
 341         /*
 342          * There are two serial driver i.e. 8250 based simple serial
 343          * driver and APB DMA based serial driver for higher baudrate
 344          * and performace. To enable the 8250 based driver, the compatible
 345          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 346          * the APB DMA based serial driver, the compatible is
 347          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 348          */
 349         uarta: serial@70006000 {
 350                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 351                 reg = <0x0 0x70006000 0x0 0x40>;
 352                 reg-shift = <2>;
 353                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 355                 resets = <&tegra_car 6>;
 356                 reset-names = "serial";
 357                 dmas = <&apbdma 8>, <&apbdma 8>;
 358                 dma-names = "rx", "tx";
 359                 status = "disabled";
 360         };
 361
 362         uartb: serial@70006040 {
 363                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 364                 reg = <0x0 0x70006040 0x0 0x40>;
 365                 reg-shift = <2>;
 366                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 368                 resets = <&tegra_car 7>;
 369                 reset-names = "serial";
 370                 dmas = <&apbdma 9>, <&apbdma 9>;
 371                 dma-names = "rx", "tx";
 372                 status = "disabled";
 373         };
 374
 375         uartc: serial@70006200 {
 376                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 377                 reg = <0x0 0x70006200 0x0 0x40>;
 378                 reg-shift = <2>;
 379                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 381                 resets = <&tegra_car 55>;
 382                 reset-names = "serial";
 383                 dmas = <&apbdma 10>, <&apbdma 10>;
 384                 dma-names = "rx", "tx";
 385                 status = "disabled";
 386         };
 387
 388         uartd: serial@70006300 {
 389                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 390                 reg = <0x0 0x70006300 0x0 0x40>;
 391                 reg-shift = <2>;
 392                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 394                 resets = <&tegra_car 65>;
 395                 reset-names = "serial";
 396                 dmas = <&apbdma 19>, <&apbdma 19>;
 397                 dma-names = "rx", "tx";
 398                 status = "disabled";
 399         };
 400
 401         pwm: pwm@7000a000 {
 402                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 403                 reg = <0x0 0x7000a000 0x0 0x100>;
 404                 #pwm-cells = <2>;
 405                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 406                 resets = <&tegra_car 17>;
 407                 reset-names = "pwm";
 408                 status = "disabled";
 409         };
 410
 411         i2c@7000c000 {
 412                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 413                 reg = <0x0 0x7000c000 0x0 0x100>;
 414                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 418                 clock-names = "div-clk";
 419                 resets = <&tegra_car 12>;
 420                 reset-names = "i2c";
 421                 dmas = <&apbdma 21>, <&apbdma 21>;
 422                 dma-names = "rx", "tx";
 423                 status = "disabled";
 424         };
 425
 426         i2c@7000c400 {
 427                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 428                 reg = <0x0 0x7000c400 0x0 0x100>;
 429                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 433                 clock-names = "div-clk";
 434                 resets = <&tegra_car 54>;
 435                 reset-names = "i2c";
 436                 dmas = <&apbdma 22>, <&apbdma 22>;
 437                 dma-names = "rx", "tx";
 438                 status = "disabled";
 439         };
 440
 441         i2c@7000c500 {
 442                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 443                 reg = <0x0 0x7000c500 0x0 0x100>;
 444                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 448                 clock-names = "div-clk";
 449                 resets = <&tegra_car 67>;
 450                 reset-names = "i2c";
 451                 dmas = <&apbdma 23>, <&apbdma 23>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         i2c@7000c700 {
 457                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 458                 reg = <0x0 0x7000c700 0x0 0x100>;
 459                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 463                 clock-names = "div-clk";
 464                 resets = <&tegra_car 103>;
 465                 reset-names = "i2c";
 466                 dmas = <&apbdma 26>, <&apbdma 26>;
 467                 dma-names = "rx", "tx";
 468                 status = "disabled";
 469         };
 470
 471         i2c@7000d000 {
 472                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 473                 reg = <0x0 0x7000d000 0x0 0x100>;
 474                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 478                 clock-names = "div-clk";
 479                 resets = <&tegra_car 47>;
 480                 reset-names = "i2c";
 481                 dmas = <&apbdma 24>, <&apbdma 24>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         i2c@7000d100 {
 487                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 488                 reg = <0x0 0x7000d100 0x0 0x100>;
 489                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 493                 clock-names = "div-clk";
 494                 resets = <&tegra_car 166>;
 495                 reset-names = "i2c";
 496                 dmas = <&apbdma 30>, <&apbdma 30>;
 497                 dma-names = "rx", "tx";
 498                 status = "disabled";
 499         };
 500
 501         spi@7000d400 {
 502                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 503                 reg = <0x0 0x7000d400 0x0 0x200>;
 504                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 508                 clock-names = "spi";
 509                 resets = <&tegra_car 41>;
 510                 reset-names = "spi";
 511                 dmas = <&apbdma 15>, <&apbdma 15>;
 512                 dma-names = "rx", "tx";
 513                 status = "disabled";
 514         };
 515
 516         spi@7000d600 {
 517                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 518                 reg = <0x0 0x7000d600 0x0 0x200>;
 519                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 523                 clock-names = "spi";
 524                 resets = <&tegra_car 44>;
 525                 reset-names = "spi";
 526                 dmas = <&apbdma 16>, <&apbdma 16>;
 527                 dma-names = "rx", "tx";
 528                 status = "disabled";
 529         };
 530
 531         spi@7000d800 {
 532                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 533                 reg = <0x0 0x7000d800 0x0 0x200>;
 534                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 538                 clock-names = "spi";
 539                 resets = <&tegra_car 46>;
 540                 reset-names = "spi";
 541                 dmas = <&apbdma 17>, <&apbdma 17>;
 542                 dma-names = "rx", "tx";
 543                 status = "disabled";
 544         };
 545
 546         spi@7000da00 {
 547                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 548                 reg = <0x0 0x7000da00 0x0 0x200>;
 549                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 553                 clock-names = "spi";
 554                 resets = <&tegra_car 68>;
 555                 reset-names = "spi";
 556                 dmas = <&apbdma 18>, <&apbdma 18>;
 557                 dma-names = "rx", "tx";
 558                 status = "disabled";
 559         };
 560
 561         spi@7000dc00 {
 562                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 563                 reg = <0x0 0x7000dc00 0x0 0x200>;
 564                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 568                 clock-names = "spi";
 569                 resets = <&tegra_car 104>;
 570                 reset-names = "spi";
 571                 dmas = <&apbdma 27>, <&apbdma 27>;
 572                 dma-names = "rx", "tx";
 573                 status = "disabled";
 574         };
 575
 576         spi@7000de00 {
 577                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 578                 reg = <0x0 0x7000de00 0x0 0x200>;
 579                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 583                 clock-names = "spi";
 584                 resets = <&tegra_car 105>;
 585                 reset-names = "spi";
 586                 dmas = <&apbdma 28>, <&apbdma 28>;
 587                 dma-names = "rx", "tx";
 588                 status = "disabled";
 589         };
 590
 591         rtc@7000e000 {
 592                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 593                 reg = <0x0 0x7000e000 0x0 0x100>;
 594                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 595                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 596         };
 597
 598         pmc@7000e400 {
 599                 compatible = "nvidia,tegra124-pmc";
 600                 reg = <0x0 0x7000e400 0x0 0x400>;
 601                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 602                 clock-names = "pclk", "clk32k_in";
 603         };
 604
 605         fuse@7000f800 {
 606                 compatible = "nvidia,tegra124-efuse";
 607                 reg = <0x0 0x7000f800 0x0 0x400>;
 608                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 609                 clock-names = "fuse";
 610                 resets = <&tegra_car 39>;
 611                 reset-names = "fuse";
 612         };
 613
 614         mc: memory-controller@70019000 {
 615                 compatible = "nvidia,tegra124-mc";
 616                 reg = <0x0 0x70019000 0x0 0x1000>;
 617                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 618                 clock-names = "mc";
 619
 620                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 621
 622                 #iommu-cells = <1>;
 623         };
 624
 625         emc: emc@7001b000 {
 626                 compatible = "nvidia,tegra124-emc";
 627                 reg = <0x0 0x7001b000 0x0 0x1000>;
 628
 629                 nvidia,memory-controller = <&mc>;
 630         };
 631
 632         sata@70020000 {
 633                 compatible = "nvidia,tegra124-ahci";
 634                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 635                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 636                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 638                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 639                          <&tegra_car TEGRA124_CLK_CML1>,
 640                          <&tegra_car TEGRA124_CLK_PLL_E>;
 641                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 642                 resets = <&tegra_car 124>,
 643                          <&tegra_car 123>,
 644                          <&tegra_car 129>;
 645                 reset-names = "sata", "sata-oob", "sata-cold";
 646                 status = "disabled";
 647         };
 648
 649         hda@70030000 {
 650                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 651                 reg = <0x0 0x70030000 0x0 0x10000>;
 652                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 654                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 655                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 656                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 657                 resets = <&tegra_car 125>, /* hda */
 658                          <&tegra_car 128>, /* hda2hdmi */
 659                          <&tegra_car 111>; /* hda2codec_2x */
 660                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 661                 status = "disabled";
 662         };
 663
 664         usb@70090000 {
 665                 compatible = "nvidia,tegra124-xusb";
 666                 reg = <0x0 0x70090000 0x0 0x8000>,
 667                       <0x0 0x70098000 0x0 0x1000>,
 668                       <0x0 0x70099000 0x0 0x1000>;
 669                 reg-names = "hcd", "fpci", "ipfs";
 670
 671                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 672                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 673
 674                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
 675                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
 676                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
 677                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
 678                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
 679                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
 680                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
 681                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
 682                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
 683                          <&tegra_car TEGRA124_CLK_CLK_M>,
 684                          <&tegra_car TEGRA124_CLK_PLL_E>;
 685                 clock-names = "xusb_host", "xusb_host_src",
 686                               "xusb_falcon_src", "xusb_ss",
 687                               "xusb_ss_div2", "xusb_ss_src",
 688                               "xusb_hs_src", "xusb_fs_src",
 689                               "pll_u_480m", "clk_m", "pll_e";
 690                 resets = <&tegra_car 89>, <&tegra_car 156>,
 691                          <&tegra_car 143>;
 692                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 693
 694                 nvidia,xusb-padctl = <&padctl>;
 695
 696                 status = "disabled";
 697         };
 698
 699         padctl: padctl@7009f000 {
 700                 compatible = "nvidia,tegra124-xusb-padctl";
 701                 reg = <0x0 0x7009f000 0x0 0x1000>;
 702                 resets = <&tegra_car 142>;
 703                 reset-names = "padctl";
 704
 705                 pads {
 706                         usb2 {
 707                                 status = "disabled";
 708
 709                                 lanes {
 710                                         usb2-0 {
 711                                                 status = "disabled";
 712                                                 #phy-cells = <0>;
 713                                         };
 714
 715                                         usb2-1 {
 716                                                 status = "disabled";
 717                                                 #phy-cells = <0>;
 718                                         };
 719
 720                                         usb2-2 {
 721                                                 status = "disabled";
 722                                                 #phy-cells = <0>;
 723                                         };
 724                                 };
 725                         };
 726
 727                         ulpi {
 728                                 status = "disabled";
 729
 730                                 lanes {
 731                                         ulpi-0 {
 732                                                 status = "disabled";
 733                                                 #phy-cells = <0>;
 734                                         };
 735                                 };
 736                         };
 737
 738                         hsic {
 739                                 status = "disabled";
 740
 741                                 lanes {
 742                                         hsic-0 {
 743                                                 status = "disabled";
 744                                                 #phy-cells = <0>;
 745                                         };
 746
 747                                         hsic-1 {
 748                                                 status = "disabled";
 749                                                 #phy-cells = <0>;
 750                                         };
 751                                 };
 752                         };
 753
 754                         pcie {
 755                                 status = "disabled";
 756
 757                                 lanes {
 758                                         pcie-0 {
 759                                                 status = "disabled";
 760                                                 #phy-cells = <0>;
 761                                         };
 762
 763                                         pcie-1 {
 764                                                 status = "disabled";
 765                                                 #phy-cells = <0>;
 766                                         };
 767
 768                                         pcie-2 {
 769                                                 status = "disabled";
 770                                                 #phy-cells = <0>;
 771                                         };
 772
 773                                         pcie-3 {
 774                                                 status = "disabled";
 775                                                 #phy-cells = <0>;
 776                                         };
 777
 778                                         pcie-4 {
 779                                                 status = "disabled";
 780                                                 #phy-cells = <0>;
 781                                         };
 782                                 };
 783                         };
 784
 785                         sata {
 786                                 status = "disabled";
 787
 788                                 lanes {
 789                                         sata-0 {
 790                                                 status = "disabled";
 791                                                 #phy-cells = <0>;
 792                                         };
 793                                 };
 794                         };
 795                 };
 796
 797                 ports {
 798                         usb2-0 {
 799                                 status = "disabled";
 800                         };
 801
 802                         usb2-1 {
 803                                 status = "disabled";
 804                         };
 805
 806                         usb2-2 {
 807                                 status = "disabled";
 808                         };
 809
 810                         ulpi-0 {
 811                                 status = "disabled";
 812                         };
 813
 814                         hsic-0 {
 815                                 status = "disabled";
 816                         };
 817
 818                         hsic-1 {
 819                                 status = "disabled";
 820                         };
 821
 822                         usb3-0 {
 823                                 status = "disabled";
 824                         };
 825
 826                         usb3-1 {
 827                                 status = "disabled";
 828                         };
 829                 };
 830         };
 831
 832         sdhci@700b0000 {
 833                 compatible = "nvidia,tegra124-sdhci";
 834                 reg = <0x0 0x700b0000 0x0 0x200>;
 835                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 837                 resets = <&tegra_car 14>;
 838                 reset-names = "sdhci";
 839                 status = "disabled";
 840         };
 841
 842         sdhci@700b0200 {
 843                 compatible = "nvidia,tegra124-sdhci";
 844                 reg = <0x0 0x700b0200 0x0 0x200>;
 845                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 846                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 847                 resets = <&tegra_car 9>;
 848                 reset-names = "sdhci";
 849                 status = "disabled";
 850         };
 851
 852         sdhci@700b0400 {
 853                 compatible = "nvidia,tegra124-sdhci";
 854                 reg = <0x0 0x700b0400 0x0 0x200>;
 855                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 856                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 857                 resets = <&tegra_car 69>;
 858                 reset-names = "sdhci";
 859                 status = "disabled";
 860         };
 861
 862         sdhci@700b0600 {
 863                 compatible = "nvidia,tegra124-sdhci";
 864                 reg = <0x0 0x700b0600 0x0 0x200>;
 865                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 866                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 867                 resets = <&tegra_car 15>;
 868                 reset-names = "sdhci";
 869                 status = "disabled";
 870         };
 871
 872         cec@70015000 {
 873                 compatible = "nvidia,tegra124-cec";
 874                 reg = <0x0 0x70015000 0x0 0x00001000>;
 875                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&tegra_car TEGRA124_CLK_CEC>;
 877                 clock-names = "cec";
 878                 status = "disabled";
 879                 hdmi-phandle = <&hdmi>;
 880         };
 881
 882         soctherm: thermal-sensor@700e2000 {
 883                 compatible = "nvidia,tegra124-soctherm";
 884                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
 885                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
 886                 reg-names = "soctherm-reg", "car-reg";
 887                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 889                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 890                 clock-names = "tsensor", "soctherm";
 891                 resets = <&tegra_car 78>;
 892                 reset-names = "soctherm";
 893                 #thermal-sensor-cells = <1>;
 894
 895                 throttle-cfgs {
 896                         throttle_heavy: heavy {
 897                                 nvidia,priority = <100>;
 898                                 nvidia,cpu-throt-percent = <85>;
 899
 900                                 #cooling-cells = <2>;
 901                         };
 902                 };
 903         };
 904
 905         dfll: clock@70110000 {
 906                 compatible = "nvidia,tegra124-dfll";
 907                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 908                       <0 0x70110000 0 0x100>, /* I2C output control */
 909                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 910                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 911                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 913                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 914                          <&tegra_car TEGRA124_CLK_I2C5>;
 915                 clock-names = "soc", "ref", "i2c";
 916                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 917                 reset-names = "dvco";
 918                 #clock-cells = <0>;
 919                 clock-output-names = "dfllCPU_out";
 920                 nvidia,sample-rate = <12500>;
 921                 nvidia,droop-ctrl = <0x00000f00>;
 922                 nvidia,force-mode = <1>;
 923                 nvidia,cf = <10>;
 924                 nvidia,ci = <0>;
 925                 nvidia,cg = <2>;
 926                 status = "disabled";
 927         };
 928
 929         ahub@70300000 {
 930                 compatible = "nvidia,tegra124-ahub";
 931                 reg = <0x0 0x70300000 0x0 0x200>,
 932                       <0x0 0x70300800 0x0 0x800>,
 933                       <0x0 0x70300200 0x0 0x600>;
 934                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 935                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 936                          <&tegra_car TEGRA124_CLK_APBIF>;
 937                 clock-names = "d_audio", "apbif";
 938                 resets = <&tegra_car 106>, /* d_audio */
 939                          <&tegra_car 107>, /* apbif */
 940                          <&tegra_car 30>,  /* i2s0 */
 941                          <&tegra_car 11>,  /* i2s1 */
 942                          <&tegra_car 18>,  /* i2s2 */
 943                          <&tegra_car 101>, /* i2s3 */
 944                          <&tegra_car 102>, /* i2s4 */
 945                          <&tegra_car 108>, /* dam0 */
 946                          <&tegra_car 109>, /* dam1 */
 947                          <&tegra_car 110>, /* dam2 */
 948                          <&tegra_car 10>,  /* spdif */
 949                          <&tegra_car 153>, /* amx */
 950                          <&tegra_car 185>, /* amx1 */
 951                          <&tegra_car 154>, /* adx */
 952                          <&tegra_car 180>, /* adx1 */
 953                          <&tegra_car 186>, /* afc0 */
 954                          <&tegra_car 187>, /* afc1 */
 955                          <&tegra_car 188>, /* afc2 */
 956                          <&tegra_car 189>, /* afc3 */
 957                          <&tegra_car 190>, /* afc4 */
 958                          <&tegra_car 191>; /* afc5 */
 959                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 960                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 961                               "spdif", "amx", "amx1", "adx", "adx1",
 962                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 963                 dmas = <&apbdma 1>, <&apbdma 1>,
 964                        <&apbdma 2>, <&apbdma 2>,
 965                        <&apbdma 3>, <&apbdma 3>,
 966                        <&apbdma 4>, <&apbdma 4>,
 967                        <&apbdma 6>, <&apbdma 6>,
 968                        <&apbdma 7>, <&apbdma 7>,
 969                        <&apbdma 12>, <&apbdma 12>,
 970                        <&apbdma 13>, <&apbdma 13>,
 971                        <&apbdma 14>, <&apbdma 14>,
 972                        <&apbdma 29>, <&apbdma 29>;
 973                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 974                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 975                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 976                             "rx9", "tx9";
 977                 ranges;
 978                 #address-cells = <2>;
 979                 #size-cells = <2>;
 980
 981                 tegra_i2s0: i2s@70301000 {
 982                         compatible = "nvidia,tegra124-i2s";
 983                         reg = <0x0 0x70301000 0x0 0x100>;
 984                         nvidia,ahub-cif-ids = <4 4>;
 985                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 986                         resets = <&tegra_car 30>;
 987                         reset-names = "i2s";
 988                         status = "disabled";
 989                 };
 990
 991                 tegra_i2s1: i2s@70301100 {
 992                         compatible = "nvidia,tegra124-i2s";
 993                         reg = <0x0 0x70301100 0x0 0x100>;
 994                         nvidia,ahub-cif-ids = <5 5>;
 995                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 996                         resets = <&tegra_car 11>;
 997                         reset-names = "i2s";
 998                         status = "disabled";
 999                 };
1000
1001                 tegra_i2s2: i2s@70301200 {
1002                         compatible = "nvidia,tegra124-i2s";
1003                         reg = <0x0 0x70301200 0x0 0x100>;
1004                         nvidia,ahub-cif-ids = <6 6>;
1005                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1006                         resets = <&tegra_car 18>;
1007                         reset-names = "i2s";
1008                         status = "disabled";
1009                 };
1010
1011                 tegra_i2s3: i2s@70301300 {
1012                         compatible = "nvidia,tegra124-i2s";
1013                         reg = <0x0 0x70301300 0x0 0x100>;
1014                         nvidia,ahub-cif-ids = <7 7>;
1015                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1016                         resets = <&tegra_car 101>;
1017                         reset-names = "i2s";
1018                         status = "disabled";
1019                 };
1020
1021                 tegra_i2s4: i2s@70301400 {
1022                         compatible = "nvidia,tegra124-i2s";
1023                         reg = <0x0 0x70301400 0x0 0x100>;
1024                         nvidia,ahub-cif-ids = <8 8>;
1025                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1026                         resets = <&tegra_car 102>;
1027                         reset-names = "i2s";
1028                         status = "disabled";
1029                 };
1030         };
1031
1032         usb@7d000000 {
1033                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1034                 reg = <0x0 0x7d000000 0x0 0x4000>;
1035                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1036                 phy_type = "utmi";
1037                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1038                 resets = <&tegra_car 22>;
1039                 reset-names = "usb";
1040                 nvidia,phy = <&phy1>;
1041                 status = "disabled";
1042         };
1043
1044         phy1: usb-phy@7d000000 {
1045                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1046                 reg = <0x0 0x7d000000 0x0 0x4000>,
1047                       <0x0 0x7d000000 0x0 0x4000>;
1048                 phy_type = "utmi";
1049                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1050                          <&tegra_car TEGRA124_CLK_PLL_U>,
1051                          <&tegra_car TEGRA124_CLK_USBD>;
1052                 clock-names = "reg", "pll_u", "utmi-pads";
1053                 resets = <&tegra_car 22>, <&tegra_car 22>;
1054                 reset-names = "usb", "utmi-pads";
1055                 nvidia,hssync-start-delay = <0>;
1056                 nvidia,idle-wait-delay = <17>;
1057                 nvidia,elastic-limit = <16>;
1058                 nvidia,term-range-adj = <6>;
1059                 nvidia,xcvr-setup = <9>;
1060                 nvidia,xcvr-lsfslew = <0>;
1061                 nvidia,xcvr-lsrslew = <3>;
1062                 nvidia,hssquelch-level = <2>;
1063                 nvidia,hsdiscon-level = <5>;
1064                 nvidia,xcvr-hsslew = <12>;
1065                 nvidia,has-utmi-pad-registers;
1066                 status = "disabled";
1067         };
1068
1069         usb@7d004000 {
1070                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1071                 reg = <0x0 0x7d004000 0x0 0x4000>;
1072                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1073                 phy_type = "utmi";
1074                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1075                 resets = <&tegra_car 58>;
1076                 reset-names = "usb";
1077                 nvidia,phy = <&phy2>;
1078                 status = "disabled";
1079         };
1080
1081         phy2: usb-phy@7d004000 {
1082                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1083                 reg = <0x0 0x7d004000 0x0 0x4000>,
1084                       <0x0 0x7d000000 0x0 0x4000>;
1085                 phy_type = "utmi";
1086                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1087                          <&tegra_car TEGRA124_CLK_PLL_U>,
1088                          <&tegra_car TEGRA124_CLK_USBD>;
1089                 clock-names = "reg", "pll_u", "utmi-pads";
1090                 resets = <&tegra_car 58>, <&tegra_car 22>;
1091                 reset-names = "usb", "utmi-pads";
1092                 nvidia,hssync-start-delay = <0>;
1093                 nvidia,idle-wait-delay = <17>;
1094                 nvidia,elastic-limit = <16>;
1095                 nvidia,term-range-adj = <6>;
1096                 nvidia,xcvr-setup = <9>;
1097                 nvidia,xcvr-lsfslew = <0>;
1098                 nvidia,xcvr-lsrslew = <3>;
1099                 nvidia,hssquelch-level = <2>;
1100                 nvidia,hsdiscon-level = <5>;
1101                 nvidia,xcvr-hsslew = <12>;
1102                 status = "disabled";
1103         };
1104
1105         usb@7d008000 {
1106                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1107                 reg = <0x0 0x7d008000 0x0 0x4000>;
1108                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1109                 phy_type = "utmi";
1110                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1111                 resets = <&tegra_car 59>;
1112                 reset-names = "usb";
1113                 nvidia,phy = <&phy3>;
1114                 status = "disabled";
1115         };
1116
1117         phy3: usb-phy@7d008000 {
1118                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1119                 reg = <0x0 0x7d008000 0x0 0x4000>,
1120                       <0x0 0x7d000000 0x0 0x4000>;
1121                 phy_type = "utmi";
1122                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1123                          <&tegra_car TEGRA124_CLK_PLL_U>,
1124                          <&tegra_car TEGRA124_CLK_USBD>;
1125                 clock-names = "reg", "pll_u", "utmi-pads";
1126                 resets = <&tegra_car 59>, <&tegra_car 22>;
1127                 reset-names = "usb", "utmi-pads";
1128                 nvidia,hssync-start-delay = <0>;
1129                 nvidia,idle-wait-delay = <17>;
1130                 nvidia,elastic-limit = <16>;
1131                 nvidia,term-range-adj = <6>;
1132                 nvidia,xcvr-setup = <9>;
1133                 nvidia,xcvr-lsfslew = <0>;
1134                 nvidia,xcvr-lsrslew = <3>;
1135                 nvidia,hssquelch-level = <2>;
1136                 nvidia,hsdiscon-level = <5>;
1137                 nvidia,xcvr-hsslew = <12>;
1138                 status = "disabled";
1139         };
1140
1141         cpus {
1142                 #address-cells = <1>;
1143                 #size-cells = <0>;
1144
1145                 cpu@0 {
1146                         device_type = "cpu";
1147                         compatible = "arm,cortex-a15";
1148                         reg = <0>;
1149
1150                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1151                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1152                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1153                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1154                                  <&dfll>;
1155                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1156                         /* FIXME: what's the actual transition time? */
1157                         clock-latency = <300000>;
1158                 };
1159
1160                 cpu@1 {
1161                         device_type = "cpu";
1162                         compatible = "arm,cortex-a15";
1163                         reg = <1>;
1164                 };
1165
1166                 cpu@2 {
1167                         device_type = "cpu";
1168                         compatible = "arm,cortex-a15";
1169                         reg = <2>;
1170                 };
1171
1172                 cpu@3 {
1173                         device_type = "cpu";
1174                         compatible = "arm,cortex-a15";
1175                         reg = <3>;
1176                 };
1177         };
1178
1179         pmu {
1180                 compatible = "arm,cortex-a15-pmu";
1181                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1182                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1183                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1184                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-affinity = <&{/cpus/cpu@0}>,
1186                                      <&{/cpus/cpu@1}>,
1187                                      <&{/cpus/cpu@2}>,
1188                                      <&{/cpus/cpu@3}>;
1189         };
1190
1191         thermal-zones {
1192                 cpu {
1193                         polling-delay-passive = <1000>;
1194                         polling-delay = <1000>;
1195
1196                         thermal-sensors =
1197                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1198
1199                         trips {
1200                                 cpu-shutdown-trip {
1201                                         temperature = <103000>;
1202                                         hysteresis = <0>;
1203                                         type = "critical";
1204                                 };
1205                                 cpu_throttle_trip: throttle-trip {
1206                                         temperature = <100000>;
1207                                         hysteresis = <1000>;
1208                                         type = "hot";
1209                                 };
1210                         };
1211
1212                         cooling-maps {
1213                                 map0 {
1214                                         trip = <&cpu_throttle_trip>;
1215                                         cooling-device = <&throttle_heavy 1 1>;
1216                                 };
1217                         };
1218                 };
1219
1220                 mem {
1221                         polling-delay-passive = <1000>;
1222                         polling-delay = <1000>;
1223
1224                         thermal-sensors =
1225                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1226
1227                         trips {
1228                                 mem-shutdown-trip {
1229                                         temperature = <103000>;
1230                                         hysteresis = <0>;
1231                                         type = "critical";
1232                                 };
1233                         };
1234
1235                         cooling-maps {
1236                                 /*
1237                                  * There are currently no cooling maps,
1238                                  * because there are no cooling devices.
1239                                  */
1240                         };
1241                 };
1242
1243                 gpu {
1244                         polling-delay-passive = <1000>;
1245                         polling-delay = <1000>;
1246
1247                         thermal-sensors =
1248                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1249
1250                         trips {
1251                                 gpu-shutdown-trip {
1252                                         temperature = <101000>;
1253                                         hysteresis = <0>;
1254                                         type = "critical";
1255                                 };
1256                                 gpu_throttle_trip: throttle-trip {
1257                                         temperature = <99000>;
1258                                         hysteresis = <1000>;
1259                                         type = "hot";
1260                                 };
1261                         };
1262
1263                         cooling-maps {
1264                                 map0 {
1265                                         trip = <&gpu_throttle_trip>;
1266                                         cooling-device = <&throttle_heavy 1 1>;
1267                                 };
1268                         };
1269                 };
1270
1271                 pllx {
1272                         polling-delay-passive = <1000>;
1273                         polling-delay = <1000>;
1274
1275                         thermal-sensors =
1276                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1277
1278                         trips {
1279                                 pllx-shutdown-trip {
1280                                         temperature = <103000>;
1281                                         hysteresis = <0>;
1282                                         type = "critical";
1283                                 };
1284                         };
1285
1286                         cooling-maps {
1287                                 /*
1288                                  * There are currently no cooling maps,
1289                                  * because there are no cooling devices.
1290                                  */
1291                         };
1292                 };
1293         };
1294
1295         timer {
1296                 compatible = "arm,armv7-timer";
1297                 interrupts = <GIC_PPI 13
1298                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1299                              <GIC_PPI 14
1300                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1301                              <GIC_PPI 11
1302                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1303                              <GIC_PPI 10
1304                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1305                 interrupt-parent = <&gic>;
1306         };
1307 };