1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * Motherboard Express uATX
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
11 * Technical Reference Manual)
13 * WARNING! The hardware described in this file is independent from the
14 * original variant (vexpress-v2m.dtsi), but there is a strong
15 * correspondence between the two configurations.
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m.dtsi!
26 arm,vexpress,site = <0>;
27 arm,v2m-memory-map = "rs1";
28 compatible = "arm,vexpress,v2m-p1", "simple-bus";
29 #address-cells = <2>; /* SMB chipselect number and offset */
31 #interrupt-cells = <1>;
34 nor_flash: flash@0,00000000 {
35 compatible = "arm,vexpress-flash", "cfi-flash";
36 reg = <0 0x00000000 0x04000000>,
37 <4 0x00000000 0x04000000>;
40 compatible = "arm,arm-firmware-suite";
45 compatible = "arm,vexpress-psram", "mtd-ram";
46 reg = <1 0x00000000 0x02000000>;
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
58 vdd33a-supply = <&v2m_fixed_3v3>;
59 vddvario-supply = <&v2m_fixed_3v3>;
63 compatible = "nxp,usb-isp1761";
64 reg = <2 0x03000000 0x20000>;
70 compatible = "simple-bus";
73 ranges = <0 3 0 0x200000>;
75 v2m_sysreg: sysreg@10000 {
76 compatible = "arm,vexpress-sysreg";
77 reg = <0x010000 0x1000>;
80 ranges = <0 0x10000 0x1000>;
82 v2m_led_gpios: gpio@8 {
83 compatible = "arm,vexpress-sysreg,sys_led";
89 v2m_mmc_gpios: gpio@48 {
90 compatible = "arm,vexpress-sysreg,sys_mci";
96 v2m_flash_gpios: gpio@4c {
97 compatible = "arm,vexpress-sysreg,sys_flash";
104 v2m_sysctl: sysctl@20000 {
105 compatible = "arm,sp810", "arm,primecell";
106 reg = <0x020000 0x1000>;
107 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
108 clock-names = "refclk", "timclk", "apb_pclk";
110 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
111 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
112 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
116 v2m_i2c_pcie: i2c@30000 {
117 compatible = "arm,versatile-i2c";
118 reg = <0x030000 0x1000>;
120 #address-cells = <1>;
124 compatible = "idt,89hpes32h8";
130 compatible = "arm,pl041", "arm,primecell";
131 reg = <0x040000 0x1000>;
134 clock-names = "apb_pclk";
138 compatible = "arm,pl180", "arm,primecell";
139 reg = <0x050000 0x1000>;
140 interrupts = <9>, <10>;
141 cd-gpios = <&v2m_mmc_gpios 0 0>;
142 wp-gpios = <&v2m_mmc_gpios 1 0>;
143 max-frequency = <12000000>;
144 vmmc-supply = <&v2m_fixed_3v3>;
145 clocks = <&v2m_clk24mhz>, <&smbclk>;
146 clock-names = "mclk", "apb_pclk";
150 compatible = "arm,pl050", "arm,primecell";
151 reg = <0x060000 0x1000>;
153 clocks = <&v2m_clk24mhz>, <&smbclk>;
154 clock-names = "KMIREFCLK", "apb_pclk";
158 compatible = "arm,pl050", "arm,primecell";
159 reg = <0x070000 0x1000>;
161 clocks = <&v2m_clk24mhz>, <&smbclk>;
162 clock-names = "KMIREFCLK", "apb_pclk";
165 v2m_serial0: uart@90000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x090000 0x1000>;
169 clocks = <&v2m_oscclk2>, <&smbclk>;
170 clock-names = "uartclk", "apb_pclk";
173 v2m_serial1: uart@a0000 {
174 compatible = "arm,pl011", "arm,primecell";
175 reg = <0x0a0000 0x1000>;
177 clocks = <&v2m_oscclk2>, <&smbclk>;
178 clock-names = "uartclk", "apb_pclk";
181 v2m_serial2: uart@b0000 {
182 compatible = "arm,pl011", "arm,primecell";
183 reg = <0x0b0000 0x1000>;
185 clocks = <&v2m_oscclk2>, <&smbclk>;
186 clock-names = "uartclk", "apb_pclk";
189 v2m_serial3: uart@c0000 {
190 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x0c0000 0x1000>;
193 clocks = <&v2m_oscclk2>, <&smbclk>;
194 clock-names = "uartclk", "apb_pclk";
198 compatible = "arm,sp805", "arm,primecell";
199 reg = <0x0f0000 0x1000>;
201 clocks = <&v2m_refclk32khz>, <&smbclk>;
202 clock-names = "wdogclk", "apb_pclk";
205 v2m_timer01: timer@110000 {
206 compatible = "arm,sp804", "arm,primecell";
207 reg = <0x110000 0x1000>;
209 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
210 clock-names = "timclken1", "timclken2", "apb_pclk";
213 v2m_timer23: timer@120000 {
214 compatible = "arm,sp804", "arm,primecell";
215 reg = <0x120000 0x1000>;
217 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
218 clock-names = "timclken1", "timclken2", "apb_pclk";
222 v2m_i2c_dvi: i2c@160000 {
223 compatible = "arm,versatile-i2c";
224 reg = <0x160000 0x1000>;
225 #address-cells = <1>;
229 compatible = "sil,sii9022-tpi", "sil,sii9022";
233 #address-cells = <1>;
238 dvi_bridge_in: endpoint {
239 remote-endpoint = <&clcd_pads>;
246 compatible = "sil,sii9022-cpi", "sil,sii9022";
252 compatible = "arm,pl031", "arm,primecell";
253 reg = <0x170000 0x1000>;
256 clock-names = "apb_pclk";
259 compact-flash@1a0000 {
260 compatible = "arm,vexpress-cf", "ata-generic";
261 reg = <0x1a0000 0x100
267 compatible = "arm,pl111", "arm,primecell";
268 reg = <0x1f0000 0x1000>;
269 interrupt-names = "combined";
271 clocks = <&v2m_oscclk1>, <&smbclk>;
272 clock-names = "clcdclk", "apb_pclk";
273 /* 800x600 16bpp @36MHz works fine */
274 max-memory-bandwidth = <54000000>;
275 memory-region = <&vram>;
278 clcd_pads: endpoint {
279 remote-endpoint = <&dvi_bridge_in>;
280 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
286 v2m_fixed_3v3: fixed-regulator-0 {
287 compatible = "regulator-fixed";
288 regulator-name = "3V3";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
294 v2m_clk24mhz: clk24mhz {
295 compatible = "fixed-clock";
297 clock-frequency = <24000000>;
298 clock-output-names = "v2m:clk24mhz";
301 v2m_refclk1mhz: refclk1mhz {
302 compatible = "fixed-clock";
304 clock-frequency = <1000000>;
305 clock-output-names = "v2m:refclk1mhz";
308 v2m_refclk32khz: refclk32khz {
309 compatible = "fixed-clock";
311 clock-frequency = <32768>;
312 clock-output-names = "v2m:refclk32khz";
316 compatible = "gpio-leds";
319 label = "v2m:green:user1";
320 gpios = <&v2m_led_gpios 0 0>;
321 linux,default-trigger = "heartbeat";
325 label = "v2m:green:user2";
326 gpios = <&v2m_led_gpios 1 0>;
327 linux,default-trigger = "mmc0";
331 label = "v2m:green:user3";
332 gpios = <&v2m_led_gpios 2 0>;
333 linux,default-trigger = "cpu0";
337 label = "v2m:green:user4";
338 gpios = <&v2m_led_gpios 3 0>;
339 linux,default-trigger = "cpu1";
343 label = "v2m:green:user5";
344 gpios = <&v2m_led_gpios 4 0>;
345 linux,default-trigger = "cpu2";
349 label = "v2m:green:user6";
350 gpios = <&v2m_led_gpios 5 0>;
351 linux,default-trigger = "cpu3";
355 label = "v2m:green:user7";
356 gpios = <&v2m_led_gpios 6 0>;
357 linux,default-trigger = "cpu4";
361 label = "v2m:green:user8";
362 gpios = <&v2m_led_gpios 7 0>;
363 linux,default-trigger = "cpu5";
368 compatible = "arm,vexpress,config-bus";
369 arm,vexpress,config-bridge = <&v2m_sysreg>;
372 /* MCC static memory clock */
373 compatible = "arm,vexpress-osc";
374 arm,vexpress-sysreg,func = <1 0>;
375 freq-range = <25000000 60000000>;
377 clock-output-names = "v2m:oscclk0";
380 v2m_oscclk1: oscclk1 {
382 compatible = "arm,vexpress-osc";
383 arm,vexpress-sysreg,func = <1 1>;
384 freq-range = <23750000 65000000>;
386 clock-output-names = "v2m:oscclk1";
389 v2m_oscclk2: oscclk2 {
390 /* IO FPGA peripheral clock */
391 compatible = "arm,vexpress-osc";
392 arm,vexpress-sysreg,func = <1 2>;
393 freq-range = <24000000 24000000>;
395 clock-output-names = "v2m:oscclk2";
399 /* Logic level voltage */
400 compatible = "arm,vexpress-volt";
401 arm,vexpress-sysreg,func = <2 0>;
402 regulator-name = "VIO";
408 /* MCC internal operating temperature */
409 compatible = "arm,vexpress-temp";
410 arm,vexpress-sysreg,func = <4 0>;
415 compatible = "arm,vexpress-reset";
416 arm,vexpress-sysreg,func = <5 0>;
420 compatible = "arm,vexpress-muxfpga";
421 arm,vexpress-sysreg,func = <7 0>;
425 compatible = "arm,vexpress-shutdown";
426 arm,vexpress-sysreg,func = <8 0>;
430 compatible = "arm,vexpress-reboot";
431 arm,vexpress-sysreg,func = <9 0>;
435 compatible = "arm,vexpress-dvimode";
436 arm,vexpress-sysreg,func = <11 0>;