arch/arm/mach-imx/common.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6
   7 #ifndef __ASM_ARCH_MXC_COMMON_H__
   8 #define __ASM_ARCH_MXC_COMMON_H__
   9
  10 #include <linux/reboot.h>
  11
  12 struct irq_data;
  13 struct platform_device;
  14 struct pt_regs;
  15 struct clk;
  16 struct device_node;
  17 enum mxc_cpu_pwr_mode;
  18 struct of_device_id;
  19
  20 void mx21_map_io(void);
  21 void mx27_map_io(void);
  22 void mx31_map_io(void);
  23 void mx35_map_io(void);
  24 void imx21_init_early(void);
  25 void imx27_init_early(void);
  26 void imx31_init_early(void);
  27 void imx35_init_early(void);
  28 void mxc_init_irq(void __iomem *);
  29 void mx21_init_irq(void);
  30 void mx27_init_irq(void);
  31 void mx31_init_irq(void);
  32 void mx35_init_irq(void);
  33 void imx21_soc_init(void);
  34 void imx27_soc_init(void);
  35 void imx31_soc_init(void);
  36 void imx35_soc_init(void);
  37 int mx21_clocks_init(unsigned long lref, unsigned long fref);
  38 int mx27_clocks_init(unsigned long fref);
  39 int mx31_clocks_init(unsigned long fref);
  40 int mx35_clocks_init(void);
  41 struct platform_device *mxc_register_gpio(char *name, int id,
  42         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
  43 void mxc_set_cpu_type(unsigned int type);
  44 void mxc_restart(enum reboot_mode, const char *);
  45 void mxc_arch_reset_init(void __iomem *);
  46 void imx1_reset_init(void __iomem *);
  47 void imx_set_aips(void __iomem *);
  48 void imx_aips_allow_unprivileged_access(const char *compat);
  49 int mxc_device_init(void);
  50 void imx_set_soc_revision(unsigned int rev);
  51 void imx_init_revision_from_anatop(void);
  52 struct device *imx_soc_device_init(void);
  53 void imx6_enable_rbc(bool enable);
  54 void imx_gpc_check_dt(void);
  55 void imx_gpc_set_arm_power_in_lpm(bool power_off);
  56 void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
  57 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
  58 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
  59 void imx25_pm_init(void);
  60 void imx27_pm_init(void);
  61 void imx5_pmu_init(void);
  62
  63 enum mxc_cpu_pwr_mode {
  64         WAIT_CLOCKED,           /* wfi only */
  65         WAIT_UNCLOCKED,         /* WAIT */
  66         WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
  67         STOP_POWER_ON,          /* just STOP */
  68         STOP_POWER_OFF,         /* STOP + SRPG */
  69 };
  70
  71 enum ulp_cpu_pwr_mode {
  72         ULP_PM_HSRUN,    /* High speed run mode */
  73         ULP_PM_RUN,      /* Run mode */
  74         ULP_PM_WAIT,     /* Wait mode */
  75         ULP_PM_STOP,     /* Stop mode */
  76         ULP_PM_VLPS,     /* Very low power stop mode */
  77         ULP_PM_VLLS,     /* very low leakage stop mode */
  78 };
  79
  80 void imx_enable_cpu(int cpu, bool enable);
  81 void imx_set_cpu_jump(int cpu, void *jump_addr);
  82 u32 imx_get_cpu_arg(int cpu);
  83 void imx_set_cpu_arg(int cpu, u32 arg);
  84 #ifdef CONFIG_SMP
  85 void v7_secondary_startup(void);
  86 void imx_scu_map_io(void);
  87 void imx_smp_prepare(void);
  88 #else
  89 static inline void imx_scu_map_io(void) {}
  90 static inline void imx_smp_prepare(void) {}
  91 #endif
  92 void imx_src_init(void);
  93 void imx_gpc_pre_suspend(bool arm_power_off);
  94 void imx_gpc_post_resume(void);
  95 void imx_gpc_mask_all(void);
  96 void imx_gpc_restore_all(void);
  97 void imx_gpc_hwirq_mask(unsigned int hwirq);
  98 void imx_gpc_hwirq_unmask(unsigned int hwirq);
  99 void imx_anatop_init(void);
 100 void imx_anatop_pre_suspend(void);
 101 void imx_anatop_post_resume(void);
 102 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 103 void imx6_set_int_mem_clk_lpm(bool enable);
 104 void imx6sl_set_wait_clk(bool enter);
 105 int imx_mmdc_get_ddr_type(void);
 106 int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
 107
 108 void imx_cpu_die(unsigned int cpu);
 109 int imx_cpu_kill(unsigned int cpu);
 110
 111 #ifdef CONFIG_SUSPEND
 112 void v7_cpu_resume(void);
 113 void imx53_suspend(void __iomem *ocram_vbase);
 114 extern const u32 imx53_suspend_sz;
 115 void imx6_suspend(void __iomem *ocram_vbase);
 116 #else
 117 static inline void v7_cpu_resume(void) {}
 118 static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 119 static const u32 imx53_suspend_sz;
 120 static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 121 #endif
 122
 123 void imx6_pm_ccm_init(const char *ccm_compat);
 124 void imx6q_pm_init(void);
 125 void imx6dl_pm_init(void);
 126 void imx6sl_pm_init(void);
 127 void imx6sx_pm_init(void);
 128 void imx6ul_pm_init(void);
 129 void imx7ulp_pm_init(void);
 130
 131 #ifdef CONFIG_PM
 132 void imx51_pm_init(void);
 133 void imx53_pm_init(void);
 134 #else
 135 static inline void imx51_pm_init(void) {}
 136 static inline void imx53_pm_init(void) {}
 137 #endif
 138
 139 #ifdef CONFIG_NEON
 140 int mx51_neon_fixup(void);
 141 #else
 142 static inline int mx51_neon_fixup(void) { return 0; }
 143 #endif
 144
 145 #ifdef CONFIG_CACHE_L2X0
 146 void imx_init_l2cache(void);
 147 #else
 148 static inline void imx_init_l2cache(void) {}
 149 #endif
 150
 151 extern const struct smp_operations imx_smp_ops;
 152 extern const struct smp_operations ls1021a_smp_ops;
 153
 154 #endif