arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   4  *
   5  * Copyright (C) 2011 Nokia Corporation
   6  * Paul Walmsley
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/omap-dma.h>
  11
  12 #include "omap_hwmod.h"
  13 #include "omap_hwmod_common_data.h"
  14 #include "cm-regbits-24xx.h"
  15 #include "prm-regbits-24xx.h"
  16 #include "wd_timer.h"
  17
  18 /*
  19  * 'dispc' class
  20  * display controller
  21  */
  22
  23 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  24         .rev_offs       = 0x0000,
  25         .sysc_offs      = 0x0010,
  26         .syss_offs      = 0x0014,
  27         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  28                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  29         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  30                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  31         .sysc_fields    = &omap_hwmod_sysc_type1,
  32 };
  33
  34 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  35         .name   = "dispc",
  36         .sysc   = &omap2_dispc_sysc,
  37 };
  38
  39 /* OMAP2xxx Timer Common */
  40 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  41         .rev_offs       = 0x0000,
  42         .sysc_offs      = 0x0010,
  43         .syss_offs      = 0x0014,
  44         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  45                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  46                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  47         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  48         .sysc_fields    = &omap_hwmod_sysc_type1,
  49 };
  50
  51 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  52         .name   = "timer",
  53         .sysc   = &omap2xxx_timer_sysc,
  54 };
  55
  56 /*
  57  * 'wd_timer' class
  58  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  59  * overflow condition
  60  */
  61
  62 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  63         .rev_offs       = 0x0000,
  64         .sysc_offs      = 0x0010,
  65         .syss_offs      = 0x0014,
  66         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  67                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  68         .sysc_fields    = &omap_hwmod_sysc_type1,
  69 };
  70
  71 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  72         .name           = "wd_timer",
  73         .sysc           = &omap2xxx_wd_timer_sysc,
  74         .pre_shutdown   = &omap2_wd_timer_disable,
  75         .reset          = &omap2_wd_timer_reset,
  76 };
  77
  78 /*
  79  * 'gpio' class
  80  * general purpose io module
  81  */
  82 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  83         .rev_offs       = 0x0000,
  84         .sysc_offs      = 0x0010,
  85         .syss_offs      = 0x0014,
  86         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  87                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  88                            SYSS_HAS_RESET_STATUS),
  89         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  90         .sysc_fields    = &omap_hwmod_sysc_type1,
  91 };
  92
  93 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  94         .name = "gpio",
  95         .sysc = &omap2xxx_gpio_sysc,
  96 };
  97
  98 /* system dma */
  99 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 100         .rev_offs       = 0x0000,
 101         .sysc_offs      = 0x002c,
 102         .syss_offs      = 0x0028,
 103         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 104                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 105                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 106         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 107         .sysc_fields    = &omap_hwmod_sysc_type1,
 108 };
 109
 110 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 111         .name   = "dma",
 112         .sysc   = &omap2xxx_dma_sysc,
 113 };
 114
 115 /*
 116  * 'mailbox' class
 117  * mailbox module allowing communication between the on-chip processors
 118  * using a queued mailbox-interrupt mechanism.
 119  */
 120
 121 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 122         .rev_offs       = 0x000,
 123         .sysc_offs      = 0x010,
 124         .syss_offs      = 0x014,
 125         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 126                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 128         .sysc_fields    = &omap_hwmod_sysc_type1,
 129 };
 130
 131 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 132         .name   = "mailbox",
 133         .sysc   = &omap2xxx_mailbox_sysc,
 134 };
 135
 136 /*
 137  * 'mcspi' class
 138  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 139  * bus
 140  */
 141
 142 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 143         .rev_offs       = 0x0000,
 144         .sysc_offs      = 0x0010,
 145         .syss_offs      = 0x0014,
 146         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 147                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 148                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 149         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 150         .sysc_fields    = &omap_hwmod_sysc_type1,
 151 };
 152
 153 struct omap_hwmod_class omap2xxx_mcspi_class = {
 154         .name   = "mcspi",
 155         .sysc   = &omap2xxx_mcspi_sysc,
 156 };
 157
 158 /*
 159  * 'gpmc' class
 160  * general purpose memory controller
 161  */
 162
 163 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 164         .rev_offs       = 0x0000,
 165         .sysc_offs      = 0x0010,
 166         .syss_offs      = 0x0014,
 167         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 168                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 169         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 170         .sysc_fields    = &omap_hwmod_sysc_type1,
 171 };
 172
 173 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 174         .name   = "gpmc",
 175         .sysc   = &omap2xxx_gpmc_sysc,
 176 };
 177
 178 /*
 179  * IP blocks
 180  */
 181
 182 /* L3 */
 183 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 184         .name           = "l3_main",
 185         .class          = &l3_hwmod_class,
 186         .flags          = HWMOD_NO_IDLEST,
 187 };
 188
 189 /* L4 CORE */
 190 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 191         .name           = "l4_core",
 192         .class          = &l4_hwmod_class,
 193         .flags          = HWMOD_NO_IDLEST,
 194 };
 195
 196 /* L4 WKUP */
 197 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 198         .name           = "l4_wkup",
 199         .class          = &l4_hwmod_class,
 200         .flags          = HWMOD_NO_IDLEST,
 201 };
 202
 203 /* MPU */
 204 struct omap_hwmod omap2xxx_mpu_hwmod = {
 205         .name           = "mpu",
 206         .class          = &mpu_hwmod_class,
 207         .main_clk       = "mpu_ck",
 208 };
 209
 210 /* IVA2 */
 211 struct omap_hwmod omap2xxx_iva_hwmod = {
 212         .name           = "iva",
 213         .class          = &iva_hwmod_class,
 214 };
 215
 216 /* timer1 */
 217 struct omap_hwmod omap2xxx_timer1_hwmod = {
 218         .name           = "timer1",
 219         .main_clk       = "gpt1_fck",
 220         .prcm           = {
 221                 .omap2 = {
 222                         .module_offs = WKUP_MOD,
 223                         .idlest_reg_id = 1,
 224                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 225                 },
 226         },
 227         .class          = &omap2xxx_timer_hwmod_class,
 228         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 229 };
 230
 231 /* timer2 */
 232 struct omap_hwmod omap2xxx_timer2_hwmod = {
 233         .name           = "timer2",
 234         .main_clk       = "gpt2_fck",
 235         .prcm           = {
 236                 .omap2 = {
 237                         .module_offs = CORE_MOD,
 238                         .idlest_reg_id = 1,
 239                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 240                 },
 241         },
 242         .class          = &omap2xxx_timer_hwmod_class,
 243         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 244 };
 245
 246 /* timer3 */
 247 struct omap_hwmod omap2xxx_timer3_hwmod = {
 248         .name           = "timer3",
 249         .main_clk       = "gpt3_fck",
 250         .prcm           = {
 251                 .omap2 = {
 252                         .module_offs = CORE_MOD,
 253                         .idlest_reg_id = 1,
 254                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 255                 },
 256         },
 257         .class          = &omap2xxx_timer_hwmod_class,
 258         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 259 };
 260
 261 /* timer4 */
 262 struct omap_hwmod omap2xxx_timer4_hwmod = {
 263         .name           = "timer4",
 264         .main_clk       = "gpt4_fck",
 265         .prcm           = {
 266                 .omap2 = {
 267                         .module_offs = CORE_MOD,
 268                         .idlest_reg_id = 1,
 269                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 270                 },
 271         },
 272         .class          = &omap2xxx_timer_hwmod_class,
 273         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 274 };
 275
 276 /* timer5 */
 277 struct omap_hwmod omap2xxx_timer5_hwmod = {
 278         .name           = "timer5",
 279         .main_clk       = "gpt5_fck",
 280         .prcm           = {
 281                 .omap2 = {
 282                         .module_offs = CORE_MOD,
 283                         .idlest_reg_id = 1,
 284                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 285                 },
 286         },
 287         .class          = &omap2xxx_timer_hwmod_class,
 288         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 289 };
 290
 291 /* timer6 */
 292 struct omap_hwmod omap2xxx_timer6_hwmod = {
 293         .name           = "timer6",
 294         .main_clk       = "gpt6_fck",
 295         .prcm           = {
 296                 .omap2 = {
 297                         .module_offs = CORE_MOD,
 298                         .idlest_reg_id = 1,
 299                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 300                 },
 301         },
 302         .class          = &omap2xxx_timer_hwmod_class,
 303         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 304 };
 305
 306 /* timer7 */
 307 struct omap_hwmod omap2xxx_timer7_hwmod = {
 308         .name           = "timer7",
 309         .main_clk       = "gpt7_fck",
 310         .prcm           = {
 311                 .omap2 = {
 312                         .module_offs = CORE_MOD,
 313                         .idlest_reg_id = 1,
 314                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 315                 },
 316         },
 317         .class          = &omap2xxx_timer_hwmod_class,
 318         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 319 };
 320
 321 /* timer8 */
 322 struct omap_hwmod omap2xxx_timer8_hwmod = {
 323         .name           = "timer8",
 324         .main_clk       = "gpt8_fck",
 325         .prcm           = {
 326                 .omap2 = {
 327                         .module_offs = CORE_MOD,
 328                         .idlest_reg_id = 1,
 329                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 330                 },
 331         },
 332         .class          = &omap2xxx_timer_hwmod_class,
 333         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 334 };
 335
 336 /* timer9 */
 337 struct omap_hwmod omap2xxx_timer9_hwmod = {
 338         .name           = "timer9",
 339         .main_clk       = "gpt9_fck",
 340         .prcm           = {
 341                 .omap2 = {
 342                         .module_offs = CORE_MOD,
 343                         .idlest_reg_id = 1,
 344                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 345                 },
 346         },
 347         .class          = &omap2xxx_timer_hwmod_class,
 348         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 349 };
 350
 351 /* timer10 */
 352 struct omap_hwmod omap2xxx_timer10_hwmod = {
 353         .name           = "timer10",
 354         .main_clk       = "gpt10_fck",
 355         .prcm           = {
 356                 .omap2 = {
 357                         .module_offs = CORE_MOD,
 358                         .idlest_reg_id = 1,
 359                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 360                 },
 361         },
 362         .class          = &omap2xxx_timer_hwmod_class,
 363         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 364 };
 365
 366 /* timer11 */
 367 struct omap_hwmod omap2xxx_timer11_hwmod = {
 368         .name           = "timer11",
 369         .main_clk       = "gpt11_fck",
 370         .prcm           = {
 371                 .omap2 = {
 372                         .module_offs = CORE_MOD,
 373                         .idlest_reg_id = 1,
 374                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 375                 },
 376         },
 377         .class          = &omap2xxx_timer_hwmod_class,
 378         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 379 };
 380
 381 /* timer12 */
 382 struct omap_hwmod omap2xxx_timer12_hwmod = {
 383         .name           = "timer12",
 384         .main_clk       = "gpt12_fck",
 385         .prcm           = {
 386                 .omap2 = {
 387                         .module_offs = CORE_MOD,
 388                         .idlest_reg_id = 1,
 389                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 390                 },
 391         },
 392         .class          = &omap2xxx_timer_hwmod_class,
 393         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 394 };
 395
 396 /* wd_timer2 */
 397 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 398         .name           = "wd_timer2",
 399         .class          = &omap2xxx_wd_timer_hwmod_class,
 400         .main_clk       = "mpu_wdt_fck",
 401         .prcm           = {
 402                 .omap2 = {
 403                         .module_offs = WKUP_MOD,
 404                         .idlest_reg_id = 1,
 405                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 406                 },
 407         },
 408 };
 409
 410 /* UART1 */
 411
 412 struct omap_hwmod omap2xxx_uart1_hwmod = {
 413         .name           = "uart1",
 414         .main_clk       = "uart1_fck",
 415         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 416         .prcm           = {
 417                 .omap2 = {
 418                         .module_offs = CORE_MOD,
 419                         .idlest_reg_id = 1,
 420                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 421                 },
 422         },
 423         .class          = &omap2_uart_class,
 424 };
 425
 426 /* UART2 */
 427
 428 struct omap_hwmod omap2xxx_uart2_hwmod = {
 429         .name           = "uart2",
 430         .main_clk       = "uart2_fck",
 431         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 432         .prcm           = {
 433                 .omap2 = {
 434                         .module_offs = CORE_MOD,
 435                         .idlest_reg_id = 1,
 436                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 437                 },
 438         },
 439         .class          = &omap2_uart_class,
 440 };
 441
 442 /* UART3 */
 443
 444 struct omap_hwmod omap2xxx_uart3_hwmod = {
 445         .name           = "uart3",
 446         .main_clk       = "uart3_fck",
 447         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 448         .prcm           = {
 449                 .omap2 = {
 450                         .module_offs = CORE_MOD,
 451                         .idlest_reg_id = 2,
 452                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 453                 },
 454         },
 455         .class          = &omap2_uart_class,
 456 };
 457
 458 /* dss */
 459
 460 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 461         /*
 462          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 463          * driver does not use these clocks.
 464          */
 465         { .role = "tv_clk", .clk = "dss_54m_fck" },
 466         { .role = "sys_clk", .clk = "dss2_fck" },
 467 };
 468
 469 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 470         .name           = "dss_core",
 471         .class          = &omap2_dss_hwmod_class,
 472         .main_clk       = "dss1_fck", /* instead of dss_fck */
 473         .prcm           = {
 474                 .omap2 = {
 475                         .module_offs = CORE_MOD,
 476                         .idlest_reg_id = 1,
 477                 },
 478         },
 479         .opt_clks       = dss_opt_clks,
 480         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 481         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 482 };
 483
 484 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 485         .name           = "dss_dispc",
 486         .class          = &omap2_dispc_hwmod_class,
 487         .main_clk       = "dss1_fck",
 488         .prcm           = {
 489                 .omap2 = {
 490                         .module_offs = CORE_MOD,
 491                         .idlest_reg_id = 1,
 492                 },
 493         },
 494         .flags          = HWMOD_NO_IDLEST,
 495         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 496 };
 497
 498 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 499         { .role = "ick", .clk = "dss_ick" },
 500 };
 501
 502 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 503         .name           = "dss_rfbi",
 504         .class          = &omap2_rfbi_hwmod_class,
 505         .main_clk       = "dss1_fck",
 506         .prcm           = {
 507                 .omap2 = {
 508                         .module_offs = CORE_MOD,
 509                 },
 510         },
 511         .opt_clks       = dss_rfbi_opt_clks,
 512         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 513         .flags          = HWMOD_NO_IDLEST,
 514 };
 515
 516 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 517         .name           = "dss_venc",
 518         .class          = &omap2_venc_hwmod_class,
 519         .main_clk       = "dss_54m_fck",
 520         .prcm           = {
 521                 .omap2 = {
 522                         .module_offs = CORE_MOD,
 523                 },
 524         },
 525         .flags          = HWMOD_NO_IDLEST,
 526 };
 527
 528 /* gpio1 */
 529 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 530         .name           = "gpio1",
 531         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 532         .main_clk       = "gpios_fck",
 533         .prcm           = {
 534                 .omap2 = {
 535                         .module_offs = WKUP_MOD,
 536                         .idlest_reg_id = 1,
 537                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 538                 },
 539         },
 540         .class          = &omap2xxx_gpio_hwmod_class,
 541 };
 542
 543 /* gpio2 */
 544 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 545         .name           = "gpio2",
 546         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 547         .main_clk       = "gpios_fck",
 548         .prcm           = {
 549                 .omap2 = {
 550                         .module_offs = WKUP_MOD,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 553                 },
 554         },
 555         .class          = &omap2xxx_gpio_hwmod_class,
 556 };
 557
 558 /* gpio3 */
 559 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 560         .name           = "gpio3",
 561         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 562         .main_clk       = "gpios_fck",
 563         .prcm           = {
 564                 .omap2 = {
 565                         .module_offs = WKUP_MOD,
 566                         .idlest_reg_id = 1,
 567                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 568                 },
 569         },
 570         .class          = &omap2xxx_gpio_hwmod_class,
 571 };
 572
 573 /* gpio4 */
 574 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 575         .name           = "gpio4",
 576         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 577         .main_clk       = "gpios_fck",
 578         .prcm           = {
 579                 .omap2 = {
 580                         .module_offs = WKUP_MOD,
 581                         .idlest_reg_id = 1,
 582                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 583                 },
 584         },
 585         .class          = &omap2xxx_gpio_hwmod_class,
 586 };
 587
 588 /* mcspi1 */
 589 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 590         .name           = "mcspi1",
 591         .main_clk       = "mcspi1_fck",
 592         .prcm           = {
 593                 .omap2 = {
 594                         .module_offs = CORE_MOD,
 595                         .idlest_reg_id = 1,
 596                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 597                 },
 598         },
 599         .class          = &omap2xxx_mcspi_class,
 600 };
 601
 602 /* mcspi2 */
 603 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 604         .name           = "mcspi2",
 605         .main_clk       = "mcspi2_fck",
 606         .prcm           = {
 607                 .omap2 = {
 608                         .module_offs = CORE_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 611                 },
 612         },
 613         .class          = &omap2xxx_mcspi_class,
 614 };
 615
 616 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 617         .name   = "counter",
 618 };
 619
 620 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 621         .name           = "counter_32k",
 622         .main_clk       = "func_32k_ck",
 623         .prcm           = {
 624                 .omap2  = {
 625                         .module_offs = WKUP_MOD,
 626                         .idlest_reg_id = 1,
 627                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 628                 },
 629         },
 630         .class          = &omap2xxx_counter_hwmod_class,
 631 };
 632
 633 /* gpmc */
 634 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 635         .name           = "gpmc",
 636         .class          = &omap2xxx_gpmc_hwmod_class,
 637         .main_clk       = "gpmc_fck",
 638         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 639         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 640         .prcm           = {
 641                 .omap2  = {
 642                         .module_offs = CORE_MOD,
 643                 },
 644         },
 645 };
 646
 647 /* RNG */
 648
 649 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 650         .rev_offs       = 0x3c,
 651         .sysc_offs      = 0x40,
 652         .syss_offs      = 0x44,
 653         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 654                            SYSS_HAS_RESET_STATUS),
 655         .sysc_fields    = &omap_hwmod_sysc_type1,
 656 };
 657
 658 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 659         .name           = "rng",
 660         .sysc           = &omap2_rng_sysc,
 661 };
 662
 663 struct omap_hwmod omap2xxx_rng_hwmod = {
 664         .name           = "rng",
 665         .main_clk       = "l4_ck",
 666         .prcm           = {
 667                 .omap2 = {
 668                         .module_offs = CORE_MOD,
 669                         .idlest_reg_id = 4,
 670                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 671                 },
 672         },
 673         /*
 674          * XXX The first read from the SYSSTATUS register of the RNG
 675          * after the SYSCONFIG SOFTRESET bit is set triggers an
 676          * imprecise external abort.  It's unclear why this happens.
 677          * Until this is analyzed, skip the IP block reset.
 678          */
 679         .flags          = HWMOD_INIT_NO_RESET,
 680         .class          = &omap2_rng_hwmod_class,
 681 };
 682
 683 /* SHAM */
 684
 685 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 686         .rev_offs       = 0x5c,
 687         .sysc_offs      = 0x60,
 688         .syss_offs      = 0x64,
 689         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 690                            SYSS_HAS_RESET_STATUS),
 691         .sysc_fields    = &omap_hwmod_sysc_type1,
 692 };
 693
 694 static struct omap_hwmod_class omap2xxx_sham_class = {
 695         .name   = "sham",
 696         .sysc   = &omap2_sham_sysc,
 697 };
 698
 699 struct omap_hwmod omap2xxx_sham_hwmod = {
 700         .name           = "sham",
 701         .main_clk       = "l4_ck",
 702         .prcm           = {
 703                 .omap2 = {
 704                         .module_offs = CORE_MOD,
 705                         .idlest_reg_id = 4,
 706                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 707                 },
 708         },
 709         .class          = &omap2xxx_sham_class,
 710 };
 711
 712 /* AES */
 713
 714 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 715         .rev_offs       = 0x44,
 716         .sysc_offs      = 0x48,
 717         .syss_offs      = 0x4c,
 718         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 719                            SYSS_HAS_RESET_STATUS),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap2xxx_aes_class = {
 724         .name   = "aes",
 725         .sysc   = &omap2_aes_sysc,
 726 };
 727
 728 struct omap_hwmod omap2xxx_aes_hwmod = {
 729         .name           = "aes",
 730         .main_clk       = "l4_ck",
 731         .prcm           = {
 732                 .omap2 = {
 733                         .module_offs = CORE_MOD,
 734                         .idlest_reg_id = 4,
 735                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 736                 },
 737         },
 738         .class          = &omap2xxx_aes_class,
 739 };