arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19
  20 #include "control.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "prm-regbits-33xx.h"
  24 #include "omap_hwmod_33xx_43xx_common_data.h"
  25
  26 /*
  27  * IP blocks
  28  */
  29
  30 /* emif */
  31 static struct omap_hwmod am33xx_emif_hwmod = {
  32         .name           = "emif",
  33         .class          = &am33xx_emif_hwmod_class,
  34         .clkdm_name     = "l3_clkdm",
  35         .flags          = HWMOD_INIT_NO_IDLE,
  36         .main_clk       = "dpll_ddr_m2_div2_ck",
  37         .prcm           = {
  38                 .omap4  = {
  39                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  40                         .modulemode     = MODULEMODE_SWCTRL,
  41                 },
  42         },
  43 };
  44
  45 /* l4_hs */
  46 static struct omap_hwmod am33xx_l4_hs_hwmod = {
  47         .name           = "l4_hs",
  48         .class          = &am33xx_l4_hwmod_class,
  49         .clkdm_name     = "l4hs_clkdm",
  50         .flags          = HWMOD_INIT_NO_IDLE,
  51         .main_clk       = "l4hs_gclk",
  52         .prcm           = {
  53                 .omap4  = {
  54                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  55                         .modulemode     = MODULEMODE_SWCTRL,
  56                 },
  57         },
  58 };
  59
  60 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  61         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  62 };
  63
  64 /* wkup_m3  */
  65 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  66         .name           = "wkup_m3",
  67         .class          = &am33xx_wkup_m3_hwmod_class,
  68         .clkdm_name     = "l4_wkup_aon_clkdm",
  69         /* Keep hardreset asserted */
  70         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  71         .main_clk       = "dpll_core_m4_div2_ck",
  72         .prcm           = {
  73                 .omap4  = {
  74                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  75                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  76                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
  77                         .modulemode     = MODULEMODE_SWCTRL,
  78                 },
  79         },
  80         .rst_lines      = am33xx_wkup_m3_resets,
  81         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  82 };
  83
  84 /*
  85  * 'adc/tsc' class
  86  * TouchScreen Controller (Anolog-To-Digital Converter)
  87  */
  88 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  89         .rev_offs       = 0x00,
  90         .sysc_offs      = 0x10,
  91         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  93                         SIDLE_SMART_WKUP),
  94         .sysc_fields    = &omap_hwmod_sysc_type2,
  95 };
  96
  97 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
  98         .name           = "adc_tsc",
  99         .sysc           = &am33xx_adc_tsc_sysc,
 100 };
 101
 102 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 103         .name           = "adc_tsc",
 104         .class          = &am33xx_adc_tsc_hwmod_class,
 105         .clkdm_name     = "l4_wkup_clkdm",
 106         .main_clk       = "adc_tsc_fck",
 107         .prcm           = {
 108                 .omap4  = {
 109                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 110                         .modulemode     = MODULEMODE_SWCTRL,
 111                 },
 112         },
 113 };
 114
 115 /*
 116  * Modules omap_hwmod structures
 117  *
 118  * The following IPs are excluded for the moment because:
 119  * - They do not need an explicit SW control using omap_hwmod API.
 120  * - They still need to be validated with the driver
 121  *   properly adapted to omap_hwmod / omap_device
 122  *
 123  *    - cEFUSE (doesn't fall under any ocp_if)
 124  *    - clkdiv32k
 125  *    - ocp watch point
 126  */
 127 #if 0
 128 /*
 129  * 'cefuse' class
 130  */
 131 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 132         .name           = "cefuse",
 133 };
 134
 135 static struct omap_hwmod am33xx_cefuse_hwmod = {
 136         .name           = "cefuse",
 137         .class          = &am33xx_cefuse_hwmod_class,
 138         .clkdm_name     = "l4_cefuse_clkdm",
 139         .main_clk       = "cefuse_fck",
 140         .prcm           = {
 141                 .omap4  = {
 142                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 143                         .modulemode     = MODULEMODE_SWCTRL,
 144                 },
 145         },
 146 };
 147
 148 /*
 149  * 'clkdiv32k' class
 150  */
 151 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 152         .name           = "clkdiv32k",
 153 };
 154
 155 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 156         .name           = "clkdiv32k",
 157         .class          = &am33xx_clkdiv32k_hwmod_class,
 158         .clkdm_name     = "clk_24mhz_clkdm",
 159         .main_clk       = "clkdiv32k_ick",
 160         .prcm           = {
 161                 .omap4  = {
 162                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 163                         .modulemode     = MODULEMODE_SWCTRL,
 164                 },
 165         },
 166 };
 167
 168 /* ocpwp */
 169 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 170         .name           = "ocpwp",
 171 };
 172
 173 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 174         .name           = "ocpwp",
 175         .class          = &am33xx_ocpwp_hwmod_class,
 176         .clkdm_name     = "l4ls_clkdm",
 177         .main_clk       = "l4ls_gclk",
 178         .prcm           = {
 179                 .omap4  = {
 180                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 181                         .modulemode     = MODULEMODE_SWCTRL,
 182                 },
 183         },
 184 };
 185 #endif
 186
 187 /*
 188  * 'debugss' class
 189  * debug sub system
 190  */
 191 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 192         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 193         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 194 };
 195
 196 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 197         .name           = "debugss",
 198 };
 199
 200 static struct omap_hwmod am33xx_debugss_hwmod = {
 201         .name           = "debugss",
 202         .class          = &am33xx_debugss_hwmod_class,
 203         .clkdm_name     = "l3_aon_clkdm",
 204         .main_clk       = "trace_clk_div_ck",
 205         .prcm           = {
 206                 .omap4  = {
 207                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 208                         .modulemode     = MODULEMODE_SWCTRL,
 209                 },
 210         },
 211         .opt_clks       = debugss_opt_clks,
 212         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 213 };
 214
 215 static struct omap_hwmod am33xx_control_hwmod = {
 216         .name           = "control",
 217         .class          = &am33xx_control_hwmod_class,
 218         .clkdm_name     = "l4_wkup_clkdm",
 219         .flags          = HWMOD_INIT_NO_IDLE,
 220         .main_clk       = "dpll_core_m4_div2_ck",
 221         .prcm           = {
 222                 .omap4  = {
 223                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 224                         .modulemode     = MODULEMODE_SWCTRL,
 225                 },
 226         },
 227 };
 228
 229 /* lcdc */
 230 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
 231         .rev_offs       = 0x0,
 232         .sysc_offs      = 0x54,
 233         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
 234         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 235                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
 236         .sysc_fields    = &omap_hwmod_sysc_type2,
 237 };
 238
 239 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 240         .name           = "lcdc",
 241         .sysc           = &lcdc_sysc,
 242 };
 243
 244 static struct omap_hwmod am33xx_lcdc_hwmod = {
 245         .name           = "lcdc",
 246         .class          = &am33xx_lcdc_hwmod_class,
 247         .clkdm_name     = "lcdc_clkdm",
 248         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 249         .main_clk       = "lcd_gclk",
 250         .prcm           = {
 251                 .omap4  = {
 252                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
 253                         .modulemode     = MODULEMODE_SWCTRL,
 254                 },
 255         },
 256 };
 257
 258 /*
 259  * Interfaces
 260  */
 261
 262 /* l3 main -> emif */
 263 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
 264         .master         = &am33xx_l3_main_hwmod,
 265         .slave          = &am33xx_emif_hwmod,
 266         .clk            = "dpll_core_m4_ck",
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* l3 main -> l4 hs */
 271 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
 272         .master         = &am33xx_l3_main_hwmod,
 273         .slave          = &am33xx_l4_hs_hwmod,
 274         .clk            = "l3s_gclk",
 275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 276 };
 277
 278 /* wkup m3 -> l4 wkup */
 279 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
 280         .master         = &am33xx_wkup_m3_hwmod,
 281         .slave          = &am33xx_l4_wkup_hwmod,
 282         .clk            = "dpll_core_m4_div2_ck",
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* l4 wkup -> wkup m3 */
 287 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
 288         .master         = &am33xx_l4_wkup_hwmod,
 289         .slave          = &am33xx_wkup_m3_hwmod,
 290         .clk            = "dpll_core_m4_div2_ck",
 291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 292 };
 293
 294 /* l4 hs -> pru-icss */
 295 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
 296         .master         = &am33xx_l4_hs_hwmod,
 297         .slave          = &am33xx_pruss_hwmod,
 298         .clk            = "dpll_core_m4_ck",
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* l3_main -> debugss */
 303 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
 304         .master         = &am33xx_l3_main_hwmod,
 305         .slave          = &am33xx_debugss_hwmod,
 306         .clk            = "dpll_core_m4_ck",
 307         .user           = OCP_USER_MPU,
 308 };
 309
 310 /* l4 wkup -> smartreflex0 */
 311 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 312         .master         = &am33xx_l4_wkup_hwmod,
 313         .slave          = &am33xx_smartreflex0_hwmod,
 314         .clk            = "dpll_core_m4_div2_ck",
 315         .user           = OCP_USER_MPU,
 316 };
 317
 318 /* l4 wkup -> smartreflex1 */
 319 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 320         .master         = &am33xx_l4_wkup_hwmod,
 321         .slave          = &am33xx_smartreflex1_hwmod,
 322         .clk            = "dpll_core_m4_div2_ck",
 323         .user           = OCP_USER_MPU,
 324 };
 325
 326 /* l4 wkup -> control */
 327 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
 328         .master         = &am33xx_l4_wkup_hwmod,
 329         .slave          = &am33xx_control_hwmod,
 330         .clk            = "dpll_core_m4_div2_ck",
 331         .user           = OCP_USER_MPU,
 332 };
 333
 334 /* L4 WKUP -> ADC_TSC */
 335 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
 336         .master         = &am33xx_l4_wkup_hwmod,
 337         .slave          = &am33xx_adc_tsc_hwmod,
 338         .clk            = "dpll_core_m4_div2_ck",
 339         .user           = OCP_USER_MPU,
 340 };
 341
 342 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
 343         .master         = &am33xx_l3_main_hwmod,
 344         .slave          = &am33xx_lcdc_hwmod,
 345         .clk            = "dpll_core_m4_ck",
 346         .user           = OCP_USER_MPU,
 347 };
 348
 349 /* l4 wkup -> timer1 */
 350 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
 351         .master         = &am33xx_l4_wkup_hwmod,
 352         .slave          = &am33xx_timer1_hwmod,
 353         .clk            = "dpll_core_m4_div2_ck",
 354         .user           = OCP_USER_MPU,
 355 };
 356
 357 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 358         &am33xx_l3_main__emif,
 359         &am33xx_mpu__l3_main,
 360         &am33xx_mpu__prcm,
 361         &am33xx_l3_s__l4_ls,
 362         &am33xx_l3_s__l4_wkup,
 363         &am33xx_l3_main__l4_hs,
 364         &am33xx_l3_main__l3_s,
 365         &am33xx_l3_main__l3_instr,
 366         &am33xx_l3_main__gfx,
 367         &am33xx_l3_s__l3_main,
 368         &am33xx_pruss__l3_main,
 369         &am33xx_wkup_m3__l4_wkup,
 370         &am33xx_gfx__l3_main,
 371         &am33xx_l3_main__debugss,
 372         &am33xx_l4_wkup__wkup_m3,
 373         &am33xx_l4_wkup__control,
 374         &am33xx_l4_wkup__smartreflex0,
 375         &am33xx_l4_wkup__smartreflex1,
 376         &am33xx_l4_wkup__timer1,
 377         &am33xx_l4_wkup__rtc,
 378         &am33xx_l4_wkup__adc_tsc,
 379         &am33xx_l4_hs__pruss,
 380         &am33xx_l4_per__dcan0,
 381         &am33xx_l4_per__dcan1,
 382         &am33xx_l4_ls__timer2,
 383         &am33xx_l4_ls__timer3,
 384         &am33xx_l4_ls__timer4,
 385         &am33xx_l4_ls__timer5,
 386         &am33xx_l4_ls__timer6,
 387         &am33xx_l4_ls__timer7,
 388         &am33xx_l3_main__tpcc,
 389         &am33xx_l4_ls__spinlock,
 390         &am33xx_l4_ls__elm,
 391         &am33xx_l4_ls__epwmss0,
 392         &am33xx_l4_ls__epwmss1,
 393         &am33xx_l4_ls__epwmss2,
 394         &am33xx_l3_s__gpmc,
 395         &am33xx_l3_main__lcdc,
 396         &am33xx_l4_ls__mcspi0,
 397         &am33xx_l4_ls__mcspi1,
 398         &am33xx_l3_main__tptc0,
 399         &am33xx_l3_main__tptc1,
 400         &am33xx_l3_main__tptc2,
 401         &am33xx_l3_main__ocmc,
 402         &am33xx_l3_main__sha0,
 403         &am33xx_l3_main__aes0,
 404         NULL,
 405 };
 406
 407 int __init am33xx_hwmod_init(void)
 408 {
 409         omap_hwmod_am33xx_reg();
 410         omap_hwmod_init();
 411         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 412 }