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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
blobcc5ad6acab1d9524c14041c9fefb74b5f56b3be7
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Hardware modules present on the OMAP54xx chips
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 */
16
17 #include <linux/io.h>
18 #include <linux/power/smartreflex.h>
19
20 #include <linux/omap-dma.h>
21
22 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
24 #include "cm1_54xx.h"
25 #include "cm2_54xx.h"
26 #include "prm54xx.h"
27
28 /* Base offset for all OMAP5 interrupts external to MPUSS */
29 #define OMAP54XX_IRQ_GIC_START 32
30
31 /* Base offset for all OMAP5 dma requests */
32 #define OMAP54XX_DMA_REQ_START 1
33
34
35 /*
36 * IP blocks
37 */
38
39 /*
40 * 'dmm' class
41 * instance(s): dmm
42 */
43 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
44 .name = "dmm",
45 };
46
47 /* dmm */
48 static struct omap_hwmod omap54xx_dmm_hwmod = {
49 .name = "dmm",
50 .class = &omap54xx_dmm_hwmod_class,
51 .clkdm_name = "emif_clkdm",
52 .prcm = {
53 .omap4 = {
54 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
55 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
56 },
57 },
58 };
59
60 /*
61 * 'l3' class
62 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
63 */
64 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
65 .name = "l3",
66 };
67
68 /* l3_instr */
69 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
70 .name = "l3_instr",
71 .class = &omap54xx_l3_hwmod_class,
72 .clkdm_name = "l3instr_clkdm",
73 .prcm = {
74 .omap4 = {
75 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
76 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
77 .modulemode = MODULEMODE_HWCTRL,
78 },
79 },
80 };
81
82 /* l3_main_1 */
83 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
84 .name = "l3_main_1",
85 .class = &omap54xx_l3_hwmod_class,
86 .clkdm_name = "l3main1_clkdm",
87 .prcm = {
88 .omap4 = {
89 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
90 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
91 },
92 },
93 };
94
95 /* l3_main_2 */
96 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
97 .name = "l3_main_2",
98 .class = &omap54xx_l3_hwmod_class,
99 .clkdm_name = "l3main2_clkdm",
100 .prcm = {
101 .omap4 = {
102 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
103 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
104 },
105 },
106 };
107
108 /* l3_main_3 */
109 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
110 .name = "l3_main_3",
111 .class = &omap54xx_l3_hwmod_class,
112 .clkdm_name = "l3instr_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
116 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
117 .modulemode = MODULEMODE_HWCTRL,
118 },
119 },
120 };
121
122 /*
123 * 'l4' class
124 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
125 */
126 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
127 .name = "l4",
128 };
129
130 /* l4_abe */
131 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
132 .name = "l4_abe",
133 .class = &omap54xx_l4_hwmod_class,
134 .clkdm_name = "abe_clkdm",
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
138 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
139 },
140 },
141 };
142
143 /* l4_cfg */
144 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
145 .name = "l4_cfg",
146 .class = &omap54xx_l4_hwmod_class,
147 .clkdm_name = "l4cfg_clkdm",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
151 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
152 },
153 },
154 };
155
156 /* l4_per */
157 static struct omap_hwmod omap54xx_l4_per_hwmod = {
158 .name = "l4_per",
159 .class = &omap54xx_l4_hwmod_class,
160 .clkdm_name = "l4per_clkdm",
161 .prcm = {
162 .omap4 = {
163 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
164 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
165 },
166 },
167 };
168
169 /* l4_wkup */
170 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
171 .name = "l4_wkup",
172 .class = &omap54xx_l4_hwmod_class,
173 .clkdm_name = "wkupaon_clkdm",
174 .prcm = {
175 .omap4 = {
176 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
177 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
178 },
179 },
180 };
181
182 /*
183 * 'mpu_bus' class
184 * instance(s): mpu_private
185 */
186 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
187 .name = "mpu_bus",
188 };
189
190 /* mpu_private */
191 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
192 .name = "mpu_private",
193 .class = &omap54xx_mpu_bus_hwmod_class,
194 .clkdm_name = "mpu_clkdm",
195 .prcm = {
196 .omap4 = {
197 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
198 },
199 },
200 };
201
202 /*
203 * 'counter' class
204 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
205 */
206
207 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
208 .rev_offs = 0x0000,
209 .sysc_offs = 0x0010,
210 .sysc_flags = SYSC_HAS_SIDLEMODE,
211 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
212 .sysc_fields = &omap_hwmod_sysc_type1,
213 };
214
215 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
216 .name = "counter",
217 .sysc = &omap54xx_counter_sysc,
218 };
219
220 /* counter_32k */
221 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
222 .name = "counter_32k",
223 .class = &omap54xx_counter_hwmod_class,
224 .clkdm_name = "wkupaon_clkdm",
225 .flags = HWMOD_SWSUP_SIDLE,
226 .main_clk = "wkupaon_iclk_mux",
227 .prcm = {
228 .omap4 = {
229 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
230 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
231 },
232 },
233 };
234
235 /*
236 * 'dma' class
237 * dma controller for data exchange between memory to memory (i.e. internal or
238 * external memory) and gp peripherals to memory or memory to gp peripherals
239 */
240
241 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
242 .rev_offs = 0x0000,
243 .sysc_offs = 0x002c,
244 .syss_offs = 0x0028,
245 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
246 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
247 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
248 SYSS_HAS_RESET_STATUS),
249 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
250 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
251 .sysc_fields = &omap_hwmod_sysc_type1,
252 };
253
254 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
255 .name = "dma",
256 .sysc = &omap54xx_dma_sysc,
257 };
258
259 /* dma dev_attr */
260 static struct omap_dma_dev_attr dma_dev_attr = {
261 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
262 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
263 .lch_count = 32,
264 };
265
266 /* dma_system */
267 static struct omap_hwmod omap54xx_dma_system_hwmod = {
268 .name = "dma_system",
269 .class = &omap54xx_dma_hwmod_class,
270 .clkdm_name = "dma_clkdm",
271 .main_clk = "l3_iclk_div",
272 .prcm = {
273 .omap4 = {
274 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
275 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
276 },
277 },
278 .dev_attr = &dma_dev_attr,
279 };
280
281 /*
282 * 'dmic' class
283 * digital microphone controller
284 */
285
286 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
287 .rev_offs = 0x0000,
288 .sysc_offs = 0x0010,
289 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
290 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
291 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
292 SIDLE_SMART_WKUP),
293 .sysc_fields = &omap_hwmod_sysc_type2,
294 };
295
296 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
297 .name = "dmic",
298 .sysc = &omap54xx_dmic_sysc,
299 };
300
301 /* dmic */
302 static struct omap_hwmod omap54xx_dmic_hwmod = {
303 .name = "dmic",
304 .class = &omap54xx_dmic_hwmod_class,
305 .clkdm_name = "abe_clkdm",
306 .main_clk = "dmic_gfclk",
307 .prcm = {
308 .omap4 = {
309 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
310 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 };
315
316 /*
317 * 'dss' class
318 * display sub-system
319 */
320 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
321 .rev_offs = 0x0000,
322 .syss_offs = 0x0014,
323 .sysc_flags = SYSS_HAS_RESET_STATUS,
324 };
325
326 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
327 .name = "dss",
328 .sysc = &omap54xx_dss_sysc,
329 .reset = omap_dss_reset,
330 };
331
332 /* dss */
333 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
334 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
335 { .role = "sys_clk", .clk = "dss_sys_clk" },
336 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
337 };
338
339 static struct omap_hwmod omap54xx_dss_hwmod = {
340 .name = "dss_core",
341 .class = &omap54xx_dss_hwmod_class,
342 .clkdm_name = "dss_clkdm",
343 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
344 .main_clk = "dss_dss_clk",
345 .prcm = {
346 .omap4 = {
347 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
348 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
349 .modulemode = MODULEMODE_SWCTRL,
350 },
351 },
352 .opt_clks = dss_opt_clks,
353 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
354 };
355
356 /*
357 * 'dispc' class
358 * display controller
359 */
360
361 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
362 .rev_offs = 0x0000,
363 .sysc_offs = 0x0010,
364 .syss_offs = 0x0014,
365 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
366 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
367 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
368 SYSS_HAS_RESET_STATUS),
369 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
370 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
371 .sysc_fields = &omap_hwmod_sysc_type1,
372 };
373
374 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
375 .name = "dispc",
376 .sysc = &omap54xx_dispc_sysc,
377 };
378
379 /* dss_dispc */
380 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
381 { .role = "sys_clk", .clk = "dss_sys_clk" },
382 };
383
384 /* dss_dispc dev_attr */
385 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
386 .has_framedonetv_irq = 1,
387 .manager_count = 4,
388 };
389
390 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
391 .name = "dss_dispc",
392 .class = &omap54xx_dispc_hwmod_class,
393 .clkdm_name = "dss_clkdm",
394 .main_clk = "dss_dss_clk",
395 .prcm = {
396 .omap4 = {
397 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
398 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
399 },
400 },
401 .opt_clks = dss_dispc_opt_clks,
402 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
403 .dev_attr = &dss_dispc_dev_attr,
404 .parent_hwmod = &omap54xx_dss_hwmod,
405 };
406
407 /*
408 * 'dsi1' class
409 * display serial interface controller
410 */
411
412 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
413 .rev_offs = 0x0000,
414 .sysc_offs = 0x0010,
415 .syss_offs = 0x0014,
416 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
417 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
418 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
419 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
420 .sysc_fields = &omap_hwmod_sysc_type1,
421 };
422
423 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
424 .name = "dsi1",
425 .sysc = &omap54xx_dsi1_sysc,
426 };
427
428 /* dss_dsi1_a */
429 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
430 { .role = "sys_clk", .clk = "dss_sys_clk" },
431 };
432
433 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
434 .name = "dss_dsi1",
435 .class = &omap54xx_dsi1_hwmod_class,
436 .clkdm_name = "dss_clkdm",
437 .main_clk = "dss_dss_clk",
438 .prcm = {
439 .omap4 = {
440 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
441 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
442 },
443 },
444 .opt_clks = dss_dsi1_a_opt_clks,
445 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
446 .parent_hwmod = &omap54xx_dss_hwmod,
447 };
448
449 /* dss_dsi1_c */
450 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
451 { .role = "sys_clk", .clk = "dss_sys_clk" },
452 };
453
454 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
455 .name = "dss_dsi2",
456 .class = &omap54xx_dsi1_hwmod_class,
457 .clkdm_name = "dss_clkdm",
458 .main_clk = "dss_dss_clk",
459 .prcm = {
460 .omap4 = {
461 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
462 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
463 },
464 },
465 .opt_clks = dss_dsi1_c_opt_clks,
466 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
467 .parent_hwmod = &omap54xx_dss_hwmod,
468 };
469
470 /*
471 * 'hdmi' class
472 * hdmi controller
473 */
474
475 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
476 .rev_offs = 0x0000,
477 .sysc_offs = 0x0010,
478 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
479 SYSC_HAS_SOFTRESET),
480 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
481 SIDLE_SMART_WKUP),
482 .sysc_fields = &omap_hwmod_sysc_type2,
483 };
484
485 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
486 .name = "hdmi",
487 .sysc = &omap54xx_hdmi_sysc,
488 };
489
490 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
491 { .role = "sys_clk", .clk = "dss_sys_clk" },
492 };
493
494 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
495 .name = "dss_hdmi",
496 .class = &omap54xx_hdmi_hwmod_class,
497 .clkdm_name = "dss_clkdm",
498 .main_clk = "dss_48mhz_clk",
499 .prcm = {
500 .omap4 = {
501 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
502 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
503 },
504 },
505 .opt_clks = dss_hdmi_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
507 .parent_hwmod = &omap54xx_dss_hwmod,
508 };
509
510 /*
511 * 'rfbi' class
512 * remote frame buffer interface
513 */
514
515 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
516 .rev_offs = 0x0000,
517 .sysc_offs = 0x0010,
518 .syss_offs = 0x0014,
519 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
520 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
521 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
522 .sysc_fields = &omap_hwmod_sysc_type1,
523 };
524
525 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
526 .name = "rfbi",
527 .sysc = &omap54xx_rfbi_sysc,
528 };
529
530 /* dss_rfbi */
531 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
532 { .role = "ick", .clk = "l3_iclk_div" },
533 };
534
535 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
536 .name = "dss_rfbi",
537 .class = &omap54xx_rfbi_hwmod_class,
538 .clkdm_name = "dss_clkdm",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
542 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
543 },
544 },
545 .opt_clks = dss_rfbi_opt_clks,
546 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
547 .parent_hwmod = &omap54xx_dss_hwmod,
548 };
549
550 /*
551 * 'emif' class
552 * external memory interface no1 (wrapper)
553 */
554
555 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
556 .rev_offs = 0x0000,
557 };
558
559 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
560 .name = "emif",
561 .sysc = &omap54xx_emif_sysc,
562 };
563
564 /* emif1 */
565 static struct omap_hwmod omap54xx_emif1_hwmod = {
566 .name = "emif1",
567 .class = &omap54xx_emif_hwmod_class,
568 .clkdm_name = "emif_clkdm",
569 .flags = HWMOD_INIT_NO_IDLE,
570 .main_clk = "dpll_core_h11x2_ck",
571 .prcm = {
572 .omap4 = {
573 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
574 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
575 .modulemode = MODULEMODE_HWCTRL,
576 },
577 },
578 };
579
580 /* emif2 */
581 static struct omap_hwmod omap54xx_emif2_hwmod = {
582 .name = "emif2",
583 .class = &omap54xx_emif_hwmod_class,
584 .clkdm_name = "emif_clkdm",
585 .flags = HWMOD_INIT_NO_IDLE,
586 .main_clk = "dpll_core_h11x2_ck",
587 .prcm = {
588 .omap4 = {
589 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
590 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
591 .modulemode = MODULEMODE_HWCTRL,
592 },
593 },
594 };
595
596 /*
597 * 'kbd' class
598 * keyboard controller
599 */
600
601 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
602 .rev_offs = 0x0000,
603 .sysc_offs = 0x0010,
604 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
605 SYSC_HAS_SOFTRESET),
606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
607 .sysc_fields = &omap_hwmod_sysc_type1,
608 };
609
610 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
611 .name = "kbd",
612 .sysc = &omap54xx_kbd_sysc,
613 };
614
615 /* kbd */
616 static struct omap_hwmod omap54xx_kbd_hwmod = {
617 .name = "kbd",
618 .class = &omap54xx_kbd_hwmod_class,
619 .clkdm_name = "wkupaon_clkdm",
620 .main_clk = "sys_32k_ck",
621 .prcm = {
622 .omap4 = {
623 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
624 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
625 .modulemode = MODULEMODE_SWCTRL,
626 },
627 },
628 };
629
630 /*
631 * 'mcpdm' class
632 * multi channel pdm controller (proprietary interface with phoenix power
633 * ic)
634 */
635
636 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
637 .rev_offs = 0x0000,
638 .sysc_offs = 0x0010,
639 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
640 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
641 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
642 SIDLE_SMART_WKUP),
643 .sysc_fields = &omap_hwmod_sysc_type2,
644 };
645
646 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
647 .name = "mcpdm",
648 .sysc = &omap54xx_mcpdm_sysc,
649 };
650
651 /* mcpdm */
652 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
653 .name = "mcpdm",
654 .class = &omap54xx_mcpdm_hwmod_class,
655 .clkdm_name = "abe_clkdm",
656 /*
657 * It's suspected that the McPDM requires an off-chip main
658 * functional clock, controlled via I2C. This IP block is
659 * currently reset very early during boot, before I2C is
660 * available, so it doesn't seem that we have any choice in
661 * the kernel other than to avoid resetting it. XXX This is
662 * really a hardware issue workaround: every IP block should
663 * be able to source its main functional clock from either
664 * on-chip or off-chip sources. McPDM seems to be the only
665 * current exception.
666 */
667
668 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
669 .main_clk = "pad_clks_ck",
670 .prcm = {
671 .omap4 = {
672 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
673 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
674 .modulemode = MODULEMODE_SWCTRL,
675 },
676 },
677 };
678
679
680 /*
681 * 'mmu' class
682 * The memory management unit performs virtual to physical address translation
683 * for its requestors.
684 */
685
686 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
687 .rev_offs = 0x0000,
688 .sysc_offs = 0x0010,
689 .syss_offs = 0x0014,
690 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
691 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
692 SYSS_HAS_RESET_STATUS),
693 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
694 .sysc_fields = &omap_hwmod_sysc_type1,
695 };
696
697 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
698 .name = "mmu",
699 .sysc = &omap54xx_mmu_sysc,
700 };
701
702 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
703 { .name = "mmu_cache", .rst_shift = 1 },
704 };
705
706 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
707 .name = "mmu_dsp",
708 .class = &omap54xx_mmu_hwmod_class,
709 .clkdm_name = "dsp_clkdm",
710 .rst_lines = omap54xx_mmu_dsp_resets,
711 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
712 .main_clk = "dpll_iva_h11x2_ck",
713 .prcm = {
714 .omap4 = {
715 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
716 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
717 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
718 .modulemode = MODULEMODE_HWCTRL,
719 },
720 },
721 };
722
723 /* mmu ipu */
724 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
725 { .name = "mmu_cache", .rst_shift = 2 },
726 };
727
728 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
729 .name = "mmu_ipu",
730 .class = &omap54xx_mmu_hwmod_class,
731 .clkdm_name = "ipu_clkdm",
732 .rst_lines = omap54xx_mmu_ipu_resets,
733 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
734 .main_clk = "dpll_core_h22x2_ck",
735 .prcm = {
736 .omap4 = {
737 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
738 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
739 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
740 .modulemode = MODULEMODE_HWCTRL,
741 },
742 },
743 };
744
745 /*
746 * 'mpu' class
747 * mpu sub-system
748 */
749
750 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
751 .name = "mpu",
752 };
753
754 /* mpu */
755 static struct omap_hwmod omap54xx_mpu_hwmod = {
756 .name = "mpu",
757 .class = &omap54xx_mpu_hwmod_class,
758 .clkdm_name = "mpu_clkdm",
759 .flags = HWMOD_INIT_NO_IDLE,
760 .main_clk = "dpll_mpu_m2_ck",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
764 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
765 },
766 },
767 };
768
769 /*
770 * 'spinlock' class
771 * spinlock provides hardware assistance for synchronizing the processes
772 * running on multiple processors
773 */
774
775 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
776 .rev_offs = 0x0000,
777 .sysc_offs = 0x0010,
778 .syss_offs = 0x0014,
779 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
780 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
781 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
782 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
783 .sysc_fields = &omap_hwmod_sysc_type1,
784 };
785
786 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
787 .name = "spinlock",
788 .sysc = &omap54xx_spinlock_sysc,
789 };
790
791 /* spinlock */
792 static struct omap_hwmod omap54xx_spinlock_hwmod = {
793 .name = "spinlock",
794 .class = &omap54xx_spinlock_hwmod_class,
795 .clkdm_name = "l4cfg_clkdm",
796 .prcm = {
797 .omap4 = {
798 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
799 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
800 },
801 },
802 };
803
804 /*
805 * 'ocp2scp' class
806 * bridge to transform ocp interface protocol to scp (serial control port)
807 * protocol
808 */
809
810 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
811 .rev_offs = 0x0000,
812 .sysc_offs = 0x0010,
813 .syss_offs = 0x0014,
814 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
815 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
817 .sysc_fields = &omap_hwmod_sysc_type1,
818 };
819
820 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
821 .name = "ocp2scp",
822 .sysc = &omap54xx_ocp2scp_sysc,
823 };
824
825 /* ocp2scp1 */
826 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
827 .name = "ocp2scp1",
828 .class = &omap54xx_ocp2scp_hwmod_class,
829 .clkdm_name = "l3init_clkdm",
830 .main_clk = "l4_root_clk_div",
831 .prcm = {
832 .omap4 = {
833 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
834 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
835 .modulemode = MODULEMODE_HWCTRL,
836 },
837 },
838 };
839
840 /*
841 * 'timer' class
842 * general purpose timer module with accurate 1ms tick
843 * This class contains several variants: ['timer_1ms', 'timer']
844 */
845
846 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
847 .rev_offs = 0x0000,
848 .sysc_offs = 0x0010,
849 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
850 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
851 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
852 SIDLE_SMART_WKUP),
853 .sysc_fields = &omap_hwmod_sysc_type2,
854 };
855
856 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
857 .name = "timer",
858 .sysc = &omap54xx_timer_1ms_sysc,
859 };
860
861 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
862 .rev_offs = 0x0000,
863 .sysc_offs = 0x0010,
864 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
865 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
866 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
867 SIDLE_SMART_WKUP),
868 .sysc_fields = &omap_hwmod_sysc_type2,
869 };
870
871 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
872 .name = "timer",
873 .sysc = &omap54xx_timer_sysc,
874 };
875
876 /* timer1 */
877 static struct omap_hwmod omap54xx_timer1_hwmod = {
878 .name = "timer1",
879 .class = &omap54xx_timer_1ms_hwmod_class,
880 .clkdm_name = "wkupaon_clkdm",
881 .main_clk = "timer1_gfclk_mux",
882 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
883 .prcm = {
884 .omap4 = {
885 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
886 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
887 .modulemode = MODULEMODE_SWCTRL,
888 },
889 },
890 };
891
892 /* timer2 */
893 static struct omap_hwmod omap54xx_timer2_hwmod = {
894 .name = "timer2",
895 .class = &omap54xx_timer_1ms_hwmod_class,
896 .clkdm_name = "l4per_clkdm",
897 .main_clk = "timer2_gfclk_mux",
898 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
899 .prcm = {
900 .omap4 = {
901 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
902 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
903 .modulemode = MODULEMODE_SWCTRL,
904 },
905 },
906 };
907
908 /* timer3 */
909 static struct omap_hwmod omap54xx_timer3_hwmod = {
910 .name = "timer3",
911 .class = &omap54xx_timer_hwmod_class,
912 .clkdm_name = "l4per_clkdm",
913 .main_clk = "timer3_gfclk_mux",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
917 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 };
922
923 /* timer4 */
924 static struct omap_hwmod omap54xx_timer4_hwmod = {
925 .name = "timer4",
926 .class = &omap54xx_timer_hwmod_class,
927 .clkdm_name = "l4per_clkdm",
928 .main_clk = "timer4_gfclk_mux",
929 .prcm = {
930 .omap4 = {
931 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
932 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
934 },
935 },
936 };
937
938 /* timer5 */
939 static struct omap_hwmod omap54xx_timer5_hwmod = {
940 .name = "timer5",
941 .class = &omap54xx_timer_hwmod_class,
942 .clkdm_name = "abe_clkdm",
943 .main_clk = "timer5_gfclk_mux",
944 .prcm = {
945 .omap4 = {
946 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
947 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
948 .modulemode = MODULEMODE_SWCTRL,
949 },
950 },
951 };
952
953 /* timer6 */
954 static struct omap_hwmod omap54xx_timer6_hwmod = {
955 .name = "timer6",
956 .class = &omap54xx_timer_hwmod_class,
957 .clkdm_name = "abe_clkdm",
958 .main_clk = "timer6_gfclk_mux",
959 .prcm = {
960 .omap4 = {
961 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
962 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
963 .modulemode = MODULEMODE_SWCTRL,
964 },
965 },
966 };
967
968 /* timer7 */
969 static struct omap_hwmod omap54xx_timer7_hwmod = {
970 .name = "timer7",
971 .class = &omap54xx_timer_hwmod_class,
972 .clkdm_name = "abe_clkdm",
973 .main_clk = "timer7_gfclk_mux",
974 .prcm = {
975 .omap4 = {
976 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
977 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
978 .modulemode = MODULEMODE_SWCTRL,
979 },
980 },
981 };
982
983 /* timer8 */
984 static struct omap_hwmod omap54xx_timer8_hwmod = {
985 .name = "timer8",
986 .class = &omap54xx_timer_hwmod_class,
987 .clkdm_name = "abe_clkdm",
988 .main_clk = "timer8_gfclk_mux",
989 .prcm = {
990 .omap4 = {
991 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
992 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
993 .modulemode = MODULEMODE_SWCTRL,
994 },
995 },
996 };
997
998 /* timer9 */
999 static struct omap_hwmod omap54xx_timer9_hwmod = {
1000 .name = "timer9",
1001 .class = &omap54xx_timer_hwmod_class,
1002 .clkdm_name = "l4per_clkdm",
1003 .main_clk = "timer9_gfclk_mux",
1004 .prcm = {
1005 .omap4 = {
1006 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1007 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1008 .modulemode = MODULEMODE_SWCTRL,
1009 },
1010 },
1011 };
1012
1013 /* timer10 */
1014 static struct omap_hwmod omap54xx_timer10_hwmod = {
1015 .name = "timer10",
1016 .class = &omap54xx_timer_1ms_hwmod_class,
1017 .clkdm_name = "l4per_clkdm",
1018 .main_clk = "timer10_gfclk_mux",
1019 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1020 .prcm = {
1021 .omap4 = {
1022 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1023 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1024 .modulemode = MODULEMODE_SWCTRL,
1025 },
1026 },
1027 };
1028
1029 /* timer11 */
1030 static struct omap_hwmod omap54xx_timer11_hwmod = {
1031 .name = "timer11",
1032 .class = &omap54xx_timer_hwmod_class,
1033 .clkdm_name = "l4per_clkdm",
1034 .main_clk = "timer11_gfclk_mux",
1035 .prcm = {
1036 .omap4 = {
1037 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1038 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1039 .modulemode = MODULEMODE_SWCTRL,
1040 },
1041 },
1042 };
1043
1044 /*
1045 * 'usb_host_hs' class
1046 * high-speed multi-port usb host controller
1047 */
1048
1049 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1050 .rev_offs = 0x0000,
1051 .sysc_offs = 0x0010,
1052 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1053 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1054 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1055 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1056 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1057 .sysc_fields = &omap_hwmod_sysc_type2,
1058 };
1059
1060 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1061 .name = "usb_host_hs",
1062 .sysc = &omap54xx_usb_host_hs_sysc,
1063 };
1064
1065 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1066 .name = "usb_host_hs",
1067 .class = &omap54xx_usb_host_hs_hwmod_class,
1068 .clkdm_name = "l3init_clkdm",
1069 /*
1070 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1071 * id: i660
1072 *
1073 * Description:
1074 * In the following configuration :
1075 * - USBHOST module is set to smart-idle mode
1076 * - PRCM asserts idle_req to the USBHOST module ( This typically
1077 * happens when the system is going to a low power mode : all ports
1078 * have been suspended, the master part of the USBHOST module has
1079 * entered the standby state, and SW has cut the functional clocks)
1080 * - an USBHOST interrupt occurs before the module is able to answer
1081 * idle_ack, typically a remote wakeup IRQ.
1082 * Then the USB HOST module will enter a deadlock situation where it
1083 * is no more accessible nor functional.
1084 *
1085 * Workaround:
1086 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1087 */
1088
1089 /*
1090 * Errata: USB host EHCI may stall when entering smart-standby mode
1091 * Id: i571
1092 *
1093 * Description:
1094 * When the USBHOST module is set to smart-standby mode, and when it is
1095 * ready to enter the standby state (i.e. all ports are suspended and
1096 * all attached devices are in suspend mode), then it can wrongly assert
1097 * the Mstandby signal too early while there are still some residual OCP
1098 * transactions ongoing. If this condition occurs, the internal state
1099 * machine may go to an undefined state and the USB link may be stuck
1100 * upon the next resume.
1101 *
1102 * Workaround:
1103 * Don't use smart standby; use only force standby,
1104 * hence HWMOD_SWSUP_MSTANDBY
1105 */
1106
1107 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1108 .main_clk = "l3init_60m_fclk",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1112 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1113 .modulemode = MODULEMODE_SWCTRL,
1114 },
1115 },
1116 };
1117
1118 /*
1119 * 'usb_tll_hs' class
1120 * usb_tll_hs module is the adapter on the usb_host_hs ports
1121 */
1122
1123 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1124 .rev_offs = 0x0000,
1125 .sysc_offs = 0x0010,
1126 .syss_offs = 0x0014,
1127 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1128 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1129 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1130 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1131 .sysc_fields = &omap_hwmod_sysc_type1,
1132 };
1133
1134 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1135 .name = "usb_tll_hs",
1136 .sysc = &omap54xx_usb_tll_hs_sysc,
1137 };
1138
1139 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1140 .name = "usb_tll_hs",
1141 .class = &omap54xx_usb_tll_hs_hwmod_class,
1142 .clkdm_name = "l3init_clkdm",
1143 .main_clk = "l4_root_clk_div",
1144 .prcm = {
1145 .omap4 = {
1146 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1147 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1148 .modulemode = MODULEMODE_HWCTRL,
1149 },
1150 },
1151 };
1152
1153 /*
1154 * 'usb_otg_ss' class
1155 * 2.0 super speed (usb_otg_ss) controller
1156 */
1157
1158 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1159 .rev_offs = 0x0000,
1160 .sysc_offs = 0x0010,
1161 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1162 SYSC_HAS_SIDLEMODE),
1163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1164 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1165 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1166 .sysc_fields = &omap_hwmod_sysc_type2,
1167 };
1168
1169 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1170 .name = "usb_otg_ss",
1171 .sysc = &omap54xx_usb_otg_ss_sysc,
1172 };
1173
1174 /* usb_otg_ss */
1175 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1176 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1177 };
1178
1179 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1180 .name = "usb_otg_ss",
1181 .class = &omap54xx_usb_otg_ss_hwmod_class,
1182 .clkdm_name = "l3init_clkdm",
1183 .flags = HWMOD_SWSUP_SIDLE,
1184 .main_clk = "dpll_core_h13x2_ck",
1185 .prcm = {
1186 .omap4 = {
1187 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1188 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1189 .modulemode = MODULEMODE_HWCTRL,
1190 },
1191 },
1192 .opt_clks = usb_otg_ss_opt_clks,
1193 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1194 };
1195
1196
1197 /*
1198 * 'ocp2scp' class
1199 * bridge to transform ocp interface protocol to scp (serial control port)
1200 * protocol
1201 */
1202 /* ocp2scp3 */
1203 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
1204 /* l4_cfg -> ocp2scp3 */
1205 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
1206 .master = &omap54xx_l4_cfg_hwmod,
1207 .slave = &omap54xx_ocp2scp3_hwmod,
1208 .clk = "l4_root_clk_div",
1209 .user = OCP_USER_MPU | OCP_USER_SDMA,
1210 };
1211
1212 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
1213 .name = "ocp2scp3",
1214 .class = &omap54xx_ocp2scp_hwmod_class,
1215 .clkdm_name = "l3init_clkdm",
1216 .prcm = {
1217 .omap4 = {
1218 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1219 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1220 .modulemode = MODULEMODE_HWCTRL,
1221 },
1222 },
1223 };
1224
1225 /*
1226 * 'sata' class
1227 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
1228 */
1229
1230 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
1231 .rev_offs = 0x00fc,
1232 .sysc_offs = 0x0000,
1233 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1234 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1235 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1236 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1237 .sysc_fields = &omap_hwmod_sysc_type2,
1238 };
1239
1240 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
1241 .name = "sata",
1242 .sysc = &omap54xx_sata_sysc,
1243 };
1244
1245 /* sata */
1246 static struct omap_hwmod omap54xx_sata_hwmod = {
1247 .name = "sata",
1248 .class = &omap54xx_sata_hwmod_class,
1249 .clkdm_name = "l3init_clkdm",
1250 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1251 .main_clk = "func_48m_fclk",
1252 .mpu_rt_idx = 1,
1253 .prcm = {
1254 .omap4 = {
1255 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1256 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1257 .modulemode = MODULEMODE_SWCTRL,
1258 },
1259 },
1260 };
1261
1262 /* l4_cfg -> sata */
1263 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
1264 .master = &omap54xx_l4_cfg_hwmod,
1265 .slave = &omap54xx_sata_hwmod,
1266 .clk = "l3_iclk_div",
1267 .user = OCP_USER_MPU | OCP_USER_SDMA,
1268 };
1269
1270 /*
1271 * Interfaces
1272 */
1273
1274 /* l3_main_1 -> dmm */
1275 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1276 .master = &omap54xx_l3_main_1_hwmod,
1277 .slave = &omap54xx_dmm_hwmod,
1278 .clk = "l3_iclk_div",
1279 .user = OCP_USER_SDMA,
1280 };
1281
1282 /* l3_main_3 -> l3_instr */
1283 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1284 .master = &omap54xx_l3_main_3_hwmod,
1285 .slave = &omap54xx_l3_instr_hwmod,
1286 .clk = "l3_iclk_div",
1287 .user = OCP_USER_MPU | OCP_USER_SDMA,
1288 };
1289
1290 /* l3_main_2 -> l3_main_1 */
1291 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1292 .master = &omap54xx_l3_main_2_hwmod,
1293 .slave = &omap54xx_l3_main_1_hwmod,
1294 .clk = "l3_iclk_div",
1295 .user = OCP_USER_MPU | OCP_USER_SDMA,
1296 };
1297
1298 /* l4_cfg -> l3_main_1 */
1299 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1300 .master = &omap54xx_l4_cfg_hwmod,
1301 .slave = &omap54xx_l3_main_1_hwmod,
1302 .clk = "l3_iclk_div",
1303 .user = OCP_USER_MPU | OCP_USER_SDMA,
1304 };
1305
1306 /* l4_cfg -> mmu_dsp */
1307 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
1308 .master = &omap54xx_l4_cfg_hwmod,
1309 .slave = &omap54xx_mmu_dsp_hwmod,
1310 .clk = "l4_root_clk_div",
1311 .user = OCP_USER_MPU | OCP_USER_SDMA,
1312 };
1313
1314 /* mpu -> l3_main_1 */
1315 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1316 .master = &omap54xx_mpu_hwmod,
1317 .slave = &omap54xx_l3_main_1_hwmod,
1318 .clk = "l3_iclk_div",
1319 .user = OCP_USER_MPU,
1320 };
1321
1322 /* l3_main_1 -> l3_main_2 */
1323 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1324 .master = &omap54xx_l3_main_1_hwmod,
1325 .slave = &omap54xx_l3_main_2_hwmod,
1326 .clk = "l3_iclk_div",
1327 .user = OCP_USER_MPU,
1328 };
1329
1330 /* l4_cfg -> l3_main_2 */
1331 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1332 .master = &omap54xx_l4_cfg_hwmod,
1333 .slave = &omap54xx_l3_main_2_hwmod,
1334 .clk = "l3_iclk_div",
1335 .user = OCP_USER_MPU | OCP_USER_SDMA,
1336 };
1337
1338 /* l3_main_2 -> mmu_ipu */
1339 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
1340 .master = &omap54xx_l3_main_2_hwmod,
1341 .slave = &omap54xx_mmu_ipu_hwmod,
1342 .clk = "l3_iclk_div",
1343 .user = OCP_USER_MPU | OCP_USER_SDMA,
1344 };
1345
1346 /* l3_main_1 -> l3_main_3 */
1347 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1348 .master = &omap54xx_l3_main_1_hwmod,
1349 .slave = &omap54xx_l3_main_3_hwmod,
1350 .clk = "l3_iclk_div",
1351 .user = OCP_USER_MPU,
1352 };
1353
1354 /* l3_main_2 -> l3_main_3 */
1355 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1356 .master = &omap54xx_l3_main_2_hwmod,
1357 .slave = &omap54xx_l3_main_3_hwmod,
1358 .clk = "l3_iclk_div",
1359 .user = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* l4_cfg -> l3_main_3 */
1363 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1364 .master = &omap54xx_l4_cfg_hwmod,
1365 .slave = &omap54xx_l3_main_3_hwmod,
1366 .clk = "l3_iclk_div",
1367 .user = OCP_USER_MPU | OCP_USER_SDMA,
1368 };
1369
1370 /* l3_main_1 -> l4_abe */
1371 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1372 .master = &omap54xx_l3_main_1_hwmod,
1373 .slave = &omap54xx_l4_abe_hwmod,
1374 .clk = "abe_iclk",
1375 .user = OCP_USER_MPU | OCP_USER_SDMA,
1376 };
1377
1378 /* mpu -> l4_abe */
1379 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1380 .master = &omap54xx_mpu_hwmod,
1381 .slave = &omap54xx_l4_abe_hwmod,
1382 .clk = "abe_iclk",
1383 .user = OCP_USER_MPU | OCP_USER_SDMA,
1384 };
1385
1386 /* l3_main_1 -> l4_cfg */
1387 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1388 .master = &omap54xx_l3_main_1_hwmod,
1389 .slave = &omap54xx_l4_cfg_hwmod,
1390 .clk = "l4_root_clk_div",
1391 .user = OCP_USER_MPU | OCP_USER_SDMA,
1392 };
1393
1394 /* l3_main_2 -> l4_per */
1395 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1396 .master = &omap54xx_l3_main_2_hwmod,
1397 .slave = &omap54xx_l4_per_hwmod,
1398 .clk = "l4_root_clk_div",
1399 .user = OCP_USER_MPU | OCP_USER_SDMA,
1400 };
1401
1402 /* l3_main_1 -> l4_wkup */
1403 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1404 .master = &omap54xx_l3_main_1_hwmod,
1405 .slave = &omap54xx_l4_wkup_hwmod,
1406 .clk = "wkupaon_iclk_mux",
1407 .user = OCP_USER_MPU | OCP_USER_SDMA,
1408 };
1409
1410 /* mpu -> mpu_private */
1411 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1412 .master = &omap54xx_mpu_hwmod,
1413 .slave = &omap54xx_mpu_private_hwmod,
1414 .clk = "l3_iclk_div",
1415 .user = OCP_USER_MPU | OCP_USER_SDMA,
1416 };
1417
1418 /* l4_wkup -> counter_32k */
1419 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1420 .master = &omap54xx_l4_wkup_hwmod,
1421 .slave = &omap54xx_counter_32k_hwmod,
1422 .clk = "wkupaon_iclk_mux",
1423 .user = OCP_USER_MPU | OCP_USER_SDMA,
1424 };
1425
1426 /* l4_cfg -> dma_system */
1427 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1428 .master = &omap54xx_l4_cfg_hwmod,
1429 .slave = &omap54xx_dma_system_hwmod,
1430 .clk = "l4_root_clk_div",
1431 .user = OCP_USER_MPU | OCP_USER_SDMA,
1432 };
1433
1434 /* l4_abe -> dmic */
1435 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1436 .master = &omap54xx_l4_abe_hwmod,
1437 .slave = &omap54xx_dmic_hwmod,
1438 .clk = "abe_iclk",
1439 .user = OCP_USER_MPU,
1440 };
1441
1442 /* l3_main_2 -> dss */
1443 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
1444 .master = &omap54xx_l3_main_2_hwmod,
1445 .slave = &omap54xx_dss_hwmod,
1446 .clk = "l3_iclk_div",
1447 .user = OCP_USER_MPU | OCP_USER_SDMA,
1448 };
1449
1450 /* l3_main_2 -> dss_dispc */
1451 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
1452 .master = &omap54xx_l3_main_2_hwmod,
1453 .slave = &omap54xx_dss_dispc_hwmod,
1454 .clk = "l3_iclk_div",
1455 .user = OCP_USER_MPU | OCP_USER_SDMA,
1456 };
1457
1458 /* l3_main_2 -> dss_dsi1_a */
1459 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
1460 .master = &omap54xx_l3_main_2_hwmod,
1461 .slave = &omap54xx_dss_dsi1_a_hwmod,
1462 .clk = "l3_iclk_div",
1463 .user = OCP_USER_MPU | OCP_USER_SDMA,
1464 };
1465
1466 /* l3_main_2 -> dss_dsi1_c */
1467 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
1468 .master = &omap54xx_l3_main_2_hwmod,
1469 .slave = &omap54xx_dss_dsi1_c_hwmod,
1470 .clk = "l3_iclk_div",
1471 .user = OCP_USER_MPU | OCP_USER_SDMA,
1472 };
1473
1474 /* l3_main_2 -> dss_hdmi */
1475 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
1476 .master = &omap54xx_l3_main_2_hwmod,
1477 .slave = &omap54xx_dss_hdmi_hwmod,
1478 .clk = "l3_iclk_div",
1479 .user = OCP_USER_MPU | OCP_USER_SDMA,
1480 };
1481
1482 /* l3_main_2 -> dss_rfbi */
1483 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
1484 .master = &omap54xx_l3_main_2_hwmod,
1485 .slave = &omap54xx_dss_rfbi_hwmod,
1486 .clk = "l3_iclk_div",
1487 .user = OCP_USER_MPU | OCP_USER_SDMA,
1488 };
1489
1490 /* mpu -> emif1 */
1491 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1492 .master = &omap54xx_mpu_hwmod,
1493 .slave = &omap54xx_emif1_hwmod,
1494 .clk = "dpll_core_h11x2_ck",
1495 .user = OCP_USER_MPU | OCP_USER_SDMA,
1496 };
1497
1498 /* mpu -> emif2 */
1499 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1500 .master = &omap54xx_mpu_hwmod,
1501 .slave = &omap54xx_emif2_hwmod,
1502 .clk = "dpll_core_h11x2_ck",
1503 .user = OCP_USER_MPU | OCP_USER_SDMA,
1504 };
1505
1506 /* l4_wkup -> kbd */
1507 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1508 .master = &omap54xx_l4_wkup_hwmod,
1509 .slave = &omap54xx_kbd_hwmod,
1510 .clk = "wkupaon_iclk_mux",
1511 .user = OCP_USER_MPU | OCP_USER_SDMA,
1512 };
1513
1514 /* l4_abe -> mcpdm */
1515 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1516 .master = &omap54xx_l4_abe_hwmod,
1517 .slave = &omap54xx_mcpdm_hwmod,
1518 .clk = "abe_iclk",
1519 .user = OCP_USER_MPU,
1520 };
1521
1522 /* l4_cfg -> mpu */
1523 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1524 .master = &omap54xx_l4_cfg_hwmod,
1525 .slave = &omap54xx_mpu_hwmod,
1526 .clk = "l4_root_clk_div",
1527 .user = OCP_USER_MPU | OCP_USER_SDMA,
1528 };
1529
1530 /* l4_cfg -> spinlock */
1531 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
1532 .master = &omap54xx_l4_cfg_hwmod,
1533 .slave = &omap54xx_spinlock_hwmod,
1534 .clk = "l4_root_clk_div",
1535 .user = OCP_USER_MPU | OCP_USER_SDMA,
1536 };
1537
1538 /* l4_cfg -> ocp2scp1 */
1539 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
1540 .master = &omap54xx_l4_cfg_hwmod,
1541 .slave = &omap54xx_ocp2scp1_hwmod,
1542 .clk = "l4_root_clk_div",
1543 .user = OCP_USER_MPU | OCP_USER_SDMA,
1544 };
1545
1546 /* l4_wkup -> timer1 */
1547 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1548 .master = &omap54xx_l4_wkup_hwmod,
1549 .slave = &omap54xx_timer1_hwmod,
1550 .clk = "wkupaon_iclk_mux",
1551 .user = OCP_USER_MPU | OCP_USER_SDMA,
1552 };
1553
1554 /* l4_per -> timer2 */
1555 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1556 .master = &omap54xx_l4_per_hwmod,
1557 .slave = &omap54xx_timer2_hwmod,
1558 .clk = "l4_root_clk_div",
1559 .user = OCP_USER_MPU | OCP_USER_SDMA,
1560 };
1561
1562 /* l4_per -> timer3 */
1563 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1564 .master = &omap54xx_l4_per_hwmod,
1565 .slave = &omap54xx_timer3_hwmod,
1566 .clk = "l4_root_clk_div",
1567 .user = OCP_USER_MPU | OCP_USER_SDMA,
1568 };
1569
1570 /* l4_per -> timer4 */
1571 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1572 .master = &omap54xx_l4_per_hwmod,
1573 .slave = &omap54xx_timer4_hwmod,
1574 .clk = "l4_root_clk_div",
1575 .user = OCP_USER_MPU | OCP_USER_SDMA,
1576 };
1577
1578 /* l4_abe -> timer5 */
1579 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1580 .master = &omap54xx_l4_abe_hwmod,
1581 .slave = &omap54xx_timer5_hwmod,
1582 .clk = "abe_iclk",
1583 .user = OCP_USER_MPU,
1584 };
1585
1586 /* l4_abe -> timer6 */
1587 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1588 .master = &omap54xx_l4_abe_hwmod,
1589 .slave = &omap54xx_timer6_hwmod,
1590 .clk = "abe_iclk",
1591 .user = OCP_USER_MPU,
1592 };
1593
1594 /* l4_abe -> timer7 */
1595 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1596 .master = &omap54xx_l4_abe_hwmod,
1597 .slave = &omap54xx_timer7_hwmod,
1598 .clk = "abe_iclk",
1599 .user = OCP_USER_MPU,
1600 };
1601
1602 /* l4_abe -> timer8 */
1603 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1604 .master = &omap54xx_l4_abe_hwmod,
1605 .slave = &omap54xx_timer8_hwmod,
1606 .clk = "abe_iclk",
1607 .user = OCP_USER_MPU,
1608 };
1609
1610 /* l4_per -> timer9 */
1611 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1612 .master = &omap54xx_l4_per_hwmod,
1613 .slave = &omap54xx_timer9_hwmod,
1614 .clk = "l4_root_clk_div",
1615 .user = OCP_USER_MPU | OCP_USER_SDMA,
1616 };
1617
1618 /* l4_per -> timer10 */
1619 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1620 .master = &omap54xx_l4_per_hwmod,
1621 .slave = &omap54xx_timer10_hwmod,
1622 .clk = "l4_root_clk_div",
1623 .user = OCP_USER_MPU | OCP_USER_SDMA,
1624 };
1625
1626 /* l4_per -> timer11 */
1627 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
1628 .master = &omap54xx_l4_per_hwmod,
1629 .slave = &omap54xx_timer11_hwmod,
1630 .clk = "l4_root_clk_div",
1631 .user = OCP_USER_MPU | OCP_USER_SDMA,
1632 };
1633
1634 /* l4_cfg -> usb_host_hs */
1635 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
1636 .master = &omap54xx_l4_cfg_hwmod,
1637 .slave = &omap54xx_usb_host_hs_hwmod,
1638 .clk = "l3_iclk_div",
1639 .user = OCP_USER_MPU | OCP_USER_SDMA,
1640 };
1641
1642 /* l4_cfg -> usb_tll_hs */
1643 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
1644 .master = &omap54xx_l4_cfg_hwmod,
1645 .slave = &omap54xx_usb_tll_hs_hwmod,
1646 .clk = "l4_root_clk_div",
1647 .user = OCP_USER_MPU | OCP_USER_SDMA,
1648 };
1649
1650 /* l4_cfg -> usb_otg_ss */
1651 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
1652 .master = &omap54xx_l4_cfg_hwmod,
1653 .slave = &omap54xx_usb_otg_ss_hwmod,
1654 .clk = "dpll_core_h13x2_ck",
1655 .user = OCP_USER_MPU | OCP_USER_SDMA,
1656 };
1657
1658 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
1659 &omap54xx_l3_main_1__dmm,
1660 &omap54xx_l3_main_3__l3_instr,
1661 &omap54xx_l3_main_2__l3_main_1,
1662 &omap54xx_l4_cfg__l3_main_1,
1663 &omap54xx_mpu__l3_main_1,
1664 &omap54xx_l3_main_1__l3_main_2,
1665 &omap54xx_l4_cfg__l3_main_2,
1666 &omap54xx_l3_main_1__l3_main_3,
1667 &omap54xx_l3_main_2__l3_main_3,
1668 &omap54xx_l4_cfg__l3_main_3,
1669 &omap54xx_l3_main_1__l4_abe,
1670 &omap54xx_mpu__l4_abe,
1671 &omap54xx_l3_main_1__l4_cfg,
1672 &omap54xx_l3_main_2__l4_per,
1673 &omap54xx_l3_main_1__l4_wkup,
1674 &omap54xx_mpu__mpu_private,
1675 &omap54xx_l4_wkup__counter_32k,
1676 &omap54xx_l4_cfg__dma_system,
1677 &omap54xx_l4_abe__dmic,
1678 &omap54xx_l4_cfg__mmu_dsp,
1679 &omap54xx_l3_main_2__dss,
1680 &omap54xx_l3_main_2__dss_dispc,
1681 &omap54xx_l3_main_2__dss_dsi1_a,
1682 &omap54xx_l3_main_2__dss_dsi1_c,
1683 &omap54xx_l3_main_2__dss_hdmi,
1684 &omap54xx_l3_main_2__dss_rfbi,
1685 &omap54xx_mpu__emif1,
1686 &omap54xx_mpu__emif2,
1687 &omap54xx_l3_main_2__mmu_ipu,
1688 &omap54xx_l4_wkup__kbd,
1689 &omap54xx_l4_abe__mcpdm,
1690 &omap54xx_l4_cfg__mpu,
1691 &omap54xx_l4_cfg__spinlock,
1692 &omap54xx_l4_cfg__ocp2scp1,
1693 &omap54xx_l4_wkup__timer1,
1694 &omap54xx_l4_per__timer2,
1695 &omap54xx_l4_per__timer3,
1696 &omap54xx_l4_per__timer4,
1697 &omap54xx_l4_abe__timer5,
1698 &omap54xx_l4_abe__timer6,
1699 &omap54xx_l4_abe__timer7,
1700 &omap54xx_l4_abe__timer8,
1701 &omap54xx_l4_per__timer9,
1702 &omap54xx_l4_per__timer10,
1703 &omap54xx_l4_per__timer11,
1704 &omap54xx_l4_cfg__usb_host_hs,
1705 &omap54xx_l4_cfg__usb_tll_hs,
1706 &omap54xx_l4_cfg__usb_otg_ss,
1707 &omap54xx_l4_cfg__ocp2scp3,
1708 &omap54xx_l4_cfg__sata,
1709 NULL,
1710 };
1711
1712 int __init omap54xx_hwmod_init(void)
1713 {
1714 omap_hwmod_init();
1715 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
1716 }
Linux with added FPC-III support