arch/arm/mach-s3c24xx/include/mach/regs-lcd.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  */
   6
   7 #ifndef ___ASM_ARCH_REGS_LCD_H
   8 #define ___ASM_ARCH_REGS_LCD_H
   9
  10 #define S3C2410_LCDREG(x)       (x)
  11
  12 /* LCD control registers */
  13 #define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
  14 #define S3C2410_LCDCON2     S3C2410_LCDREG(0x04)
  15 #define S3C2410_LCDCON3     S3C2410_LCDREG(0x08)
  16 #define S3C2410_LCDCON4     S3C2410_LCDREG(0x0C)
  17 #define S3C2410_LCDCON5     S3C2410_LCDREG(0x10)
  18
  19 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
  20 #define S3C2410_LCDCON1_MMODE      (1<<7)
  21 #define S3C2410_LCDCON1_DSCAN4     (0<<5)
  22 #define S3C2410_LCDCON1_STN4       (1<<5)
  23 #define S3C2410_LCDCON1_STN8       (2<<5)
  24 #define S3C2410_LCDCON1_TFT        (3<<5)
  25
  26 #define S3C2410_LCDCON1_STN1BPP    (0<<1)
  27 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
  28 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
  29 #define S3C2410_LCDCON1_STN8BPP    (3<<1)
  30 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
  31
  32 #define S3C2410_LCDCON1_TFT1BPP    (8<<1)
  33 #define S3C2410_LCDCON1_TFT2BPP    (9<<1)
  34 #define S3C2410_LCDCON1_TFT4BPP    (10<<1)
  35 #define S3C2410_LCDCON1_TFT8BPP    (11<<1)
  36 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
  37 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
  38
  39 #define S3C2410_LCDCON1_ENVID      (1)
  40
  41 #define S3C2410_LCDCON1_MODEMASK    0x1E
  42
  43 #define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
  44 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
  45 #define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
  46 #define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
  47
  48 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
  49 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
  50 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
  51
  52 #define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
  53 #define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
  54 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
  55 #define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
  56 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
  57
  58 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
  59 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
  60
  61 /* LDCCON4 changes for STN mode on the S3C2412 */
  62
  63 #define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
  64 #define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
  65 #define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
  66
  67 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
  68
  69 #define S3C2410_LCDCON5_BPP24BL     (1<<12)
  70 #define S3C2410_LCDCON5_FRM565      (1<<11)
  71 #define S3C2410_LCDCON5_INVVCLK     (1<<10)
  72 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
  73 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
  74 #define S3C2410_LCDCON5_INVVD       (1<<7)
  75 #define S3C2410_LCDCON5_INVVDEN     (1<<6)
  76 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
  77 #define S3C2410_LCDCON5_INVLEND     (1<<4)
  78 #define S3C2410_LCDCON5_PWREN       (1<<3)
  79 #define S3C2410_LCDCON5_ENLEND      (1<<2)
  80 #define S3C2410_LCDCON5_BSWP        (1<<1)
  81 #define S3C2410_LCDCON5_HWSWP       (1<<0)
  82
  83 /* framebuffer start addressed */
  84 #define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
  85 #define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
  86 #define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
  87
  88 #define S3C2410_LCDBANK(x)      ((x) << 21)
  89 #define S3C2410_LCDBASEU(x)     (x)
  90
  91 #define S3C2410_OFFSIZE(x)      ((x) << 11)
  92 #define S3C2410_PAGEWIDTH(x)    (x)
  93
  94 /* colour lookup and miscellaneous controls */
  95
  96 #define S3C2410_REDLUT     S3C2410_LCDREG(0x20)
  97 #define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
  98 #define S3C2410_BLUELUT    S3C2410_LCDREG(0x28)
  99
 100 #define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
 101 #define S3C2410_TPAL       S3C2410_LCDREG(0x50)
 102
 103 #define S3C2410_TPAL_EN         (1<<24)
 104
 105 /* interrupt info */
 106 #define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
 107 #define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
 108 #define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
 109 #define S3C2410_LCDINT_FIWSEL   (1<<2)
 110 #define S3C2410_LCDINT_FRSYNC   (1<<1)
 111 #define S3C2410_LCDINT_FICNT    (1<<0)
 112
 113 /* s3c2442 extra stn registers */
 114
 115 #define S3C2442_REDLUT          S3C2410_LCDREG(0x20)
 116 #define S3C2442_GREENLUT        S3C2410_LCDREG(0x24)
 117 #define S3C2442_BLUELUT         S3C2410_LCDREG(0x28)
 118 #define S3C2442_DITHMODE        S3C2410_LCDREG(0x20)
 119
 120 #define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
 121
 122 #define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
 123
 124 /* S3C2412 registers */
 125
 126 #define S3C2412_TPAL            S3C2410_LCDREG(0x20)
 127
 128 #define S3C2412_LCDINTPND       S3C2410_LCDREG(0x24)
 129 #define S3C2412_LCDSRCPND       S3C2410_LCDREG(0x28)
 130 #define S3C2412_LCDINTMSK       S3C2410_LCDREG(0x2C)
 131
 132 #define S3C2412_TCONSEL         S3C2410_LCDREG(0x30)
 133
 134 #define S3C2412_LCDCON6         S3C2410_LCDREG(0x34)
 135 #define S3C2412_LCDCON7         S3C2410_LCDREG(0x38)
 136 #define S3C2412_LCDCON8         S3C2410_LCDREG(0x3C)
 137 #define S3C2412_LCDCON9         S3C2410_LCDREG(0x40)
 138
 139 #define S3C2412_REDLUT(x)       S3C2410_LCDREG(0x44 + ((x)*4))
 140 #define S3C2412_GREENLUT(x)     S3C2410_LCDREG(0x60 + ((x)*4))
 141 #define S3C2412_BLUELUT(x)      S3C2410_LCDREG(0x98 + ((x)*4))
 142
 143 #define S3C2412_FRCPAT(x)       S3C2410_LCDREG(0xB4 + ((x)*4))
 144
 145 /* general registers */
 146
 147 /* base of the LCD registers, where INTPND, INTSRC and then INTMSK
 148  * are available. */
 149
 150 #define S3C2410_LCDINTBASE      S3C2410_LCDREG(0x54)
 151 #define S3C2412_LCDINTBASE      S3C2410_LCDREG(0x24)
 152
 153 #define S3C24XX_LCDINTPND       (0x00)
 154 #define S3C24XX_LCDSRCPND       (0x04)
 155 #define S3C24XX_LCDINTMSK       (0x08)
 156
 157 #endif /* ___ASM_ARCH_REGS_LCD_H */