| blob | 3341a12bbb9ccc3d997ab89aee9e51353a8e8e41 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 */
6 #include <linux/linkage.h>
8 #include <soc/tegra/flowctrl.h>
9 #include <soc/tegra/fuse.h>
11 #include <asm/asm-offsets.h>
12 #include <asm/assembler.h>
13 #include <asm/cache.h>
15 #include "irammap.h"
16 #include "sleep.h"
18 #define EMC_CFG 0xc
19 #define EMC_ADR_CFG 0x10
20 #define EMC_TIMING_CONTROL 0x28
21 #define EMC_NOP 0xdc
22 #define EMC_SELF_REF 0xe0
23 #define EMC_MRW 0xe8
24 #define EMC_FBIO_CFG5 0x104
25 #define EMC_AUTO_CAL_CONFIG 0x2a4
26 #define EMC_AUTO_CAL_INTERVAL 0x2a8
27 #define EMC_AUTO_CAL_STATUS 0x2ac
28 #define EMC_REQ_CTRL 0x2b0
29 #define EMC_CFG_DIG_DLL 0x2bc
30 #define EMC_EMC_STATUS 0x2b4
31 #define EMC_ZCAL_INTERVAL 0x2e0
32 #define EMC_ZQ_CAL 0x2ec
33 #define EMC_XM2VTTGENPADCTRL 0x310
34 #define EMC_XM2VTTGENPADCTRL2 0x314
36 #define PMC_CTRL 0x0
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
39 #define PMC_PLLP_WB0_OVERRIDE 0xf8
40 #define PMC_IO_DPD_REQ 0x1b8
41 #define PMC_IO_DPD_STATUS 0x1bc
43 #define CLK_RESET_CCLK_BURST 0x20
44 #define CLK_RESET_CCLK_DIVIDER 0x24
45 #define CLK_RESET_SCLK_BURST 0x28
46 #define CLK_RESET_SCLK_DIVIDER 0x2c
48 #define CLK_RESET_PLLC_BASE 0x80
49 #define CLK_RESET_PLLC_MISC 0x8c
50 #define CLK_RESET_PLLM_BASE 0x90
51 #define CLK_RESET_PLLM_MISC 0x9c
52 #define CLK_RESET_PLLP_BASE 0xa0
53 #define CLK_RESET_PLLP_MISC 0xac
54 #define CLK_RESET_PLLA_BASE 0xb0
55 #define CLK_RESET_PLLA_MISC 0xbc
56 #define CLK_RESET_PLLX_BASE 0xe0
57 #define CLK_RESET_PLLX_MISC 0xe4
58 #define CLK_RESET_PLLX_MISC3 0x518
59 #define CLK_RESET_PLLX_MISC3_IDDQ 3
60 #define CLK_RESET_PLLM_MISC_IDDQ 5
61 #define CLK_RESET_PLLC_MISC_IDDQ 26
63 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
65 #define MSELECT_CLKM (0x3 << 30)
67 #define LOCK_DELAY 50 /* safety delay after lock is detected */
69 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
71 .macro emc_device_mask, rd, base
72 ldr \rd, [\base, #EMC_ADR_CFG]
73 tst \rd, #0x1
74 moveq \rd, #(0x1 << 8) @ just 1 device
75 movne \rd, #(0x3 << 8) @ 2 devices
76 .endm
78 .macro emc_timing_update, rd, base
79 mov \rd, #1
80 str \rd, [\base, #EMC_TIMING_CONTROL]
81 1001:
82 ldr \rd, [\base, #EMC_EMC_STATUS]
83 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
84 bne 1001b
85 .endm
87 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
88 ldr \rd, [\r_car_base, #\pll_base]
89 tst \rd, #(1 << 30)
90 orreq \rd, \rd, #(1 << 30)
91 streq \rd, [\r_car_base, #\pll_base]
92 /* Enable lock detector */
93 .if \pll_misc
94 ldr \rd, [\r_car_base, #\pll_misc]
95 bic \rd, \rd, #(1 << 18)
96 str \rd, [\r_car_base, #\pll_misc]
97 ldr \rd, [\r_car_base, #\pll_misc]
98 ldr \rd, [\r_car_base, #\pll_misc]
99 orr \rd, \rd, #(1 << 18)
100 str \rd, [\r_car_base, #\pll_misc]
101 .endif
102 .endm
104 .macro pll_locked, rd, r_car_base, pll_base
105 1:
106 ldr \rd, [\r_car_base, #\pll_base]
107 tst \rd, #(1 << 27)
108 beq 1b
109 .endm
111 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
112 ldr \rd, [\car, #\iddq]
113 bic \rd, \rd, #(1<<\iddq_bit)
114 str \rd, [\car, #\iddq]
115 .endm
117 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
118 ldr \rd, [\car, #\iddq]
119 orr \rd, \rd, #(1<<\iddq_bit)
120 str \rd, [\car, #\iddq]
121 .endm
123 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
124 /*
125 * tegra30_hotplug_shutdown(void)
126 *
127 * Powergates the current CPU.
128 * Should never return.
129 */
130 ENTRY(tegra30_hotplug_shutdown)
131 /* Powergate this CPU */
132 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
133 bl tegra30_cpu_shutdown
134 ret lr @ should never get here
135 ENDPROC(tegra30_hotplug_shutdown)
137 /*
138 * tegra30_cpu_shutdown(unsigned long flags)
139 *
140 * Puts the current CPU in wait-for-event mode on the flow controller
141 * and powergates it -- flags (in R0) indicate the request type.
142 *
143 * r10 = SoC ID
144 * corrupts r0-r4, r10-r12
145 */
146 ENTRY(tegra30_cpu_shutdown)
147 cpu_id r3
148 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
149 cmp r10, #TEGRA30
150 bne _no_cpu0_chk @ It's not Tegra30
152 cmp r3, #0
153 reteq lr @ Must never be called for CPU 0
154 _no_cpu0_chk:
156 ldr r12, =TEGRA_FLOW_CTRL_VIRT
157 cpu_to_csr_reg r1, r3
158 add r1, r1, r12 @ virtual CSR address for this CPU
159 cpu_to_halt_reg r2, r3
160 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
162 /*
163 * Clear this CPU's "event" and "interrupt" flags and power gate
164 * it when halting but not before it is in the "WFE" state.
165 */
166 movw r12, \
167 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
168 FLOW_CTRL_CSR_ENABLE
169 cmp r10, #TEGRA30
170 moveq r4, #(1 << 4) @ wfe bitmap
171 movne r4, #(1 << 8) @ wfi bitmap
172 ARM( orr r12, r12, r4, lsl r3 )
173 THUMB( lsl r4, r4, r3 )
174 THUMB( orr r12, r12, r4 )
175 str r12, [r1]
177 /* Halt this CPU. */
178 mov r3, #0x400
179 delay_1:
180 subs r3, r3, #1 @ delay as a part of wfe war.
181 bge delay_1;
182 cpsid a @ disable imprecise aborts.
183 ldr r3, [r1] @ read CSR
184 str r3, [r1] @ clear CSR
186 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
187 beq flow_ctrl_setting_for_lp2
189 /* flow controller set up for hotplug */
190 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
191 b flow_ctrl_done
192 flow_ctrl_setting_for_lp2:
193 /* flow controller set up for LP2 */
194 cmp r10, #TEGRA30
195 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
196 movne r3, #FLOW_CTRL_WAITEVENT
197 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
198 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
199 flow_ctrl_done:
200 cmp r10, #TEGRA30
201 str r3, [r2]
202 ldr r0, [r2]
203 b wfe_war
205 __cpu_reset_again:
206 dsb
207 .align 5
208 wfeeq @ CPU should be power gated here
209 wfine
210 wfe_war:
211 b __cpu_reset_again
213 /*
214 * 38 nop's, which fills rest of wfe cache line and
215 * 4 more cachelines with nop
216 */
217 .rept 38
218 nop
219 .endr
220 b . @ should never get here
222 ENDPROC(tegra30_cpu_shutdown)
223 #endif
225 #ifdef CONFIG_PM_SLEEP
226 /*
227 * tegra30_sleep_core_finish(unsigned long v2p)
228 *
229 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
230 * tegra30_tear_down_core in IRAM
231 */
232 ENTRY(tegra30_sleep_core_finish)
233 mov r4, r0
234 /* Flush, disable the L1 data cache and exit SMP */
235 mov r0, #TEGRA_FLUSH_CACHE_ALL
236 bl tegra_disable_clean_inv_dcache
237 mov r0, r4
239 /*
240 * Preload all the address literals that are needed for the
241 * CPU power-gating process, to avoid loading from SDRAM which
242 * are not supported once SDRAM is put into self-refresh.
243 * LP0 / LP1 use physical address, since the MMU needs to be
244 * disabled before putting SDRAM into self-refresh to avoid
245 * memory access due to page table walks.
246 */
247 mov32 r4, TEGRA_PMC_BASE
248 mov32 r5, TEGRA_CLK_RESET_BASE
249 mov32 r6, TEGRA_FLOW_CTRL_BASE
250 mov32 r7, TEGRA_TMRUS_BASE
252 mov32 r3, tegra_shut_off_mmu
253 add r3, r3, r0
255 mov32 r0, tegra30_tear_down_core
256 mov32 r1, tegra30_iram_start
257 sub r0, r0, r1
258 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
259 add r0, r0, r1
261 ret r3
262 ENDPROC(tegra30_sleep_core_finish)
264 /*
265 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
266 *
267 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
268 */
269 ENTRY(tegra30_sleep_cpu_secondary_finish)
270 mov r7, lr
272 /* Flush and disable the L1 data cache */
273 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
274 bl tegra_disable_clean_inv_dcache
276 /* Powergate this CPU. */
277 mov r0, #0 @ power mode flags (!hotplug)
278 bl tegra30_cpu_shutdown
279 mov r0, #1 @ never return here
280 ret r7
281 ENDPROC(tegra30_sleep_cpu_secondary_finish)
283 /*
284 * tegra30_tear_down_cpu
285 *
286 * Switches the CPU to enter sleep.
287 */
288 ENTRY(tegra30_tear_down_cpu)
289 mov32 r6, TEGRA_FLOW_CTRL_BASE
291 b tegra30_enter_sleep
292 ENDPROC(tegra30_tear_down_cpu)
294 /* START OF ROUTINES COPIED TO IRAM */
295 .align L1_CACHE_SHIFT
296 .globl tegra30_iram_start
297 tegra30_iram_start:
299 /*
300 * tegra30_lp1_reset
301 *
302 * reset vector for LP1 restore; copied into IRAM during suspend.
303 * Brings the system back up to a safe staring point (SDRAM out of
304 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
305 * system clock running on the same PLL that it suspended at), and
306 * jumps to tegra_resume to restore virtual addressing.
307 * The physical address of tegra_resume expected to be stored in
308 * PMC_SCRATCH41.
309 *
310 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
311 */
312 ENTRY(tegra30_lp1_reset)
313 /*
314 * The CPU and system bus are running at 32KHz and executing from
315 * IRAM when this code is executed; immediately switch to CLKM and
316 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
317 */
318 mov32 r0, TEGRA_CLK_RESET_BASE
320 mov r1, #(1 << 28)
321 str r1, [r0, #CLK_RESET_SCLK_BURST]
322 str r1, [r0, #CLK_RESET_CCLK_BURST]
323 mov r1, #0
324 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
325 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
327 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
328 cmp r10, #TEGRA30
329 beq _no_pll_iddq_exit
331 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
332 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
333 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
335 mov32 r7, TEGRA_TMRUS_BASE
336 ldr r1, [r7]
337 add r1, r1, #2
338 wait_until r1, r7, r3
340 /* enable PLLM via PMC */
341 mov32 r2, TEGRA_PMC_BASE
342 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
343 orr r1, r1, #(1 << 12)
344 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
346 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
347 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
348 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
350 b _pll_m_c_x_done
352 _no_pll_iddq_exit:
353 /* enable PLLM via PMC */
354 mov32 r2, TEGRA_PMC_BASE
355 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
356 orr r1, r1, #(1 << 12)
357 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
360 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
361 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
363 _pll_m_c_x_done:
364 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
365 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
367 pll_locked r1, r0, CLK_RESET_PLLM_BASE
368 pll_locked r1, r0, CLK_RESET_PLLP_BASE
369 pll_locked r1, r0, CLK_RESET_PLLA_BASE
370 pll_locked r1, r0, CLK_RESET_PLLC_BASE
371 pll_locked r1, r0, CLK_RESET_PLLX_BASE
373 mov32 r7, TEGRA_TMRUS_BASE
374 ldr r1, [r7]
375 add r1, r1, #LOCK_DELAY
376 wait_until r1, r7, r3
378 adr r5, tegra_sdram_pad_save
380 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
381 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
383 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
384 str r4, [r0, #CLK_RESET_SCLK_BURST]
386 cmp r10, #TEGRA30
387 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
388 movteq r4, #:upper16:((1 << 28) | (0x8))
389 movwne r4, #:lower16:((1 << 28) | (0xe))
390 movtne r4, #:upper16:((1 << 28) | (0xe))
391 str r4, [r0, #CLK_RESET_CCLK_BURST]
393 /* Restore pad power state to normal */
394 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
395 mvn r1, r1
396 bic r1, r1, #(1 << 31)
397 orr r1, r1, #(1 << 30)
398 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
400 cmp r10, #TEGRA30
401 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
402 movteq r0, #:upper16:TEGRA_EMC_BASE
403 cmp r10, #TEGRA114
404 movweq r0, #:lower16:TEGRA_EMC0_BASE
405 movteq r0, #:upper16:TEGRA_EMC0_BASE
406 cmp r10, #TEGRA124
407 movweq r0, #:lower16:TEGRA124_EMC_BASE
408 movteq r0, #:upper16:TEGRA124_EMC_BASE
410 exit_self_refresh:
411 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
412 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
413 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
414 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
415 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
416 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
418 /* Relock DLL */
419 ldr r1, [r0, #EMC_CFG_DIG_DLL]
420 orr r1, r1, #(1 << 30) @ set DLL_RESET
421 str r1, [r0, #EMC_CFG_DIG_DLL]
423 emc_timing_update r1, r0
425 cmp r10, #TEGRA114
426 movweq r1, #:lower16:TEGRA_EMC1_BASE
427 movteq r1, #:upper16:TEGRA_EMC1_BASE
428 cmpeq r0, r1
430 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
431 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
432 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
433 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
435 emc_wait_auto_cal_onetime:
436 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
437 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
438 bne emc_wait_auto_cal_onetime
440 ldr r1, [r0, #EMC_CFG]
441 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
442 str r1, [r0, #EMC_CFG]
444 mov r1, #0
445 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
446 mov r1, #1
447 cmp r10, #TEGRA30
448 streq r1, [r0, #EMC_NOP]
449 streq r1, [r0, #EMC_NOP]
451 emc_device_mask r1, r0
453 exit_selfrefresh_loop:
454 ldr r2, [r0, #EMC_EMC_STATUS]
455 ands r2, r2, r1
456 bne exit_selfrefresh_loop
458 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
460 mov32 r7, TEGRA_TMRUS_BASE
461 ldr r2, [r0, #EMC_FBIO_CFG5]
463 and r2, r2, #3 @ check DRAM_TYPE
464 cmp r2, #2
465 beq emc_lpddr2
467 /* Issue a ZQ_CAL for dev0 - DDR3 */
468 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
469 str r2, [r0, #EMC_ZQ_CAL]
470 ldr r2, [r7]
471 add r2, r2, #10
472 wait_until r2, r7, r3
474 tst r1, #2
475 beq zcal_done
477 /* Issue a ZQ_CAL for dev1 - DDR3 */
478 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
479 str r2, [r0, #EMC_ZQ_CAL]
480 ldr r2, [r7]
481 add r2, r2, #10
482 wait_until r2, r7, r3
483 b zcal_done
485 emc_lpddr2:
486 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
487 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
488 str r2, [r0, #EMC_MRW]
489 ldr r2, [r7]
490 add r2, r2, #1
491 wait_until r2, r7, r3
493 tst r1, #2
494 beq zcal_done
496 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
497 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
498 str r2, [r0, #EMC_MRW]
499 ldr r2, [r7]
500 add r2, r2, #1
501 wait_until r2, r7, r3
503 zcal_done:
504 mov r1, #0 @ unstall all transactions
505 str r1, [r0, #EMC_REQ_CTRL]
506 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
507 str r1, [r0, #EMC_ZCAL_INTERVAL]
508 ldr r1, [r5, #0x0] @ restore EMC_CFG
509 str r1, [r0, #EMC_CFG]
511 emc_timing_update r1, r0
513 /* Tegra114 had dual EMC channel, now config the other one */
514 cmp r10, #TEGRA114
515 bne __no_dual_emc_chanl
516 mov32 r1, TEGRA_EMC1_BASE
517 cmp r0, r1
518 movne r0, r1
519 addne r5, r5, #0x20
520 bne exit_self_refresh
521 __no_dual_emc_chanl:
523 mov32 r0, TEGRA_PMC_BASE
524 ldr r0, [r0, #PMC_SCRATCH41]
525 ret r0 @ jump to tegra_resume
526 ENDPROC(tegra30_lp1_reset)
528 .align L1_CACHE_SHIFT
529 tegra30_sdram_pad_address:
530 .word TEGRA_EMC_BASE + EMC_CFG @0x0
531 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
532 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
533 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
534 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
535 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
536 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
537 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
538 tegra30_sdram_pad_address_end:
540 tegra114_sdram_pad_address:
541 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
542 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
543 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
544 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
545 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
546 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
547 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
548 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
549 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
550 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
551 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
552 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
553 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
554 tegra114_sdram_pad_adress_end:
556 tegra124_sdram_pad_address:
557 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
558 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
559 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
560 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
561 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
562 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
563 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
564 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
565 tegra124_sdram_pad_address_end:
567 tegra30_sdram_pad_size:
568 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
570 tegra114_sdram_pad_size:
571 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
573 .type tegra_sdram_pad_save, %object
574 tegra_sdram_pad_save:
575 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
576 .long 0
577 .endr
579 /*
580 * tegra30_tear_down_core
581 *
582 * copied into and executed from IRAM
583 * puts memory in self-refresh for LP0 and LP1
584 */
585 tegra30_tear_down_core:
586 bl tegra30_sdram_self_refresh
587 bl tegra30_switch_cpu_to_clk32k
588 b tegra30_enter_sleep
590 /*
591 * tegra30_switch_cpu_to_clk32k
592 *
593 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
594 * to the 32KHz clock.
595 * r4 = TEGRA_PMC_BASE
596 * r5 = TEGRA_CLK_RESET_BASE
597 * r6 = TEGRA_FLOW_CTRL_BASE
598 * r7 = TEGRA_TMRUS_BASE
599 * r10= SoC ID
600 */
601 tegra30_switch_cpu_to_clk32k:
602 /*
603 * start by jumping to CLKM to safely disable PLLs, then jump to
604 * CLKS.
605 */
606 mov r0, #(1 << 28)
607 str r0, [r5, #CLK_RESET_SCLK_BURST]
608 /* 2uS delay delay between changing SCLK and CCLK */
609 ldr r1, [r7]
610 add r1, r1, #2
611 wait_until r1, r7, r9
612 str r0, [r5, #CLK_RESET_CCLK_BURST]
613 mov r0, #0
614 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
615 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
617 /* switch the clock source of mselect to be CLK_M */
618 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
619 orr r0, r0, #MSELECT_CLKM
620 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
622 /* 2uS delay delay between changing SCLK and disabling PLLs */
623 ldr r1, [r7]
624 add r1, r1, #2
625 wait_until r1, r7, r9
627 /* disable PLLM via PMC in LP1 */
628 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
629 bic r0, r0, #(1 << 12)
630 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
632 /* disable PLLP, PLLA, PLLC and PLLX */
633 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
634 bic r0, r0, #(1 << 30)
635 str r0, [r5, #CLK_RESET_PLLP_BASE]
636 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
637 bic r0, r0, #(1 << 30)
638 str r0, [r5, #CLK_RESET_PLLA_BASE]
639 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
640 bic r0, r0, #(1 << 30)
641 str r0, [r5, #CLK_RESET_PLLC_BASE]
642 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
643 bic r0, r0, #(1 << 30)
644 str r0, [r5, #CLK_RESET_PLLX_BASE]
646 cmp r10, #TEGRA30
647 beq _no_pll_in_iddq
648 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
649 _no_pll_in_iddq:
651 /* switch to CLKS */
652 mov r0, #0 /* brust policy = 32KHz */
653 str r0, [r5, #CLK_RESET_SCLK_BURST]
655 ret lr
657 /*
658 * tegra30_enter_sleep
659 *
660 * uses flow controller to enter sleep state
661 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
662 * executes from SDRAM with target state is LP2
663 * r6 = TEGRA_FLOW_CTRL_BASE
664 */
665 tegra30_enter_sleep:
666 cpu_id r1
668 cpu_to_csr_reg r2, r1
669 ldr r0, [r6, r2]
670 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
671 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
672 str r0, [r6, r2]
674 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
675 cmp r10, #TEGRA30
676 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
677 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
678 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
680 cpu_to_halt_reg r2, r1
681 str r0, [r6, r2]
682 dsb
683 ldr r0, [r6, r2] /* memory barrier */
685 cmp r10, #TEGRA30
686 halted:
687 isb
688 dsb
689 wfine /* CPU should be power gated here */
690 wfeeq
692 /* !!!FIXME!!! Implement halt failure handler */
693 b halted
695 /*
696 * tegra30_sdram_self_refresh
697 *
698 * called with MMU off and caches disabled
699 * must be executed from IRAM
700 * r4 = TEGRA_PMC_BASE
701 * r5 = TEGRA_CLK_RESET_BASE
702 * r6 = TEGRA_FLOW_CTRL_BASE
703 * r7 = TEGRA_TMRUS_BASE
704 * r10= SoC ID
705 */
706 tegra30_sdram_self_refresh:
708 adr r8, tegra_sdram_pad_save
709 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
710 cmp r10, #TEGRA30
711 adreq r2, tegra30_sdram_pad_address
712 ldreq r3, tegra30_sdram_pad_size
713 cmp r10, #TEGRA114
714 adreq r2, tegra114_sdram_pad_address
715 ldreq r3, tegra114_sdram_pad_size
716 cmp r10, #TEGRA124
717 adreq r2, tegra124_sdram_pad_address
718 ldreq r3, tegra30_sdram_pad_size
720 mov r9, #0
722 padsave:
723 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
725 ldr r1, [r0]
726 str r1, [r8, r9] @ save the content of the addr
728 add r9, r9, #4
729 cmp r3, r9
730 bne padsave
731 padsave_done:
733 dsb
735 cmp r10, #TEGRA30
736 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
737 cmp r10, #TEGRA114
738 ldreq r0, =TEGRA_EMC0_BASE
739 cmp r10, #TEGRA124
740 ldreq r0, =TEGRA124_EMC_BASE
742 enter_self_refresh:
743 cmp r10, #TEGRA30
744 mov r1, #0
745 str r1, [r0, #EMC_ZCAL_INTERVAL]
746 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
747 ldr r1, [r0, #EMC_CFG]
748 bic r1, r1, #(1 << 28)
749 bicne r1, r1, #(1 << 29)
750 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
752 emc_timing_update r1, r0
754 ldr r1, [r7]
755 add r1, r1, #5
756 wait_until r1, r7, r2
758 emc_wait_auto_cal:
759 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
760 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
761 bne emc_wait_auto_cal
763 mov r1, #3
764 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
766 emcidle:
767 ldr r1, [r0, #EMC_EMC_STATUS]
768 tst r1, #4
769 beq emcidle
771 mov r1, #1
772 str r1, [r0, #EMC_SELF_REF]
774 emc_device_mask r1, r0
776 emcself:
777 ldr r2, [r0, #EMC_EMC_STATUS]
778 and r2, r2, r1
779 cmp r2, r1
780 bne emcself @ loop until DDR in self-refresh
782 /* Put VTTGEN in the lowest power mode */
783 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
784 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
785 and r1, r1, r2
786 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
787 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
788 cmp r10, #TEGRA30
789 orreq r1, r1, #7 @ set E_NO_VTTGEN
790 orrne r1, r1, #0x3f
791 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
793 emc_timing_update r1, r0
795 /* Tegra114 had dual EMC channel, now config the other one */
796 cmp r10, #TEGRA114
797 bne no_dual_emc_chanl
798 mov32 r1, TEGRA_EMC1_BASE
799 cmp r0, r1
800 movne r0, r1
801 bne enter_self_refresh
802 no_dual_emc_chanl:
804 ldr r1, [r4, #PMC_CTRL]
805 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
806 bne pmc_io_dpd_skip
807 /*
808 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
809 * and COMP in the lowest power mode when LP1.
810 */
811 mov32 r1, 0x8EC00000
812 str r1, [r4, #PMC_IO_DPD_REQ]
813 pmc_io_dpd_skip:
815 dsb
817 ret lr
819 .ltorg
820 /* dummy symbol for end of IRAM */
821 .align L1_CACHE_SHIFT
822 .global tegra30_iram_end
823 tegra30_iram_end:
824 b .
825 #endif