| blob | 7fabc8d9654a5daeb6a66df3a86ca69232ced289 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
15 / {
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 chosen {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
25 simplefb_cvbs: framebuffer-cvbs {
26 compatible = "amlogic,simple-framebuffer",
27 "simple-framebuffer";
28 amlogic,pipeline = "vpu-cvbs";
29 clocks = <&clkc CLKID_HDMI>,
30 <&clkc CLKID_HTX_PCLK>,
31 <&clkc CLKID_VPU_INTR>;
32 status = "disabled";
33 };
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "amlogic,simple-framebuffer",
37 "simple-framebuffer";
38 amlogic,pipeline = "vpu-hdmi";
39 clocks = <&clkc CLKID_HDMI>,
40 <&clkc CLKID_HTX_PCLK>,
41 <&clkc CLKID_VPU_INTR>;
42 status = "disabled";
43 };
44 };
46 efuse: efuse {
47 compatible = "amlogic,meson-gxbb-efuse";
48 clocks = <&clkc CLKID_EFUSE>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 read-only;
52 secure-monitor = <&sm>;
53 };
55 psci {
56 compatible = "arm,psci-1.0";
57 method = "smc";
58 };
60 reserved-memory {
61 #address-cells = <2>;
62 #size-cells = <2>;
63 ranges;
65 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
66 secmon_reserved: secmon@5000000 {
67 reg = <0x0 0x05000000 0x0 0x300000>;
68 no-map;
69 };
71 linux,cma {
72 compatible = "shared-dma-pool";
73 reusable;
74 size = <0x0 0x10000000>;
75 alignment = <0x0 0x400000>;
76 linux,cma-default;
77 };
78 };
80 sm: secure-monitor {
81 compatible = "amlogic,meson-gxbb-sm";
82 };
84 soc {
85 compatible = "simple-bus";
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
90 pcie: pcie@fc000000 {
91 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
92 reg = <0x0 0xfc000000 0x0 0x400000
93 0x0 0xff648000 0x0 0x2000
94 0x0 0xfc400000 0x0 0x200000>;
95 reg-names = "elbi", "cfg", "config";
96 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
97 #interrupt-cells = <1>;
98 interrupt-map-mask = <0 0 0 0>;
99 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
100 bus-range = <0x0 0xff>;
101 #address-cells = <3>;
102 #size-cells = <2>;
103 device_type = "pci";
104 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
105 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
107 clocks = <&clkc CLKID_PCIE_PHY
108 &clkc CLKID_PCIE_COMB
109 &clkc CLKID_PCIE_PLL>;
110 clock-names = "general",
111 "pclk",
112 "port";
113 resets = <&reset RESET_PCIE_CTRL_A>,
114 <&reset RESET_PCIE_APB>;
115 reset-names = "port",
116 "apb";
117 num-lanes = <1>;
118 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
119 phy-names = "pcie";
120 status = "disabled";
121 };
123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay = <1000>;
126 polling-delay-passive = <100>;
127 thermal-sensors = <&cpu_temp>;
129 trips {
130 cpu_passive: cpu-passive {
131 temperature = <85000>; /* millicelsius */
132 hysteresis = <2000>; /* millicelsius */
133 type = "passive";
134 };
136 cpu_hot: cpu-hot {
137 temperature = <95000>; /* millicelsius */
138 hysteresis = <2000>; /* millicelsius */
139 type = "hot";
140 };
142 cpu_critical: cpu-critical {
143 temperature = <110000>; /* millicelsius */
144 hysteresis = <2000>; /* millicelsius */
145 type = "critical";
146 };
147 };
148 };
150 ddr_thermal: ddr-thermal {
151 polling-delay = <1000>;
152 polling-delay-passive = <100>;
153 thermal-sensors = <&ddr_temp>;
155 trips {
156 ddr_passive: ddr-passive {
157 temperature = <85000>; /* millicelsius */
158 hysteresis = <2000>; /* millicelsius */
159 type = "passive";
160 };
162 ddr_critical: ddr-critical {
163 temperature = <110000>; /* millicelsius */
164 hysteresis = <2000>; /* millicelsius */
165 type = "critical";
166 };
167 };
169 cooling-maps {
170 map {
171 trip = <&ddr_passive>;
172 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
173 };
174 };
175 };
176 };
178 ethmac: ethernet@ff3f0000 {
179 compatible = "amlogic,meson-axg-dwmac",
180 "snps,dwmac-3.70a",
181 "snps,dwmac";
182 reg = <0x0 0xff3f0000 0x0 0x10000>,
183 <0x0 0xff634540 0x0 0x8>;
184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "macirq";
186 clocks = <&clkc CLKID_ETH>,
187 <&clkc CLKID_FCLK_DIV2>,
188 <&clkc CLKID_MPLL2>;
189 clock-names = "stmmaceth", "clkin0", "clkin1";
190 rx-fifo-depth = <4096>;
191 tx-fifo-depth = <2048>;
192 status = "disabled";
194 mdio0: mdio {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "snps,dwmac-mdio";
198 };
199 };
201 apb: bus@ff600000 {
202 compatible = "simple-bus";
203 reg = <0x0 0xff600000 0x0 0x200000>;
204 #address-cells = <2>;
205 #size-cells = <2>;
206 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
208 hdmi_tx: hdmi-tx@0 {
209 compatible = "amlogic,meson-g12a-dw-hdmi";
210 reg = <0x0 0x0 0x0 0x10000>;
211 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
212 resets = <&reset RESET_HDMITX_CAPB3>,
213 <&reset RESET_HDMITX_PHY>,
214 <&reset RESET_HDMITX>;
215 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
216 clocks = <&clkc CLKID_HDMI>,
217 <&clkc CLKID_HTX_PCLK>,
218 <&clkc CLKID_VPU_INTR>;
219 clock-names = "isfr", "iahb", "venci";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 #sound-dai-cells = <0>;
223 status = "disabled";
225 /* VPU VENC Input */
226 hdmi_tx_venc_port: port@0 {
227 reg = <0>;
229 hdmi_tx_in: endpoint {
230 remote-endpoint = <&hdmi_tx_out>;
231 };
232 };
234 /* TMDS Output */
235 hdmi_tx_tmds_port: port@1 {
236 reg = <1>;
237 };
238 };
240 apb_efuse: bus@30000 {
241 compatible = "simple-bus";
242 reg = <0x0 0x30000 0x0 0x2000>;
243 #address-cells = <2>;
244 #size-cells = <2>;
245 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
247 hwrng: rng@218 {
248 compatible = "amlogic,meson-rng";
249 reg = <0x0 0x218 0x0 0x4>;
250 };
251 };
253 periphs: bus@34400 {
254 compatible = "simple-bus";
255 reg = <0x0 0x34400 0x0 0x400>;
256 #address-cells = <2>;
257 #size-cells = <2>;
258 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
260 periphs_pinctrl: pinctrl@40 {
261 compatible = "amlogic,meson-g12a-periphs-pinctrl";
262 #address-cells = <2>;
263 #size-cells = <2>;
264 ranges;
266 gpio: bank@40 {
267 reg = <0x0 0x40 0x0 0x4c>,
268 <0x0 0xe8 0x0 0x18>,
269 <0x0 0x120 0x0 0x18>,
270 <0x0 0x2c0 0x0 0x40>,
271 <0x0 0x340 0x0 0x1c>;
272 reg-names = "gpio",
273 "pull",
274 "pull-enable",
275 "mux",
276 "ds";
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&periphs_pinctrl 0 0 86>;
280 };
282 cec_ao_a_h_pins: cec_ao_a_h {
283 mux {
284 groups = "cec_ao_a_h";
285 function = "cec_ao_a_h";
286 bias-disable;
287 };
288 };
290 cec_ao_b_h_pins: cec_ao_b_h {
291 mux {
292 groups = "cec_ao_b_h";
293 function = "cec_ao_b_h";
294 bias-disable;
295 };
296 };
298 emmc_pins: emmc {
299 mux-0 {
300 groups = "emmc_nand_d0",
301 "emmc_nand_d1",
302 "emmc_nand_d2",
303 "emmc_nand_d3",
304 "emmc_nand_d4",
305 "emmc_nand_d5",
306 "emmc_nand_d6",
307 "emmc_nand_d7",
308 "emmc_cmd";
309 function = "emmc";
310 bias-pull-up;
311 drive-strength-microamp = <4000>;
312 };
314 mux-1 {
315 groups = "emmc_clk";
316 function = "emmc";
317 bias-disable;
318 drive-strength-microamp = <4000>;
319 };
320 };
322 emmc_ds_pins: emmc-ds {
323 mux {
324 groups = "emmc_nand_ds";
325 function = "emmc";
326 bias-pull-down;
327 drive-strength-microamp = <4000>;
328 };
329 };
331 emmc_clk_gate_pins: emmc_clk_gate {
332 mux {
333 groups = "BOOT_8";
334 function = "gpio_periphs";
335 bias-pull-down;
336 drive-strength-microamp = <4000>;
337 };
338 };
340 hdmitx_ddc_pins: hdmitx_ddc {
341 mux {
342 groups = "hdmitx_sda",
343 "hdmitx_sck";
344 function = "hdmitx";
345 bias-disable;
346 drive-strength-microamp = <4000>;
347 };
348 };
350 hdmitx_hpd_pins: hdmitx_hpd {
351 mux {
352 groups = "hdmitx_hpd_in";
353 function = "hdmitx";
354 bias-disable;
355 };
356 };
359 i2c0_sda_c_pins: i2c0-sda-c {
360 mux {
361 groups = "i2c0_sda_c";
362 function = "i2c0";
363 bias-disable;
364 drive-strength-microamp = <3000>;
366 };
367 };
369 i2c0_sck_c_pins: i2c0-sck-c {
370 mux {
371 groups = "i2c0_sck_c";
372 function = "i2c0";
373 bias-disable;
374 drive-strength-microamp = <3000>;
375 };
376 };
378 i2c0_sda_z0_pins: i2c0-sda-z0 {
379 mux {
380 groups = "i2c0_sda_z0";
381 function = "i2c0";
382 bias-disable;
383 drive-strength-microamp = <3000>;
384 };
385 };
387 i2c0_sck_z1_pins: i2c0-sck-z1 {
388 mux {
389 groups = "i2c0_sck_z1";
390 function = "i2c0";
391 bias-disable;
392 drive-strength-microamp = <3000>;
393 };
394 };
396 i2c0_sda_z7_pins: i2c0-sda-z7 {
397 mux {
398 groups = "i2c0_sda_z7";
399 function = "i2c0";
400 bias-disable;
401 drive-strength-microamp = <3000>;
402 };
403 };
405 i2c0_sda_z8_pins: i2c0-sda-z8 {
406 mux {
407 groups = "i2c0_sda_z8";
408 function = "i2c0";
409 bias-disable;
410 drive-strength-microamp = <3000>;
411 };
412 };
414 i2c1_sda_x_pins: i2c1-sda-x {
415 mux {
416 groups = "i2c1_sda_x";
417 function = "i2c1";
418 bias-disable;
419 drive-strength-microamp = <3000>;
420 };
421 };
423 i2c1_sck_x_pins: i2c1-sck-x {
424 mux {
425 groups = "i2c1_sck_x";
426 function = "i2c1";
427 bias-disable;
428 drive-strength-microamp = <3000>;
429 };
430 };
432 i2c1_sda_h2_pins: i2c1-sda-h2 {
433 mux {
434 groups = "i2c1_sda_h2";
435 function = "i2c1";
436 bias-disable;
437 drive-strength-microamp = <3000>;
438 };
439 };
441 i2c1_sck_h3_pins: i2c1-sck-h3 {
442 mux {
443 groups = "i2c1_sck_h3";
444 function = "i2c1";
445 bias-disable;
446 drive-strength-microamp = <3000>;
447 };
448 };
450 i2c1_sda_h6_pins: i2c1-sda-h6 {
451 mux {
452 groups = "i2c1_sda_h6";
453 function = "i2c1";
454 bias-disable;
455 drive-strength-microamp = <3000>;
456 };
457 };
459 i2c1_sck_h7_pins: i2c1-sck-h7 {
460 mux {
461 groups = "i2c1_sck_h7";
462 function = "i2c1";
463 bias-disable;
464 drive-strength-microamp = <3000>;
465 };
466 };
468 i2c2_sda_x_pins: i2c2-sda-x {
469 mux {
470 groups = "i2c2_sda_x";
471 function = "i2c2";
472 bias-disable;
473 drive-strength-microamp = <3000>;
474 };
475 };
477 i2c2_sck_x_pins: i2c2-sck-x {
478 mux {
479 groups = "i2c2_sck_x";
480 function = "i2c2";
481 bias-disable;
482 drive-strength-microamp = <3000>;
483 };
484 };
486 i2c2_sda_z_pins: i2c2-sda-z {
487 mux {
488 groups = "i2c2_sda_z";
489 function = "i2c2";
490 bias-disable;
491 drive-strength-microamp = <3000>;
492 };
493 };
495 i2c2_sck_z_pins: i2c2-sck-z {
496 mux {
497 groups = "i2c2_sck_z";
498 function = "i2c2";
499 bias-disable;
500 drive-strength-microamp = <3000>;
501 };
502 };
504 i2c3_sda_h_pins: i2c3-sda-h {
505 mux {
506 groups = "i2c3_sda_h";
507 function = "i2c3";
508 bias-disable;
509 drive-strength-microamp = <3000>;
510 };
511 };
513 i2c3_sck_h_pins: i2c3-sck-h {
514 mux {
515 groups = "i2c3_sck_h";
516 function = "i2c3";
517 bias-disable;
518 drive-strength-microamp = <3000>;
519 };
520 };
522 i2c3_sda_a_pins: i2c3-sda-a {
523 mux {
524 groups = "i2c3_sda_a";
525 function = "i2c3";
526 bias-disable;
527 drive-strength-microamp = <3000>;
528 };
529 };
531 i2c3_sck_a_pins: i2c3-sck-a {
532 mux {
533 groups = "i2c3_sck_a";
534 function = "i2c3";
535 bias-disable;
536 drive-strength-microamp = <3000>;
537 };
538 };
540 mclk0_a_pins: mclk0-a {
541 mux {
542 groups = "mclk0_a";
543 function = "mclk0";
544 bias-disable;
545 drive-strength-microamp = <3000>;
546 };
547 };
549 mclk1_a_pins: mclk1-a {
550 mux {
551 groups = "mclk1_a";
552 function = "mclk1";
553 bias-disable;
554 drive-strength-microamp = <3000>;
555 };
556 };
558 mclk1_x_pins: mclk1-x {
559 mux {
560 groups = "mclk1_x";
561 function = "mclk1";
562 bias-disable;
563 drive-strength-microamp = <3000>;
564 };
565 };
567 mclk1_z_pins: mclk1-z {
568 mux {
569 groups = "mclk1_z";
570 function = "mclk1";
571 bias-disable;
572 drive-strength-microamp = <3000>;
573 };
574 };
576 pdm_din0_a_pins: pdm-din0-a {
577 mux {
578 groups = "pdm_din0_a";
579 function = "pdm";
580 bias-disable;
581 };
582 };
584 pdm_din0_c_pins: pdm-din0-c {
585 mux {
586 groups = "pdm_din0_c";
587 function = "pdm";
588 bias-disable;
589 };
590 };
592 pdm_din0_x_pins: pdm-din0-x {
593 mux {
594 groups = "pdm_din0_x";
595 function = "pdm";
596 bias-disable;
597 };
598 };
600 pdm_din0_z_pins: pdm-din0-z {
601 mux {
602 groups = "pdm_din0_z";
603 function = "pdm";
604 bias-disable;
605 };
606 };
608 pdm_din1_a_pins: pdm-din1-a {
609 mux {
610 groups = "pdm_din1_a";
611 function = "pdm";
612 bias-disable;
613 };
614 };
616 pdm_din1_c_pins: pdm-din1-c {
617 mux {
618 groups = "pdm_din1_c";
619 function = "pdm";
620 bias-disable;
621 };
622 };
624 pdm_din1_x_pins: pdm-din1-x {
625 mux {
626 groups = "pdm_din1_x";
627 function = "pdm";
628 bias-disable;
629 };
630 };
632 pdm_din1_z_pins: pdm-din1-z {
633 mux {
634 groups = "pdm_din1_z";
635 function = "pdm";
636 bias-disable;
637 };
638 };
640 pdm_din2_a_pins: pdm-din2-a {
641 mux {
642 groups = "pdm_din2_a";
643 function = "pdm";
644 bias-disable;
645 };
646 };
648 pdm_din2_c_pins: pdm-din2-c {
649 mux {
650 groups = "pdm_din2_c";
651 function = "pdm";
652 bias-disable;
653 };
654 };
656 pdm_din2_x_pins: pdm-din2-x {
657 mux {
658 groups = "pdm_din2_x";
659 function = "pdm";
660 bias-disable;
661 };
662 };
664 pdm_din2_z_pins: pdm-din2-z {
665 mux {
666 groups = "pdm_din2_z";
667 function = "pdm";
668 bias-disable;
669 };
670 };
672 pdm_din3_a_pins: pdm-din3-a {
673 mux {
674 groups = "pdm_din3_a";
675 function = "pdm";
676 bias-disable;
677 };
678 };
680 pdm_din3_c_pins: pdm-din3-c {
681 mux {
682 groups = "pdm_din3_c";
683 function = "pdm";
684 bias-disable;
685 };
686 };
688 pdm_din3_x_pins: pdm-din3-x {
689 mux {
690 groups = "pdm_din3_x";
691 function = "pdm";
692 bias-disable;
693 };
694 };
696 pdm_din3_z_pins: pdm-din3-z {
697 mux {
698 groups = "pdm_din3_z";
699 function = "pdm";
700 bias-disable;
701 };
702 };
704 pdm_dclk_a_pins: pdm-dclk-a {
705 mux {
706 groups = "pdm_dclk_a";
707 function = "pdm";
708 bias-disable;
709 drive-strength-microamp = <500>;
710 };
711 };
713 pdm_dclk_c_pins: pdm-dclk-c {
714 mux {
715 groups = "pdm_dclk_c";
716 function = "pdm";
717 bias-disable;
718 drive-strength-microamp = <500>;
719 };
720 };
722 pdm_dclk_x_pins: pdm-dclk-x {
723 mux {
724 groups = "pdm_dclk_x";
725 function = "pdm";
726 bias-disable;
727 drive-strength-microamp = <500>;
728 };
729 };
731 pdm_dclk_z_pins: pdm-dclk-z {
732 mux {
733 groups = "pdm_dclk_z";
734 function = "pdm";
735 bias-disable;
736 drive-strength-microamp = <500>;
737 };
738 };
740 pwm_a_pins: pwm-a {
741 mux {
742 groups = "pwm_a";
743 function = "pwm_a";
744 bias-disable;
745 };
746 };
748 pwm_b_x7_pins: pwm-b-x7 {
749 mux {
750 groups = "pwm_b_x7";
751 function = "pwm_b";
752 bias-disable;
753 };
754 };
756 pwm_b_x19_pins: pwm-b-x19 {
757 mux {
758 groups = "pwm_b_x19";
759 function = "pwm_b";
760 bias-disable;
761 };
762 };
764 pwm_c_c_pins: pwm-c-c {
765 mux {
766 groups = "pwm_c_c";
767 function = "pwm_c";
768 bias-disable;
769 };
770 };
772 pwm_c_x5_pins: pwm-c-x5 {
773 mux {
774 groups = "pwm_c_x5";
775 function = "pwm_c";
776 bias-disable;
777 };
778 };
780 pwm_c_x8_pins: pwm-c-x8 {
781 mux {
782 groups = "pwm_c_x8";
783 function = "pwm_c";
784 bias-disable;
785 };
786 };
788 pwm_d_x3_pins: pwm-d-x3 {
789 mux {
790 groups = "pwm_d_x3";
791 function = "pwm_d";
792 bias-disable;
793 };
794 };
796 pwm_d_x6_pins: pwm-d-x6 {
797 mux {
798 groups = "pwm_d_x6";
799 function = "pwm_d";
800 bias-disable;
801 };
802 };
804 pwm_e_pins: pwm-e {
805 mux {
806 groups = "pwm_e";
807 function = "pwm_e";
808 bias-disable;
809 };
810 };
812 pwm_f_x_pins: pwm-f-x {
813 mux {
814 groups = "pwm_f_x";
815 function = "pwm_f";
816 bias-disable;
817 };
818 };
820 pwm_f_h_pins: pwm-f-h {
821 mux {
822 groups = "pwm_f_h";
823 function = "pwm_f";
824 bias-disable;
825 };
826 };
828 sdcard_c_pins: sdcard_c {
829 mux-0 {
830 groups = "sdcard_d0_c",
831 "sdcard_d1_c",
832 "sdcard_d2_c",
833 "sdcard_d3_c",
834 "sdcard_cmd_c";
835 function = "sdcard";
836 bias-pull-up;
837 drive-strength-microamp = <4000>;
838 };
840 mux-1 {
841 groups = "sdcard_clk_c";
842 function = "sdcard";
843 bias-disable;
844 drive-strength-microamp = <4000>;
845 };
846 };
848 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
849 mux {
850 groups = "GPIOC_4";
851 function = "gpio_periphs";
852 bias-pull-down;
853 drive-strength-microamp = <4000>;
854 };
855 };
857 sdcard_z_pins: sdcard_z {
858 mux-0 {
859 groups = "sdcard_d0_z",
860 "sdcard_d1_z",
861 "sdcard_d2_z",
862 "sdcard_d3_z",
863 "sdcard_cmd_z";
864 function = "sdcard";
865 bias-pull-up;
866 drive-strength-microamp = <4000>;
867 };
869 mux-1 {
870 groups = "sdcard_clk_z";
871 function = "sdcard";
872 bias-disable;
873 drive-strength-microamp = <4000>;
874 };
875 };
877 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
878 mux {
879 groups = "GPIOZ_6";
880 function = "gpio_periphs";
881 bias-pull-down;
882 drive-strength-microamp = <4000>;
883 };
884 };
886 sdio_pins: sdio {
887 mux {
888 groups = "sdio_d0",
889 "sdio_d1",
890 "sdio_d2",
891 "sdio_d3",
892 "sdio_clk",
893 "sdio_cmd";
894 function = "sdio";
895 bias-disable;
896 drive-strength-microamp = <4000>;
897 };
898 };
900 sdio_clk_gate_pins: sdio_clk_gate {
901 mux {
902 groups = "GPIOX_4";
903 function = "gpio_periphs";
904 bias-pull-down;
905 drive-strength-microamp = <4000>;
906 };
907 };
909 spdif_in_a10_pins: spdif-in-a10 {
910 mux {
911 groups = "spdif_in_a10";
912 function = "spdif_in";
913 bias-disable;
914 };
915 };
917 spdif_in_a12_pins: spdif-in-a12 {
918 mux {
919 groups = "spdif_in_a12";
920 function = "spdif_in";
921 bias-disable;
922 };
923 };
925 spdif_in_h_pins: spdif-in-h {
926 mux {
927 groups = "spdif_in_h";
928 function = "spdif_in";
929 bias-disable;
930 };
931 };
933 spdif_out_h_pins: spdif-out-h {
934 mux {
935 groups = "spdif_out_h";
936 function = "spdif_out";
937 drive-strength-microamp = <500>;
938 bias-disable;
939 };
940 };
942 spdif_out_a11_pins: spdif-out-a11 {
943 mux {
944 groups = "spdif_out_a11";
945 function = "spdif_out";
946 drive-strength-microamp = <500>;
947 bias-disable;
948 };
949 };
951 spdif_out_a13_pins: spdif-out-a13 {
952 mux {
953 groups = "spdif_out_a13";
954 function = "spdif_out";
955 drive-strength-microamp = <500>;
956 bias-disable;
957 };
958 };
960 tdm_a_din0_pins: tdm-a-din0 {
961 mux {
962 groups = "tdm_a_din0";
963 function = "tdm_a";
964 bias-disable;
965 };
966 };
969 tdm_a_din1_pins: tdm-a-din1 {
970 mux {
971 groups = "tdm_a_din1";
972 function = "tdm_a";
973 bias-disable;
974 };
975 };
977 tdm_a_dout0_pins: tdm-a-dout0 {
978 mux {
979 groups = "tdm_a_dout0";
980 function = "tdm_a";
981 bias-disable;
982 drive-strength-microamp = <3000>;
983 };
984 };
986 tdm_a_dout1_pins: tdm-a-dout1 {
987 mux {
988 groups = "tdm_a_dout1";
989 function = "tdm_a";
990 bias-disable;
991 drive-strength-microamp = <3000>;
992 };
993 };
995 tdm_a_fs_pins: tdm-a-fs {
996 mux {
997 groups = "tdm_a_fs";
998 function = "tdm_a";
999 bias-disable;
1000 drive-strength-microamp = <3000>;
1001 };
1002 };
1004 tdm_a_sclk_pins: tdm-a-sclk {
1005 mux {
1006 groups = "tdm_a_sclk";
1007 function = "tdm_a";
1008 bias-disable;
1009 drive-strength-microamp = <3000>;
1010 };
1011 };
1013 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1014 mux {
1015 groups = "tdm_a_slv_fs";
1016 function = "tdm_a";
1017 bias-disable;
1018 };
1019 };
1022 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1023 mux {
1024 groups = "tdm_a_slv_sclk";
1025 function = "tdm_a";
1026 bias-disable;
1027 };
1028 };
1030 tdm_b_din0_pins: tdm-b-din0 {
1031 mux {
1032 groups = "tdm_b_din0";
1033 function = "tdm_b";
1034 bias-disable;
1035 };
1036 };
1038 tdm_b_din1_pins: tdm-b-din1 {
1039 mux {
1040 groups = "tdm_b_din1";
1041 function = "tdm_b";
1042 bias-disable;
1043 };
1044 };
1046 tdm_b_din2_pins: tdm-b-din2 {
1047 mux {
1048 groups = "tdm_b_din2";
1049 function = "tdm_b";
1050 bias-disable;
1051 };
1052 };
1054 tdm_b_din3_a_pins: tdm-b-din3-a {
1055 mux {
1056 groups = "tdm_b_din3_a";
1057 function = "tdm_b";
1058 bias-disable;
1059 };
1060 };
1062 tdm_b_din3_h_pins: tdm-b-din3-h {
1063 mux {
1064 groups = "tdm_b_din3_h";
1065 function = "tdm_b";
1066 bias-disable;
1067 };
1068 };
1070 tdm_b_dout0_pins: tdm-b-dout0 {
1071 mux {
1072 groups = "tdm_b_dout0";
1073 function = "tdm_b";
1074 bias-disable;
1075 drive-strength-microamp = <3000>;
1076 };
1077 };
1079 tdm_b_dout1_pins: tdm-b-dout1 {
1080 mux {
1081 groups = "tdm_b_dout1";
1082 function = "tdm_b";
1083 bias-disable;
1084 drive-strength-microamp = <3000>;
1085 };
1086 };
1088 tdm_b_dout2_pins: tdm-b-dout2 {
1089 mux {
1090 groups = "tdm_b_dout2";
1091 function = "tdm_b";
1092 bias-disable;
1093 drive-strength-microamp = <3000>;
1094 };
1095 };
1097 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1098 mux {
1099 groups = "tdm_b_dout3_a";
1100 function = "tdm_b";
1101 bias-disable;
1102 drive-strength-microamp = <3000>;
1103 };
1104 };
1106 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1107 mux {
1108 groups = "tdm_b_dout3_h";
1109 function = "tdm_b";
1110 bias-disable;
1111 drive-strength-microamp = <3000>;
1112 };
1113 };
1115 tdm_b_fs_pins: tdm-b-fs {
1116 mux {
1117 groups = "tdm_b_fs";
1118 function = "tdm_b";
1119 bias-disable;
1120 drive-strength-microamp = <3000>;
1121 };
1122 };
1124 tdm_b_sclk_pins: tdm-b-sclk {
1125 mux {
1126 groups = "tdm_b_sclk";
1127 function = "tdm_b";
1128 bias-disable;
1129 drive-strength-microamp = <3000>;
1130 };
1131 };
1133 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1134 mux {
1135 groups = "tdm_b_slv_fs";
1136 function = "tdm_b";
1137 bias-disable;
1138 };
1139 };
1141 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1142 mux {
1143 groups = "tdm_b_slv_sclk";
1144 function = "tdm_b";
1145 bias-disable;
1146 };
1147 };
1149 tdm_c_din0_a_pins: tdm-c-din0-a {
1150 mux {
1151 groups = "tdm_c_din0_a";
1152 function = "tdm_c";
1153 bias-disable;
1154 };
1155 };
1157 tdm_c_din0_z_pins: tdm-c-din0-z {
1158 mux {
1159 groups = "tdm_c_din0_z";
1160 function = "tdm_c";
1161 bias-disable;
1162 };
1163 };
1165 tdm_c_din1_a_pins: tdm-c-din1-a {
1166 mux {
1167 groups = "tdm_c_din1_a";
1168 function = "tdm_c";
1169 bias-disable;
1170 };
1171 };
1173 tdm_c_din1_z_pins: tdm-c-din1-z {
1174 mux {
1175 groups = "tdm_c_din1_z";
1176 function = "tdm_c";
1177 bias-disable;
1178 };
1179 };
1181 tdm_c_din2_a_pins: tdm-c-din2-a {
1182 mux {
1183 groups = "tdm_c_din2_a";
1184 function = "tdm_c";
1185 bias-disable;
1186 };
1187 };
1189 eth_leds_pins: eth-leds {
1190 mux {
1191 groups = "eth_link_led",
1192 "eth_act_led";
1193 function = "eth";
1194 bias-disable;
1195 };
1196 };
1198 eth_pins: eth {
1199 mux {
1200 groups = "eth_mdio",
1201 "eth_mdc",
1202 "eth_rgmii_rx_clk",
1203 "eth_rx_dv",
1204 "eth_rxd0",
1205 "eth_rxd1",
1206 "eth_txen",
1207 "eth_txd0",
1208 "eth_txd1";
1209 function = "eth";
1210 drive-strength-microamp = <4000>;
1211 bias-disable;
1212 };
1213 };
1215 eth_rgmii_pins: eth-rgmii {
1216 mux {
1217 groups = "eth_rxd2_rgmii",
1218 "eth_rxd3_rgmii",
1219 "eth_rgmii_tx_clk",
1220 "eth_txd2_rgmii",
1221 "eth_txd3_rgmii";
1222 function = "eth";
1223 drive-strength-microamp = <4000>;
1224 bias-disable;
1225 };
1226 };
1228 tdm_c_din2_z_pins: tdm-c-din2-z {
1229 mux {
1230 groups = "tdm_c_din2_z";
1231 function = "tdm_c";
1232 bias-disable;
1233 };
1234 };
1236 tdm_c_din3_a_pins: tdm-c-din3-a {
1237 mux {
1238 groups = "tdm_c_din3_a";
1239 function = "tdm_c";
1240 bias-disable;
1241 };
1242 };
1244 tdm_c_din3_z_pins: tdm-c-din3-z {
1245 mux {
1246 groups = "tdm_c_din3_z";
1247 function = "tdm_c";
1248 bias-disable;
1249 };
1250 };
1252 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1253 mux {
1254 groups = "tdm_c_dout0_a";
1255 function = "tdm_c";
1256 bias-disable;
1257 drive-strength-microamp = <3000>;
1258 };
1259 };
1261 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1262 mux {
1263 groups = "tdm_c_dout0_z";
1264 function = "tdm_c";
1265 bias-disable;
1266 drive-strength-microamp = <3000>;
1267 };
1268 };
1270 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1271 mux {
1272 groups = "tdm_c_dout1_a";
1273 function = "tdm_c";
1274 bias-disable;
1275 drive-strength-microamp = <3000>;
1276 };
1277 };
1279 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1280 mux {
1281 groups = "tdm_c_dout1_z";
1282 function = "tdm_c";
1283 bias-disable;
1284 drive-strength-microamp = <3000>;
1285 };
1286 };
1288 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1289 mux {
1290 groups = "tdm_c_dout2_a";
1291 function = "tdm_c";
1292 bias-disable;
1293 drive-strength-microamp = <3000>;
1294 };
1295 };
1297 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1298 mux {
1299 groups = "tdm_c_dout2_z";
1300 function = "tdm_c";
1301 bias-disable;
1302 drive-strength-microamp = <3000>;
1303 };
1304 };
1306 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1307 mux {
1308 groups = "tdm_c_dout3_a";
1309 function = "tdm_c";
1310 bias-disable;
1311 drive-strength-microamp = <3000>;
1312 };
1313 };
1315 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1316 mux {
1317 groups = "tdm_c_dout3_z";
1318 function = "tdm_c";
1319 bias-disable;
1320 drive-strength-microamp = <3000>;
1321 };
1322 };
1324 tdm_c_fs_a_pins: tdm-c-fs-a {
1325 mux {
1326 groups = "tdm_c_fs_a";
1327 function = "tdm_c";
1328 bias-disable;
1329 drive-strength-microamp = <3000>;
1330 };
1331 };
1333 tdm_c_fs_z_pins: tdm-c-fs-z {
1334 mux {
1335 groups = "tdm_c_fs_z";
1336 function = "tdm_c";
1337 bias-disable;
1338 drive-strength-microamp = <3000>;
1339 };
1340 };
1342 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1343 mux {
1344 groups = "tdm_c_sclk_a";
1345 function = "tdm_c";
1346 bias-disable;
1347 drive-strength-microamp = <3000>;
1348 };
1349 };
1351 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1352 mux {
1353 groups = "tdm_c_sclk_z";
1354 function = "tdm_c";
1355 bias-disable;
1356 drive-strength-microamp = <3000>;
1357 };
1358 };
1360 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1361 mux {
1362 groups = "tdm_c_slv_fs_a";
1363 function = "tdm_c";
1364 bias-disable;
1365 };
1366 };
1368 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1369 mux {
1370 groups = "tdm_c_slv_fs_z";
1371 function = "tdm_c";
1372 bias-disable;
1373 };
1374 };
1376 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1377 mux {
1378 groups = "tdm_c_slv_sclk_a";
1379 function = "tdm_c";
1380 bias-disable;
1381 };
1382 };
1384 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1385 mux {
1386 groups = "tdm_c_slv_sclk_z";
1387 function = "tdm_c";
1388 bias-disable;
1389 };
1390 };
1392 uart_a_pins: uart-a {
1393 mux {
1394 groups = "uart_a_tx",
1395 "uart_a_rx";
1396 function = "uart_a";
1397 bias-disable;
1398 };
1399 };
1401 uart_a_cts_rts_pins: uart-a-cts-rts {
1402 mux {
1403 groups = "uart_a_cts",
1404 "uart_a_rts";
1405 function = "uart_a";
1406 bias-disable;
1407 };
1408 };
1410 uart_b_pins: uart-b {
1411 mux {
1412 groups = "uart_b_tx",
1413 "uart_b_rx";
1414 function = "uart_b";
1415 bias-disable;
1416 };
1417 };
1419 uart_c_pins: uart-c {
1420 mux {
1421 groups = "uart_c_tx",
1422 "uart_c_rx";
1423 function = "uart_c";
1424 bias-disable;
1425 };
1426 };
1428 uart_c_cts_rts_pins: uart-c-cts-rts {
1429 mux {
1430 groups = "uart_c_cts",
1431 "uart_c_rts";
1432 function = "uart_c";
1433 bias-disable;
1434 };
1435 };
1436 };
1437 };
1439 cpu_temp: temperature-sensor@34800 {
1440 compatible = "amlogic,g12a-cpu-thermal",
1441 "amlogic,g12a-thermal";
1442 reg = <0x0 0x34800 0x0 0x50>;
1443 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1444 clocks = <&clkc CLKID_TS>;
1445 #thermal-sensor-cells = <0>;
1446 amlogic,ao-secure = <&sec_AO>;
1447 };
1449 ddr_temp: temperature-sensor@34c00 {
1450 compatible = "amlogic,g12a-ddr-thermal",
1451 "amlogic,g12a-thermal";
1452 reg = <0x0 0x34c00 0x0 0x50>;
1453 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1454 clocks = <&clkc CLKID_TS>;
1455 #thermal-sensor-cells = <0>;
1456 amlogic,ao-secure = <&sec_AO>;
1457 };
1459 usb2_phy0: phy@36000 {
1460 compatible = "amlogic,g12a-usb2-phy";
1461 reg = <0x0 0x36000 0x0 0x2000>;
1462 clocks = <&xtal>;
1463 clock-names = "xtal";
1464 resets = <&reset RESET_USB_PHY20>;
1465 reset-names = "phy";
1466 #phy-cells = <0>;
1467 };
1469 dmc: bus@38000 {
1470 compatible = "simple-bus";
1471 reg = <0x0 0x38000 0x0 0x400>;
1472 #address-cells = <2>;
1473 #size-cells = <2>;
1474 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1476 canvas: video-lut@48 {
1477 compatible = "amlogic,canvas";
1478 reg = <0x0 0x48 0x0 0x14>;
1479 };
1480 };
1482 usb2_phy1: phy@3a000 {
1483 compatible = "amlogic,g12a-usb2-phy";
1484 reg = <0x0 0x3a000 0x0 0x2000>;
1485 clocks = <&xtal>;
1486 clock-names = "xtal";
1487 resets = <&reset RESET_USB_PHY21>;
1488 reset-names = "phy";
1489 #phy-cells = <0>;
1490 };
1492 hiu: bus@3c000 {
1493 compatible = "simple-bus";
1494 reg = <0x0 0x3c000 0x0 0x1400>;
1495 #address-cells = <2>;
1496 #size-cells = <2>;
1497 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1499 hhi: system-controller@0 {
1500 compatible = "amlogic,meson-gx-hhi-sysctrl",
1501 "simple-mfd", "syscon";
1502 reg = <0 0 0 0x400>;
1504 clkc: clock-controller {
1505 compatible = "amlogic,g12a-clkc";
1506 #clock-cells = <1>;
1507 clocks = <&xtal>;
1508 clock-names = "xtal";
1509 };
1511 pwrc: power-controller {
1512 compatible = "amlogic,meson-g12a-pwrc";
1513 #power-domain-cells = <1>;
1514 amlogic,ao-sysctrl = <&rti>;
1515 resets = <&reset RESET_VIU>,
1516 <&reset RESET_VENC>,
1517 <&reset RESET_VCBUS>,
1518 <&reset RESET_BT656>,
1519 <&reset RESET_RDMA>,
1520 <&reset RESET_VENCI>,
1521 <&reset RESET_VENCP>,
1522 <&reset RESET_VDAC>,
1523 <&reset RESET_VDI6>,
1524 <&reset RESET_VENCL>,
1525 <&reset RESET_VID_LOCK>;
1526 reset-names = "viu", "venc", "vcbus", "bt656",
1527 "rdma", "venci", "vencp", "vdac",
1528 "vdi6", "vencl", "vid_lock";
1529 clocks = <&clkc CLKID_VPU>,
1530 <&clkc CLKID_VAPB>;
1531 clock-names = "vpu", "vapb";
1532 /*
1533 * VPU clocking is provided by two identical clock paths
1534 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1535 * free mux to safely change frequency while running.
1536 * Same for VAPB but with a final gate after the glitch free mux.
1537 */
1538 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1539 <&clkc CLKID_VPU_0>,
1540 <&clkc CLKID_VPU>, /* Glitch free mux */
1541 <&clkc CLKID_VAPB_0_SEL>,
1542 <&clkc CLKID_VAPB_0>,
1543 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1544 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1545 <0>, /* Do Nothing */
1546 <&clkc CLKID_VPU_0>,
1547 <&clkc CLKID_FCLK_DIV4>,
1548 <0>, /* Do Nothing */
1549 <&clkc CLKID_VAPB_0>;
1550 assigned-clock-rates = <0>, /* Do Nothing */
1551 <666666666>,
1552 <0>, /* Do Nothing */
1553 <0>, /* Do Nothing */
1554 <250000000>,
1555 <0>; /* Do Nothing */
1556 };
1557 };
1558 };
1560 usb3_pcie_phy: phy@46000 {
1561 compatible = "amlogic,g12a-usb3-pcie-phy";
1562 reg = <0x0 0x46000 0x0 0x2000>;
1563 clocks = <&clkc CLKID_PCIE_PLL>;
1564 clock-names = "ref_clk";
1565 resets = <&reset RESET_PCIE_PHY>;
1566 reset-names = "phy";
1567 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1568 assigned-clock-rates = <100000000>;
1569 #phy-cells = <1>;
1570 };
1572 eth_phy: mdio-multiplexer@4c000 {
1573 compatible = "amlogic,g12a-mdio-mux";
1574 reg = <0x0 0x4c000 0x0 0xa4>;
1575 clocks = <&clkc CLKID_ETH_PHY>,
1576 <&xtal>,
1577 <&clkc CLKID_MPLL_50M>;
1578 clock-names = "pclk", "clkin0", "clkin1";
1579 mdio-parent-bus = <&mdio0>;
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1583 ext_mdio: mdio@0 {
1584 reg = <0>;
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1587 };
1589 int_mdio: mdio@1 {
1590 reg = <1>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1594 internal_ephy: ethernet_phy@8 {
1595 compatible = "ethernet-phy-id0180.3301",
1596 "ethernet-phy-ieee802.3-c22";
1597 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1598 reg = <8>;
1599 max-speed = <100>;
1600 };
1601 };
1602 };
1603 };
1605 aobus: bus@ff800000 {
1606 compatible = "simple-bus";
1607 reg = <0x0 0xff800000 0x0 0x100000>;
1608 #address-cells = <2>;
1609 #size-cells = <2>;
1610 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1612 rti: sys-ctrl@0 {
1613 compatible = "amlogic,meson-gx-ao-sysctrl",
1614 "simple-mfd", "syscon";
1615 reg = <0x0 0x0 0x0 0x100>;
1616 #address-cells = <2>;
1617 #size-cells = <2>;
1618 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1620 clkc_AO: clock-controller {
1621 compatible = "amlogic,meson-g12a-aoclkc";
1622 #clock-cells = <1>;
1623 #reset-cells = <1>;
1624 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1625 clock-names = "xtal", "mpeg-clk";
1626 };
1628 ao_pinctrl: pinctrl@14 {
1629 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1630 #address-cells = <2>;
1631 #size-cells = <2>;
1632 ranges;
1634 gpio_ao: bank@14 {
1635 reg = <0x0 0x14 0x0 0x8>,
1636 <0x0 0x1c 0x0 0x8>,
1637 <0x0 0x24 0x0 0x14>;
1638 reg-names = "mux",
1639 "ds",
1640 "gpio";
1641 gpio-controller;
1642 #gpio-cells = <2>;
1643 gpio-ranges = <&ao_pinctrl 0 0 15>;
1644 };
1646 i2c_ao_sck_pins: i2c_ao_sck_pins {
1647 mux {
1648 groups = "i2c_ao_sck";
1649 function = "i2c_ao";
1650 bias-disable;
1651 drive-strength-microamp = <3000>;
1652 };
1653 };
1655 i2c_ao_sda_pins: i2c_ao_sda {
1656 mux {
1657 groups = "i2c_ao_sda";
1658 function = "i2c_ao";
1659 bias-disable;
1660 drive-strength-microamp = <3000>;
1661 };
1662 };
1664 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1665 mux {
1666 groups = "i2c_ao_sck_e";
1667 function = "i2c_ao";
1668 bias-disable;
1669 drive-strength-microamp = <3000>;
1670 };
1671 };
1673 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1674 mux {
1675 groups = "i2c_ao_sda_e";
1676 function = "i2c_ao";
1677 bias-disable;
1678 drive-strength-microamp = <3000>;
1679 };
1680 };
1682 mclk0_ao_pins: mclk0-ao {
1683 mux {
1684 groups = "mclk0_ao";
1685 function = "mclk0_ao";
1686 bias-disable;
1687 drive-strength-microamp = <3000>;
1688 };
1689 };
1691 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1692 mux {
1693 groups = "tdm_ao_b_din0";
1694 function = "tdm_ao_b";
1695 bias-disable;
1696 };
1697 };
1699 spdif_ao_out_pins: spdif-ao-out {
1700 mux {
1701 groups = "spdif_ao_out";
1702 function = "spdif_ao_out";
1703 drive-strength-microamp = <500>;
1704 bias-disable;
1705 };
1706 };
1708 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1709 mux {
1710 groups = "tdm_ao_b_din1";
1711 function = "tdm_ao_b";
1712 bias-disable;
1713 };
1714 };
1716 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1717 mux {
1718 groups = "tdm_ao_b_din2";
1719 function = "tdm_ao_b";
1720 bias-disable;
1721 };
1722 };
1724 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1725 mux {
1726 groups = "tdm_ao_b_dout0";
1727 function = "tdm_ao_b";
1728 bias-disable;
1729 drive-strength-microamp = <3000>;
1730 };
1731 };
1733 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1734 mux {
1735 groups = "tdm_ao_b_dout1";
1736 function = "tdm_ao_b";
1737 bias-disable;
1738 drive-strength-microamp = <3000>;
1739 };
1740 };
1742 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1743 mux {
1744 groups = "tdm_ao_b_dout2";
1745 function = "tdm_ao_b";
1746 bias-disable;
1747 drive-strength-microamp = <3000>;
1748 };
1749 };
1751 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1752 mux {
1753 groups = "tdm_ao_b_fs";
1754 function = "tdm_ao_b";
1755 bias-disable;
1756 drive-strength-microamp = <3000>;
1757 };
1758 };
1760 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1761 mux {
1762 groups = "tdm_ao_b_sclk";
1763 function = "tdm_ao_b";
1764 bias-disable;
1765 drive-strength-microamp = <3000>;
1766 };
1767 };
1769 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1770 mux {
1771 groups = "tdm_ao_b_slv_fs";
1772 function = "tdm_ao_b";
1773 bias-disable;
1774 };
1775 };
1777 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1778 mux {
1779 groups = "tdm_ao_b_slv_sclk";
1780 function = "tdm_ao_b";
1781 bias-disable;
1782 };
1783 };
1785 uart_ao_a_pins: uart-a-ao {
1786 mux {
1787 groups = "uart_ao_a_tx",
1788 "uart_ao_a_rx";
1789 function = "uart_ao_a";
1790 bias-disable;
1791 };
1792 };
1794 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1795 mux {
1796 groups = "uart_ao_a_cts",
1797 "uart_ao_a_rts";
1798 function = "uart_ao_a";
1799 bias-disable;
1800 };
1801 };
1803 pwm_a_e_pins: pwm-a-e {
1804 mux {
1805 groups = "pwm_a_e";
1806 function = "pwm_a_e";
1807 bias-disable;
1808 };
1809 };
1811 pwm_ao_a_pins: pwm-ao-a {
1812 mux {
1813 groups = "pwm_ao_a";
1814 function = "pwm_ao_a";
1815 bias-disable;
1816 };
1817 };
1819 pwm_ao_b_pins: pwm-ao-b {
1820 mux {
1821 groups = "pwm_ao_b";
1822 function = "pwm_ao_b";
1823 bias-disable;
1824 };
1825 };
1827 pwm_ao_c_4_pins: pwm-ao-c-4 {
1828 mux {
1829 groups = "pwm_ao_c_4";
1830 function = "pwm_ao_c";
1831 bias-disable;
1832 };
1833 };
1835 pwm_ao_c_6_pins: pwm-ao-c-6 {
1836 mux {
1837 groups = "pwm_ao_c_6";
1838 function = "pwm_ao_c";
1839 bias-disable;
1840 };
1841 };
1843 pwm_ao_d_5_pins: pwm-ao-d-5 {
1844 mux {
1845 groups = "pwm_ao_d_5";
1846 function = "pwm_ao_d";
1847 bias-disable;
1848 };
1849 };
1851 pwm_ao_d_10_pins: pwm-ao-d-10 {
1852 mux {
1853 groups = "pwm_ao_d_10";
1854 function = "pwm_ao_d";
1855 bias-disable;
1856 };
1857 };
1859 pwm_ao_d_e_pins: pwm-ao-d-e {
1860 mux {
1861 groups = "pwm_ao_d_e";
1862 function = "pwm_ao_d";
1863 };
1864 };
1866 remote_input_ao_pins: remote-input-ao {
1867 mux {
1868 groups = "remote_ao_input";
1869 function = "remote_ao_input";
1870 bias-disable;
1871 };
1872 };
1873 };
1874 };
1876 vrtc: rtc@0a8 {
1877 compatible = "amlogic,meson-vrtc";
1878 reg = <0x0 0x000a8 0x0 0x4>;
1879 };
1881 cec_AO: cec@100 {
1882 compatible = "amlogic,meson-gx-ao-cec";
1883 reg = <0x0 0x00100 0x0 0x14>;
1884 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
1885 clocks = <&clkc_AO CLKID_AO_CEC>;
1886 clock-names = "core";
1887 status = "disabled";
1888 };
1890 sec_AO: ao-secure@140 {
1891 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1892 reg = <0x0 0x140 0x0 0x140>;
1893 amlogic,has-chip-id;
1894 };
1896 cecb_AO: cec@280 {
1897 compatible = "amlogic,meson-g12a-ao-cec";
1898 reg = <0x0 0x00280 0x0 0x1c>;
1899 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1900 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
1901 clock-names = "oscin";
1902 status = "disabled";
1903 };
1905 pwm_AO_cd: pwm@2000 {
1906 compatible = "amlogic,meson-g12a-ao-pwm-cd";
1907 reg = <0x0 0x2000 0x0 0x20>;
1908 #pwm-cells = <3>;
1909 status = "disabled";
1910 };
1912 uart_AO: serial@3000 {
1913 compatible = "amlogic,meson-gx-uart",
1914 "amlogic,meson-ao-uart";
1915 reg = <0x0 0x3000 0x0 0x18>;
1916 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1917 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
1918 clock-names = "xtal", "pclk", "baud";
1919 status = "disabled";
1920 };
1922 uart_AO_B: serial@4000 {
1923 compatible = "amlogic,meson-gx-uart",
1924 "amlogic,meson-ao-uart";
1925 reg = <0x0 0x4000 0x0 0x18>;
1926 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1927 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1928 clock-names = "xtal", "pclk", "baud";
1929 status = "disabled";
1930 };
1932 i2c_AO: i2c@5000 {
1933 compatible = "amlogic,meson-axg-i2c";
1934 status = "disabled";
1935 reg = <0x0 0x05000 0x0 0x20>;
1936 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1939 clocks = <&clkc CLKID_I2C>;
1940 };
1942 pwm_AO_ab: pwm@7000 {
1943 compatible = "amlogic,meson-g12a-ao-pwm-ab";
1944 reg = <0x0 0x7000 0x0 0x20>;
1945 #pwm-cells = <3>;
1946 status = "disabled";
1947 };
1949 ir: ir@8000 {
1950 compatible = "amlogic,meson-gxbb-ir";
1951 reg = <0x0 0x8000 0x0 0x20>;
1952 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1953 status = "disabled";
1954 };
1956 saradc: adc@9000 {
1957 compatible = "amlogic,meson-g12a-saradc",
1958 "amlogic,meson-saradc";
1959 reg = <0x0 0x9000 0x0 0x48>;
1960 #io-channel-cells = <1>;
1961 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
1962 clocks = <&xtal>,
1963 <&clkc_AO CLKID_AO_SAR_ADC>,
1964 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1965 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1966 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1967 status = "disabled";
1968 };
1969 };
1971 vpu: vpu@ff900000 {
1972 compatible = "amlogic,meson-g12a-vpu";
1973 reg = <0x0 0xff900000 0x0 0x100000>,
1974 <0x0 0xff63c000 0x0 0x1000>;
1975 reg-names = "vpu", "hhi";
1976 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
1977 #address-cells = <1>;
1978 #size-cells = <0>;
1979 amlogic,canvas = <&canvas>;
1981 /* CVBS VDAC output port */
1982 cvbs_vdac_port: port@0 {
1983 reg = <0>;
1984 };
1986 /* HDMI-TX output port */
1987 hdmi_tx_port: port@1 {
1988 reg = <1>;
1990 hdmi_tx_out: endpoint {
1991 remote-endpoint = <&hdmi_tx_in>;
1992 };
1993 };
1994 };
1996 gic: interrupt-controller@ffc01000 {
1997 compatible = "arm,gic-400";
1998 reg = <0x0 0xffc01000 0 0x1000>,
1999 <0x0 0xffc02000 0 0x2000>,
2000 <0x0 0xffc04000 0 0x2000>,
2001 <0x0 0xffc06000 0 0x2000>;
2002 interrupt-controller;
2003 interrupts = <GIC_PPI 9
2004 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2005 #interrupt-cells = <3>;
2006 #address-cells = <0>;
2007 };
2009 cbus: bus@ffd00000 {
2010 compatible = "simple-bus";
2011 reg = <0x0 0xffd00000 0x0 0x100000>;
2012 #address-cells = <2>;
2013 #size-cells = <2>;
2014 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2016 reset: reset-controller@1004 {
2017 compatible = "amlogic,meson-axg-reset";
2018 reg = <0x0 0x1004 0x0 0x9c>;
2019 #reset-cells = <1>;
2020 };
2022 gpio_intc: interrupt-controller@f080 {
2023 compatible = "amlogic,meson-g12a-gpio-intc",
2024 "amlogic,meson-gpio-intc";
2025 reg = <0x0 0xf080 0x0 0x10>;
2026 interrupt-controller;
2027 #interrupt-cells = <2>;
2028 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2029 };
2031 pwm_ef: pwm@19000 {
2032 compatible = "amlogic,meson-g12a-ee-pwm";
2033 reg = <0x0 0x19000 0x0 0x20>;
2034 #pwm-cells = <3>;
2035 status = "disabled";
2036 };
2038 pwm_cd: pwm@1a000 {
2039 compatible = "amlogic,meson-g12a-ee-pwm";
2040 reg = <0x0 0x1a000 0x0 0x20>;
2041 #pwm-cells = <3>;
2042 status = "disabled";
2043 };
2045 pwm_ab: pwm@1b000 {
2046 compatible = "amlogic,meson-g12a-ee-pwm";
2047 reg = <0x0 0x1b000 0x0 0x20>;
2048 #pwm-cells = <3>;
2049 status = "disabled";
2050 };
2052 i2c3: i2c@1c000 {
2053 compatible = "amlogic,meson-axg-i2c";
2054 status = "disabled";
2055 reg = <0x0 0x1c000 0x0 0x20>;
2056 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2059 clocks = <&clkc CLKID_I2C>;
2060 };
2062 i2c2: i2c@1d000 {
2063 compatible = "amlogic,meson-axg-i2c";
2064 status = "disabled";
2065 reg = <0x0 0x1d000 0x0 0x20>;
2066 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2067 #address-cells = <1>;
2068 #size-cells = <0>;
2069 clocks = <&clkc CLKID_I2C>;
2070 };
2072 i2c1: i2c@1e000 {
2073 compatible = "amlogic,meson-axg-i2c";
2074 status = "disabled";
2075 reg = <0x0 0x1e000 0x0 0x20>;
2076 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2077 #address-cells = <1>;
2078 #size-cells = <0>;
2079 clocks = <&clkc CLKID_I2C>;
2080 };
2082 i2c0: i2c@1f000 {
2083 compatible = "amlogic,meson-axg-i2c";
2084 status = "disabled";
2085 reg = <0x0 0x1f000 0x0 0x20>;
2086 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2089 clocks = <&clkc CLKID_I2C>;
2090 };
2092 clk_msr: clock-measure@18000 {
2093 compatible = "amlogic,meson-g12a-clk-measure";
2094 reg = <0x0 0x18000 0x0 0x10>;
2095 };
2097 uart_C: serial@22000 {
2098 compatible = "amlogic,meson-gx-uart";
2099 reg = <0x0 0x22000 0x0 0x18>;
2100 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2101 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2102 clock-names = "xtal", "pclk", "baud";
2103 status = "disabled";
2104 };
2106 uart_B: serial@23000 {
2107 compatible = "amlogic,meson-gx-uart";
2108 reg = <0x0 0x23000 0x0 0x18>;
2109 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2110 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2111 clock-names = "xtal", "pclk", "baud";
2112 status = "disabled";
2113 };
2115 uart_A: serial@24000 {
2116 compatible = "amlogic,meson-gx-uart";
2117 reg = <0x0 0x24000 0x0 0x18>;
2118 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2119 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2120 clock-names = "xtal", "pclk", "baud";
2121 status = "disabled";
2122 };
2123 };
2125 sd_emmc_a: sd@ffe03000 {
2126 compatible = "amlogic,meson-axg-mmc";
2127 reg = <0x0 0xffe03000 0x0 0x800>;
2128 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2129 status = "disabled";
2130 clocks = <&clkc CLKID_SD_EMMC_A>,
2131 <&clkc CLKID_SD_EMMC_A_CLK0>,
2132 <&clkc CLKID_FCLK_DIV2>;
2133 clock-names = "core", "clkin0", "clkin1";
2134 resets = <&reset RESET_SD_EMMC_A>;
2135 };
2137 sd_emmc_b: sd@ffe05000 {
2138 compatible = "amlogic,meson-axg-mmc";
2139 reg = <0x0 0xffe05000 0x0 0x800>;
2140 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2141 status = "disabled";
2142 clocks = <&clkc CLKID_SD_EMMC_B>,
2143 <&clkc CLKID_SD_EMMC_B_CLK0>,
2144 <&clkc CLKID_FCLK_DIV2>;
2145 clock-names = "core", "clkin0", "clkin1";
2146 resets = <&reset RESET_SD_EMMC_B>;
2147 };
2149 sd_emmc_c: mmc@ffe07000 {
2150 compatible = "amlogic,meson-axg-mmc";
2151 reg = <0x0 0xffe07000 0x0 0x800>;
2152 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2153 status = "disabled";
2154 clocks = <&clkc CLKID_SD_EMMC_C>,
2155 <&clkc CLKID_SD_EMMC_C_CLK0>,
2156 <&clkc CLKID_FCLK_DIV2>;
2157 clock-names = "core", "clkin0", "clkin1";
2158 resets = <&reset RESET_SD_EMMC_C>;
2159 };
2161 usb: usb@ffe09000 {
2162 status = "disabled";
2163 compatible = "amlogic,meson-g12a-usb-ctrl";
2164 reg = <0x0 0xffe09000 0x0 0xa0>;
2165 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2166 #address-cells = <2>;
2167 #size-cells = <2>;
2168 ranges;
2170 clocks = <&clkc CLKID_USB>;
2171 resets = <&reset RESET_USB>;
2173 dr_mode = "otg";
2175 phys = <&usb2_phy0>, <&usb2_phy1>,
2176 <&usb3_pcie_phy PHY_TYPE_USB3>;
2177 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2179 dwc2: usb@ff400000 {
2180 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2181 reg = <0x0 0xff400000 0x0 0x40000>;
2182 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2183 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2184 clock-names = "ddr";
2185 phys = <&usb2_phy1>;
2186 phy-names = "usb2-phy";
2187 dr_mode = "peripheral";
2188 g-rx-fifo-size = <192>;
2189 g-np-tx-fifo-size = <128>;
2190 g-tx-fifo-size = <128 128 16 16 16>;
2191 };
2193 dwc3: usb@ff500000 {
2194 compatible = "snps,dwc3";
2195 reg = <0x0 0xff500000 0x0 0x100000>;
2196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2197 dr_mode = "host";
2198 snps,dis_u2_susphy_quirk;
2199 snps,quirk-frame-length-adjustment;
2200 };
2201 };
2203 mali: gpu@ffe40000 {
2204 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2205 reg = <0x0 0xffe40000 0x0 0x40000>;
2206 interrupt-parent = <&gic>;
2207 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "job", "mmu", "gpu";
2211 clocks = <&clkc CLKID_MALI>;
2212 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2214 /*
2215 * Mali clocking is provided by two identical clock paths
2216 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2217 * free mux to safely change frequency while running.
2218 */
2219 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2220 <&clkc CLKID_MALI_0>,
2221 <&clkc CLKID_MALI>; /* Glitch free mux */
2222 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2223 <0>, /* Do Nothing */
2224 <&clkc CLKID_MALI_0>;
2225 assigned-clock-rates = <0>, /* Do Nothing */
2226 <800000000>,
2227 <0>; /* Do Nothing */
2228 #cooling-cells = <2>;
2229 };
2230 };
2232 timer {
2233 compatible = "arm,armv8-timer";
2234 interrupts = <GIC_PPI 13
2235 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2236 <GIC_PPI 14
2237 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2238 <GIC_PPI 11
2239 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2240 <GIC_PPI 10
2241 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2242 arm,no-tick-in-suspend;
2243 };
2245 xtal: xtal-clk {
2246 compatible = "fixed-clock";
2247 clock-frequency = <24000000>;
2248 clock-output-names = "xtal";
2249 #clock-cells = <0>;
2250 };
2252 };