1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for NXP LS1028A QDS Board.
7 * Harninder Rai <harninder.rai@nxp.com>
13 #include "fsl-ls1028a.dtsi"
16 model = "LS1028A QDS Board";
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
33 device_type = "memory";
34 reg = <0x0 0x80000000 0x1 0x00000000>;
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
44 compatible = "regulator-fixed";
45 regulator-name = "1P8V";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
51 sb_3v3: regulator-sb3v3 {
52 compatible = "regulator-fixed";
53 regulator-name = "3v3_vbus";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
61 compatible = "simple-audio-card";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,widgets =
64 "Microphone", "Microphone Jack",
65 "Headphone", "Headphone Jack",
66 "Speaker", "Speaker Ext",
67 "Line", "Line In Jack";
68 simple-audio-card,routing =
69 "MIC_IN", "Microphone Jack",
70 "Microphone Jack", "Mic Bias",
71 "LINE_IN", "Line In Jack",
72 "Headphone Jack", "HP_OUT",
73 "Speaker Ext", "LINE_OUT";
75 simple-audio-card,cpu {
81 simple-audio-card,codec {
82 sound-dai = <&sgtl5000>;
85 system-clock-frequency = <25000000>;
90 compatible = "mdio-mux-multiplexer";
91 mux-controls = <&mux 0>;
92 mdio-parent-bus = <&enetc_mdio_pf3>;
96 /* on-board RGMII PHY */
102 qds_phy1: ethernet-phy@5 {
130 compatible = "nxp,pca9547";
132 #address-cells = <1>;
136 #address-cells = <1>;
141 compatible = "ti,ina220";
143 shunt-resistor = <1000>;
147 compatible = "ti,ina220";
149 shunt-resistor = <1000>;
154 #address-cells = <1>;
158 temperature-sensor@4c {
159 compatible = "nxp,sa56004";
161 vcc-supply = <&sb_3v3>;
165 compatible = "nxp,pcf2129";
170 compatible = "atmel,24c512";
175 compatible = "atmel,24c512";
181 #address-cells = <1>;
185 sgtl5000: audio-codec@a {
186 #sound-dai-cells = <0>;
187 compatible = "fsl,sgtl5000";
189 VDDA-supply = <®_1p8v>;
190 VDDIO-supply = <®_1p8v>;
191 clocks = <&sys_mclk>;
197 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
201 mux: mux-controller {
202 compatible = "reg-mux";
203 #mux-control-cells = <1>;
204 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
211 phy-handle = <&qds_phy1>;
212 phy-connection-type = "rgmii-id";