| blob | c676d0771762fcbc69c96f3f05b693b0909836e1 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 *
5 * Copyright 2017 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 / {
14 compatible = "fsl,ls1088a";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 crypto = &crypto;
21 };
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
27 /* We have 2 clusters having 4 Cortex-A53 cores each */
28 cpu0: cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a53";
31 reg = <0x0>;
32 clocks = <&clockgen 1 0>;
33 cpu-idle-states = <&CPU_PH20>;
34 #cooling-cells = <2>;
35 };
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a53";
40 reg = <0x1>;
41 clocks = <&clockgen 1 0>;
42 cpu-idle-states = <&CPU_PH20>;
43 #cooling-cells = <2>;
44 };
46 cpu2: cpu@2 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 reg = <0x2>;
50 clocks = <&clockgen 1 0>;
51 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>;
53 };
55 cpu3: cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53";
58 reg = <0x3>;
59 clocks = <&clockgen 1 0>;
60 cpu-idle-states = <&CPU_PH20>;
61 #cooling-cells = <2>;
62 };
64 cpu4: cpu@100 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a53";
67 reg = <0x100>;
68 clocks = <&clockgen 1 1>;
69 cpu-idle-states = <&CPU_PH20>;
70 #cooling-cells = <2>;
71 };
73 cpu5: cpu@101 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x101>;
77 clocks = <&clockgen 1 1>;
78 cpu-idle-states = <&CPU_PH20>;
79 #cooling-cells = <2>;
80 };
82 cpu6: cpu@102 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53";
85 reg = <0x102>;
86 clocks = <&clockgen 1 1>;
87 cpu-idle-states = <&CPU_PH20>;
88 #cooling-cells = <2>;
89 };
91 cpu7: cpu@103 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a53";
94 reg = <0x103>;
95 clocks = <&clockgen 1 1>;
96 cpu-idle-states = <&CPU_PH20>;
97 #cooling-cells = <2>;
98 };
100 CPU_PH20: cpu-ph20 {
101 compatible = "arm,idle-state";
102 idle-state-name = "PH20";
103 arm,psci-suspend-param = <0x0>;
104 entry-latency-us = <1000>;
105 exit-latency-us = <1000>;
106 min-residency-us = <3000>;
107 };
108 };
110 gic: interrupt-controller@6000000 {
111 compatible = "arm,gic-v3";
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
115 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
116 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
117 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
118 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
119 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
120 #address-cells = <2>;
121 #size-cells = <2>;
122 ranges;
124 its: gic-its@6020000 {
125 compatible = "arm,gic-v3-its";
126 msi-controller;
127 reg = <0x0 0x6020000 0 0x20000>;
128 };
129 };
131 thermal-zones {
132 cpu_thermal: cpu-thermal {
133 polling-delay-passive = <1000>;
134 polling-delay = <5000>;
135 thermal-sensors = <&tmu 0>;
137 trips {
138 cpu_alert: cpu-alert {
139 temperature = <85000>;
140 hysteresis = <2000>;
141 type = "passive";
142 };
144 cpu_crit: cpu-crit {
145 temperature = <95000>;
146 hysteresis = <2000>;
147 type = "critical";
148 };
149 };
151 cooling-maps {
152 map0 {
153 trip = <&cpu_alert>;
154 cooling-device =
155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
157 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
163 };
164 };
165 };
166 };
168 timer {
169 compatible = "arm,armv8-timer";
170 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
171 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
172 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
173 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
174 };
176 psci {
177 compatible = "arm,psci-0.2";
178 method = "smc";
179 };
181 sysclk: sysclk {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <100000000>;
185 clock-output-names = "sysclk";
186 };
188 soc {
189 compatible = "simple-bus";
190 #address-cells = <2>;
191 #size-cells = <2>;
192 ranges;
193 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
195 clockgen: clocking@1300000 {
196 compatible = "fsl,ls1088a-clockgen";
197 reg = <0 0x1300000 0 0xa0000>;
198 #clock-cells = <2>;
199 clocks = <&sysclk>;
200 };
202 dcfg: dcfg@1e00000 {
203 compatible = "fsl,ls1088a-dcfg", "syscon";
204 reg = <0x0 0x1e00000 0x0 0x10000>;
205 little-endian;
206 };
208 tmu: tmu@1f80000 {
209 compatible = "fsl,qoriq-tmu";
210 reg = <0x0 0x1f80000 0x0 0x10000>;
211 interrupts = <0 23 0x4>;
212 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
213 fsl,tmu-calibration =
214 /* Calibration data group 1 */
215 <0x00000000 0x00000026
216 0x00000001 0x0000002d
217 0x00000002 0x00000032
218 0x00000003 0x00000039
219 0x00000004 0x0000003f
220 0x00000005 0x00000046
221 0x00000006 0x0000004d
222 0x00000007 0x00000054
223 0x00000008 0x0000005a
224 0x00000009 0x00000061
225 0x0000000a 0x0000006a
226 0x0000000b 0x00000071
227 /* Calibration data group 2 */
228 0x00010000 0x00000025
229 0x00010001 0x0000002c
230 0x00010002 0x00000035
231 0x00010003 0x0000003d
232 0x00010004 0x00000045
233 0x00010005 0x0000004e
234 0x00010006 0x00000057
235 0x00010007 0x00000061
236 0x00010008 0x0000006b
237 0x00010009 0x00000076
238 /* Calibration data group 3 */
239 0x00020000 0x00000029
240 0x00020001 0x00000033
241 0x00020002 0x0000003d
242 0x00020003 0x00000049
243 0x00020004 0x00000056
244 0x00020005 0x00000061
245 0x00020006 0x0000006d
246 /* Calibration data group 4 */
247 0x00030000 0x00000021
248 0x00030001 0x0000002a
249 0x00030002 0x0000003c
250 0x00030003 0x0000004e>;
251 little-endian;
252 #thermal-sensor-cells = <1>;
253 };
255 dspi: spi@2100000 {
256 compatible = "fsl,ls1088a-dspi",
257 "fsl,ls1021a-v1.0-dspi";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x0 0x2100000 0x0 0x10000>;
261 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
262 clock-names = "dspi";
263 clocks = <&clockgen 4 1>;
264 spi-num-chipselects = <6>;
265 status = "disabled";
266 };
268 duart0: serial@21c0500 {
269 compatible = "fsl,ns16550", "ns16550a";
270 reg = <0x0 0x21c0500 0x0 0x100>;
271 clocks = <&clockgen 4 3>;
272 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
273 status = "disabled";
274 };
276 duart1: serial@21c0600 {
277 compatible = "fsl,ns16550", "ns16550a";
278 reg = <0x0 0x21c0600 0x0 0x100>;
279 clocks = <&clockgen 4 3>;
280 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
281 status = "disabled";
282 };
284 gpio0: gpio@2300000 {
285 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
286 reg = <0x0 0x2300000 0x0 0x10000>;
287 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
288 little-endian;
289 gpio-controller;
290 #gpio-cells = <2>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 };
295 gpio1: gpio@2310000 {
296 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
297 reg = <0x0 0x2310000 0x0 0x10000>;
298 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
299 little-endian;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 };
306 gpio2: gpio@2320000 {
307 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
308 reg = <0x0 0x2320000 0x0 0x10000>;
309 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
310 little-endian;
311 gpio-controller;
312 #gpio-cells = <2>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 };
317 gpio3: gpio@2330000 {
318 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
319 reg = <0x0 0x2330000 0x0 0x10000>;
320 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
321 little-endian;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 };
328 ifc: ifc@2240000 {
329 compatible = "fsl,ifc", "simple-bus";
330 reg = <0x0 0x2240000 0x0 0x20000>;
331 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
332 little-endian;
333 #address-cells = <2>;
334 #size-cells = <1>;
335 status = "disabled";
336 };
338 i2c0: i2c@2000000 {
339 compatible = "fsl,vf610-i2c";
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0x0 0x2000000 0x0 0x10000>;
343 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clockgen 4 7>;
345 status = "disabled";
346 };
348 i2c1: i2c@2010000 {
349 compatible = "fsl,vf610-i2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <0x0 0x2010000 0x0 0x10000>;
353 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clockgen 4 7>;
355 status = "disabled";
356 };
358 i2c2: i2c@2020000 {
359 compatible = "fsl,vf610-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x0 0x2020000 0x0 0x10000>;
363 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clockgen 4 7>;
365 status = "disabled";
366 };
368 i2c3: i2c@2030000 {
369 compatible = "fsl,vf610-i2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 reg = <0x0 0x2030000 0x0 0x10000>;
373 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clockgen 4 7>;
375 status = "disabled";
376 };
378 esdhc: esdhc@2140000 {
379 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
380 reg = <0x0 0x2140000 0x0 0x10000>;
381 interrupts = <0 28 0x4>; /* Level high type */
382 clock-frequency = <0>;
383 voltage-ranges = <1800 1800 3300 3300>;
384 sdhci,auto-cmd12;
385 little-endian;
386 bus-width = <4>;
387 status = "disabled";
388 };
390 usb0: usb3@3100000 {
391 compatible = "snps,dwc3";
392 reg = <0x0 0x3100000 0x0 0x10000>;
393 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
394 dr_mode = "host";
395 snps,quirk-frame-length-adjustment = <0x20>;
396 snps,dis_rxdet_inp3_quirk;
397 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
398 status = "disabled";
399 };
401 usb1: usb3@3110000 {
402 compatible = "snps,dwc3";
403 reg = <0x0 0x3110000 0x0 0x10000>;
404 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
405 dr_mode = "host";
406 snps,quirk-frame-length-adjustment = <0x20>;
407 snps,dis_rxdet_inp3_quirk;
408 status = "disabled";
409 };
411 sata: sata@3200000 {
412 compatible = "fsl,ls1088a-ahci";
413 reg = <0x0 0x3200000 0x0 0x10000>,
414 <0x7 0x100520 0x0 0x4>;
415 reg-names = "ahci", "sata-ecc";
416 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clockgen 4 3>;
418 dma-coherent;
419 status = "disabled";
420 };
422 crypto: crypto@8000000 {
423 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
424 fsl,sec-era = <8>;
425 #address-cells = <1>;
426 #size-cells = <1>;
427 ranges = <0x0 0x00 0x8000000 0x100000>;
428 reg = <0x00 0x8000000 0x0 0x100000>;
429 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
430 dma-coherent;
432 sec_jr0: jr@10000 {
433 compatible = "fsl,sec-v5.0-job-ring",
434 "fsl,sec-v4.0-job-ring";
435 reg = <0x10000 0x10000>;
436 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
437 };
439 sec_jr1: jr@20000 {
440 compatible = "fsl,sec-v5.0-job-ring",
441 "fsl,sec-v4.0-job-ring";
442 reg = <0x20000 0x10000>;
443 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
444 };
446 sec_jr2: jr@30000 {
447 compatible = "fsl,sec-v5.0-job-ring",
448 "fsl,sec-v4.0-job-ring";
449 reg = <0x30000 0x10000>;
450 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
451 };
453 sec_jr3: jr@40000 {
454 compatible = "fsl,sec-v5.0-job-ring",
455 "fsl,sec-v4.0-job-ring";
456 reg = <0x40000 0x10000>;
457 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
458 };
459 };
461 pcie@3400000 {
462 compatible = "fsl,ls1088a-pcie";
463 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
464 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
465 reg-names = "regs", "config";
466 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
467 interrupt-names = "aer";
468 #address-cells = <3>;
469 #size-cells = <2>;
470 device_type = "pci";
471 dma-coherent;
472 num-viewport = <256>;
473 bus-range = <0x0 0xff>;
474 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
475 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
476 msi-parent = <&its>;
477 #interrupt-cells = <1>;
478 interrupt-map-mask = <0 0 0 7>;
479 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
480 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
481 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
482 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
483 status = "disabled";
484 };
486 pcie@3500000 {
487 compatible = "fsl,ls1088a-pcie";
488 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
489 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
490 reg-names = "regs", "config";
491 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
492 interrupt-names = "aer";
493 #address-cells = <3>;
494 #size-cells = <2>;
495 device_type = "pci";
496 dma-coherent;
497 num-viewport = <6>;
498 bus-range = <0x0 0xff>;
499 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
500 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
501 msi-parent = <&its>;
502 #interrupt-cells = <1>;
503 interrupt-map-mask = <0 0 0 7>;
504 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
505 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
506 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
507 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
508 status = "disabled";
509 };
511 pcie@3600000 {
512 compatible = "fsl,ls1088a-pcie";
513 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
514 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
515 reg-names = "regs", "config";
516 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
517 interrupt-names = "aer";
518 #address-cells = <3>;
519 #size-cells = <2>;
520 device_type = "pci";
521 dma-coherent;
522 num-viewport = <6>;
523 bus-range = <0x0 0xff>;
524 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
525 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
526 msi-parent = <&its>;
527 #interrupt-cells = <1>;
528 interrupt-map-mask = <0 0 0 7>;
529 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
530 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
531 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
532 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
533 status = "disabled";
534 };
536 smmu: iommu@5000000 {
537 compatible = "arm,mmu-500";
538 reg = <0 0x5000000 0 0x800000>;
539 #iommu-cells = <1>;
540 stream-match-mask = <0x7C00>;
541 #global-interrupts = <12>;
542 // global secure fault
543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
544 // combined secure
545 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
546 // global non-secure fault
547 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
548 // combined non-secure
549 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
550 // performance counter interrupts 0-7
551 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
559 // per context interrupt, 64 interrupts
560 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
624 };
626 console@8340020 {
627 compatible = "fsl,dpaa2-console";
628 reg = <0x00000000 0x08340020 0 0x2>;
629 };
631 ptp-timer@8b95000 {
632 compatible = "fsl,dpaa2-ptp";
633 reg = <0x0 0x8b95000 0x0 0x100>;
634 clocks = <&clockgen 4 0>;
635 little-endian;
636 fsl,extts-fifo;
637 };
639 cluster1_core0_watchdog: wdt@c000000 {
640 compatible = "arm,sp805-wdt", "arm,primecell";
641 reg = <0x0 0xc000000 0x0 0x1000>;
642 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
643 clock-names = "apb_pclk", "wdog_clk";
644 };
646 cluster1_core1_watchdog: wdt@c010000 {
647 compatible = "arm,sp805-wdt", "arm,primecell";
648 reg = <0x0 0xc010000 0x0 0x1000>;
649 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
650 clock-names = "apb_pclk", "wdog_clk";
651 };
653 cluster1_core2_watchdog: wdt@c020000 {
654 compatible = "arm,sp805-wdt", "arm,primecell";
655 reg = <0x0 0xc020000 0x0 0x1000>;
656 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
657 clock-names = "apb_pclk", "wdog_clk";
658 };
660 cluster1_core3_watchdog: wdt@c030000 {
661 compatible = "arm,sp805-wdt", "arm,primecell";
662 reg = <0x0 0xc030000 0x0 0x1000>;
663 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
664 clock-names = "apb_pclk", "wdog_clk";
665 };
667 cluster2_core0_watchdog: wdt@c100000 {
668 compatible = "arm,sp805-wdt", "arm,primecell";
669 reg = <0x0 0xc100000 0x0 0x1000>;
670 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
671 clock-names = "apb_pclk", "wdog_clk";
672 };
674 cluster2_core1_watchdog: wdt@c110000 {
675 compatible = "arm,sp805-wdt", "arm,primecell";
676 reg = <0x0 0xc110000 0x0 0x1000>;
677 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
678 clock-names = "apb_pclk", "wdog_clk";
679 };
681 cluster2_core2_watchdog: wdt@c120000 {
682 compatible = "arm,sp805-wdt", "arm,primecell";
683 reg = <0x0 0xc120000 0x0 0x1000>;
684 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
685 clock-names = "apb_pclk", "wdog_clk";
686 };
688 cluster2_core3_watchdog: wdt@c130000 {
689 compatible = "arm,sp805-wdt", "arm,primecell";
690 reg = <0x0 0xc130000 0x0 0x1000>;
691 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
692 clock-names = "apb_pclk", "wdog_clk";
693 };
695 fsl_mc: fsl-mc@80c000000 {
696 compatible = "fsl,qoriq-mc";
697 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
698 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
699 msi-parent = <&its>;
700 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
701 dma-coherent;
702 #address-cells = <3>;
703 #size-cells = <1>;
705 /*
706 * Region type 0x0 - MC portals
707 * Region type 0x1 - QBMAN portals
708 */
709 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
710 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
712 dpmacs {
713 #address-cells = <1>;
714 #size-cells = <0>;
716 dpmac1: dpmac@1 {
717 compatible = "fsl,qoriq-mc-dpmac";
718 reg = <1>;
719 };
721 dpmac2: dpmac@2 {
722 compatible = "fsl,qoriq-mc-dpmac";
723 reg = <2>;
724 };
726 dpmac3: dpmac@3 {
727 compatible = "fsl,qoriq-mc-dpmac";
728 reg = <3>;
729 };
731 dpmac4: dpmac@4 {
732 compatible = "fsl,qoriq-mc-dpmac";
733 reg = <4>;
734 };
736 dpmac5: dpmac@5 {
737 compatible = "fsl,qoriq-mc-dpmac";
738 reg = <5>;
739 };
741 dpmac6: dpmac@6 {
742 compatible = "fsl,qoriq-mc-dpmac";
743 reg = <6>;
744 };
746 dpmac7: dpmac@7 {
747 compatible = "fsl,qoriq-mc-dpmac";
748 reg = <7>;
749 };
751 dpmac8: dpmac@8 {
752 compatible = "fsl,qoriq-mc-dpmac";
753 reg = <8>;
754 };
756 dpmac9: dpmac@9 {
757 compatible = "fsl,qoriq-mc-dpmac";
758 reg = <9>;
759 };
761 dpmac10: dpmac@a {
762 compatible = "fsl,qoriq-mc-dpmac";
763 reg = <0xa>;
764 };
765 };
766 };
767 };
769 firmware {
770 optee {
771 compatible = "linaro,optee-tz";
772 method = "smc";
773 };
774 };
775 };