| blob | 3d95b66a2d71c0fa97aba2e37d8855c44d295706 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &fec1;
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 i2c3 = &i2c4;
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 spi0 = &ecspi1;
30 spi1 = &ecspi2;
31 spi2 = &ecspi3;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 gpio0 = &gpio1;
36 gpio1 = &gpio2;
37 gpio2 = &gpio3;
38 gpio3 = &gpio4;
39 gpio4 = &gpio5;
40 };
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>; /* two CLK32 periods */
64 clocks = <&clk IMX8MM_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 };
73 A53_1: cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x1>;
77 clock-latency = <61036>; /* two CLK32 periods */
78 clocks = <&clk IMX8MM_CLK_ARM>;
79 enable-method = "psci";
80 next-level-cache = <&A53_L2>;
81 operating-points-v2 = <&a53_opp_table>;
82 cpu-idle-states = <&cpu_pd_wait>;
83 };
85 A53_2: cpu@2 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a53";
88 reg = <0x2>;
89 clock-latency = <61036>; /* two CLK32 periods */
90 clocks = <&clk IMX8MM_CLK_ARM>;
91 enable-method = "psci";
92 next-level-cache = <&A53_L2>;
93 operating-points-v2 = <&a53_opp_table>;
94 cpu-idle-states = <&cpu_pd_wait>;
95 };
97 A53_3: cpu@3 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53";
100 reg = <0x3>;
101 clock-latency = <61036>; /* two CLK32 periods */
102 clocks = <&clk IMX8MM_CLK_ARM>;
103 enable-method = "psci";
104 next-level-cache = <&A53_L2>;
105 operating-points-v2 = <&a53_opp_table>;
106 cpu-idle-states = <&cpu_pd_wait>;
107 };
109 A53_L2: l2-cache0 {
110 compatible = "cache";
111 };
112 };
114 a53_opp_table: opp-table {
115 compatible = "operating-points-v2";
116 opp-shared;
118 opp-1200000000 {
119 opp-hz = /bits/ 64 <1200000000>;
120 opp-microvolt = <850000>;
121 opp-supported-hw = <0xe>, <0x7>;
122 clock-latency-ns = <150000>;
123 opp-suspend;
124 };
126 opp-1600000000 {
127 opp-hz = /bits/ 64 <1600000000>;
128 opp-microvolt = <900000>;
129 opp-supported-hw = <0xc>, <0x7>;
130 clock-latency-ns = <150000>;
131 opp-suspend;
132 };
134 opp-1800000000 {
135 opp-hz = /bits/ 64 <1800000000>;
136 opp-microvolt = <1000000>;
137 opp-supported-hw = <0x8>, <0x3>;
138 clock-latency-ns = <150000>;
139 opp-suspend;
140 };
141 };
143 memory@40000000 {
144 device_type = "memory";
145 reg = <0x0 0x40000000 0 0x80000000>;
146 };
148 osc_32k: clock-osc-32k {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <32768>;
152 clock-output-names = "osc_32k";
153 };
155 osc_24m: clock-osc-24m {
156 compatible = "fixed-clock";
157 #clock-cells = <0>;
158 clock-frequency = <24000000>;
159 clock-output-names = "osc_24m";
160 };
162 clk_ext1: clock-ext1 {
163 compatible = "fixed-clock";
164 #clock-cells = <0>;
165 clock-frequency = <133000000>;
166 clock-output-names = "clk_ext1";
167 };
169 clk_ext2: clock-ext2 {
170 compatible = "fixed-clock";
171 #clock-cells = <0>;
172 clock-frequency = <133000000>;
173 clock-output-names = "clk_ext2";
174 };
176 clk_ext3: clock-ext3 {
177 compatible = "fixed-clock";
178 #clock-cells = <0>;
179 clock-frequency = <133000000>;
180 clock-output-names = "clk_ext3";
181 };
183 clk_ext4: clock-ext4 {
184 compatible = "fixed-clock";
185 #clock-cells = <0>;
186 clock-frequency= <133000000>;
187 clock-output-names = "clk_ext4";
188 };
190 psci {
191 compatible = "arm,psci-1.0";
192 method = "smc";
193 };
195 pmu {
196 compatible = "arm,armv8-pmuv3";
197 interrupts = <GIC_PPI 7
198 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
199 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
200 };
202 timer {
203 compatible = "arm,armv8-timer";
204 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
207 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
208 clock-frequency = <8000000>;
209 arm,no-tick-in-suspend;
210 };
212 usbphynop1: usbphynop1 {
213 compatible = "usb-nop-xceiv";
214 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
215 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
216 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
217 clock-names = "main_clk";
218 };
220 usbphynop2: usbphynop2 {
221 compatible = "usb-nop-xceiv";
222 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
223 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
224 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
225 clock-names = "main_clk";
226 };
228 soc@0 {
229 compatible = "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0x0 0x0 0x0 0x3e000000>;
234 aips1: bus@30000000 {
235 compatible = "fsl,aips-bus", "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0x30000000 0x30000000 0x400000>;
240 sai1: sai@30010000 {
241 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
242 reg = <0x30010000 0x10000>;
243 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
245 <&clk IMX8MM_CLK_SAI1_ROOT>,
246 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
247 clock-names = "bus", "mclk1", "mclk2", "mclk3";
248 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
249 dma-names = "rx", "tx";
250 status = "disabled";
251 };
253 sai2: sai@30020000 {
254 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
255 reg = <0x30020000 0x10000>;
256 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
258 <&clk IMX8MM_CLK_SAI2_ROOT>,
259 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
260 clock-names = "bus", "mclk1", "mclk2", "mclk3";
261 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
262 dma-names = "rx", "tx";
263 status = "disabled";
264 };
266 sai3: sai@30030000 {
267 #sound-dai-cells = <0>;
268 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
269 reg = <0x30030000 0x10000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
272 <&clk IMX8MM_CLK_SAI3_ROOT>,
273 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
274 clock-names = "bus", "mclk1", "mclk2", "mclk3";
275 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
276 dma-names = "rx", "tx";
277 status = "disabled";
278 };
280 sai5: sai@30050000 {
281 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
282 reg = <0x30050000 0x10000>;
283 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
285 <&clk IMX8MM_CLK_SAI5_ROOT>,
286 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
287 clock-names = "bus", "mclk1", "mclk2", "mclk3";
288 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
293 sai6: sai@30060000 {
294 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
295 reg = <0x30060000 0x10000>;
296 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
298 <&clk IMX8MM_CLK_SAI6_ROOT>,
299 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
300 clock-names = "bus", "mclk1", "mclk2", "mclk3";
301 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
302 dma-names = "rx", "tx";
303 status = "disabled";
304 };
306 gpio1: gpio@30200000 {
307 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
308 reg = <0x30200000 0x10000>;
309 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 gpio-ranges = <&iomuxc 0 10 30>;
317 };
319 gpio2: gpio@30210000 {
320 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
321 reg = <0x30210000 0x10000>;
322 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 gpio-ranges = <&iomuxc 0 40 21>;
330 };
332 gpio3: gpio@30220000 {
333 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
334 reg = <0x30220000 0x10000>;
335 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 gpio-ranges = <&iomuxc 0 61 26>;
343 };
345 gpio4: gpio@30230000 {
346 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
347 reg = <0x30230000 0x10000>;
348 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 gpio-ranges = <&iomuxc 0 87 32>;
356 };
358 gpio5: gpio@30240000 {
359 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
360 reg = <0x30240000 0x10000>;
361 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 gpio-ranges = <&iomuxc 0 119 30>;
369 };
371 wdog1: watchdog@30280000 {
372 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
373 reg = <0x30280000 0x10000>;
374 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
376 status = "disabled";
377 };
379 wdog2: watchdog@30290000 {
380 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
381 reg = <0x30290000 0x10000>;
382 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
384 status = "disabled";
385 };
387 wdog3: watchdog@302a0000 {
388 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
389 reg = <0x302a0000 0x10000>;
390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
392 status = "disabled";
393 };
395 sdma2: dma-controller@302c0000 {
396 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
397 reg = <0x302c0000 0x10000>;
398 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
400 <&clk IMX8MM_CLK_SDMA2_ROOT>;
401 clock-names = "ipg", "ahb";
402 #dma-cells = <3>;
403 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
404 };
406 sdma3: dma-controller@302b0000 {
407 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
408 reg = <0x302b0000 0x10000>;
409 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
411 <&clk IMX8MM_CLK_SDMA3_ROOT>;
412 clock-names = "ipg", "ahb";
413 #dma-cells = <3>;
414 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
415 };
417 iomuxc: pinctrl@30330000 {
418 compatible = "fsl,imx8mm-iomuxc";
419 reg = <0x30330000 0x10000>;
420 };
422 gpr: iomuxc-gpr@30340000 {
423 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
424 reg = <0x30340000 0x10000>;
425 };
427 ocotp: ocotp-ctrl@30350000 {
428 compatible = "fsl,imx8mm-ocotp", "syscon";
429 reg = <0x30350000 0x10000>;
430 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
431 /* For nvmem subnodes */
432 #address-cells = <1>;
433 #size-cells = <1>;
435 cpu_speed_grade: speed-grade@10 {
436 reg = <0x10 4>;
437 };
438 };
440 anatop: anatop@30360000 {
441 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
442 reg = <0x30360000 0x10000>;
443 };
445 snvs: snvs@30370000 {
446 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
447 reg = <0x30370000 0x10000>;
449 snvs_rtc: snvs-rtc-lp {
450 compatible = "fsl,sec-v4.0-mon-rtc-lp";
451 regmap = <&snvs>;
452 offset = <0x34>;
453 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
456 clock-names = "snvs-rtc";
457 };
459 snvs_pwrkey: snvs-powerkey {
460 compatible = "fsl,sec-v4.0-pwrkey";
461 regmap = <&snvs>;
462 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
463 linux,keycode = <KEY_POWER>;
464 wakeup-source;
465 status = "disabled";
466 };
467 };
469 clk: clock-controller@30380000 {
470 compatible = "fsl,imx8mm-ccm";
471 reg = <0x30380000 0x10000>;
472 #clock-cells = <1>;
473 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
474 <&clk_ext3>, <&clk_ext4>;
475 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
476 "clk_ext3", "clk_ext4";
477 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
478 <&clk IMX8MM_CLK_AUDIO_AHB>,
479 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
480 <&clk IMX8MM_SYS_PLL3>,
481 <&clk IMX8MM_VIDEO_PLL1>,
482 <&clk IMX8MM_AUDIO_PLL1>,
483 <&clk IMX8MM_AUDIO_PLL2>;
484 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
485 <&clk IMX8MM_SYS_PLL1_800M>;
486 assigned-clock-rates = <0>,
487 <400000000>,
488 <400000000>,
489 <750000000>,
490 <594000000>,
491 <393216000>,
492 <361267200>;
493 };
495 src: reset-controller@30390000 {
496 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
497 reg = <0x30390000 0x10000>;
498 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
499 #reset-cells = <1>;
500 };
501 };
503 aips2: bus@30400000 {
504 compatible = "fsl,aips-bus", "simple-bus";
505 #address-cells = <1>;
506 #size-cells = <1>;
507 ranges = <0x30400000 0x30400000 0x400000>;
509 pwm1: pwm@30660000 {
510 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
511 reg = <0x30660000 0x10000>;
512 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
514 <&clk IMX8MM_CLK_PWM1_ROOT>;
515 clock-names = "ipg", "per";
516 #pwm-cells = <2>;
517 status = "disabled";
518 };
520 pwm2: pwm@30670000 {
521 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
522 reg = <0x30670000 0x10000>;
523 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
525 <&clk IMX8MM_CLK_PWM2_ROOT>;
526 clock-names = "ipg", "per";
527 #pwm-cells = <2>;
528 status = "disabled";
529 };
531 pwm3: pwm@30680000 {
532 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
533 reg = <0x30680000 0x10000>;
534 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
536 <&clk IMX8MM_CLK_PWM3_ROOT>;
537 clock-names = "ipg", "per";
538 #pwm-cells = <2>;
539 status = "disabled";
540 };
542 pwm4: pwm@30690000 {
543 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
544 reg = <0x30690000 0x10000>;
545 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
547 <&clk IMX8MM_CLK_PWM4_ROOT>;
548 clock-names = "ipg", "per";
549 #pwm-cells = <2>;
550 status = "disabled";
551 };
553 system_counter: timer@306a0000 {
554 compatible = "nxp,sysctr-timer";
555 reg = <0x306a0000 0x20000>;
556 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&osc_24m>;
558 clock-names = "per";
559 };
560 };
562 aips3: bus@30800000 {
563 compatible = "fsl,aips-bus", "simple-bus";
564 #address-cells = <1>;
565 #size-cells = <1>;
566 ranges = <0x30800000 0x30800000 0x400000>;
568 ecspi1: spi@30820000 {
569 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 reg = <0x30820000 0x10000>;
573 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
575 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
576 clock-names = "ipg", "per";
577 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
578 dma-names = "rx", "tx";
579 status = "disabled";
580 };
582 ecspi2: spi@30830000 {
583 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 reg = <0x30830000 0x10000>;
587 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
589 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
590 clock-names = "ipg", "per";
591 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
592 dma-names = "rx", "tx";
593 status = "disabled";
594 };
596 ecspi3: spi@30840000 {
597 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
598 #address-cells = <1>;
599 #size-cells = <0>;
600 reg = <0x30840000 0x10000>;
601 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
603 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
604 clock-names = "ipg", "per";
605 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
606 dma-names = "rx", "tx";
607 status = "disabled";
608 };
610 uart1: serial@30860000 {
611 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
612 reg = <0x30860000 0x10000>;
613 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
615 <&clk IMX8MM_CLK_UART1_ROOT>;
616 clock-names = "ipg", "per";
617 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
618 dma-names = "rx", "tx";
619 status = "disabled";
620 };
622 uart3: serial@30880000 {
623 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
624 reg = <0x30880000 0x10000>;
625 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
627 <&clk IMX8MM_CLK_UART3_ROOT>;
628 clock-names = "ipg", "per";
629 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
630 dma-names = "rx", "tx";
631 status = "disabled";
632 };
634 uart2: serial@30890000 {
635 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
636 reg = <0x30890000 0x10000>;
637 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
639 <&clk IMX8MM_CLK_UART2_ROOT>;
640 clock-names = "ipg", "per";
641 status = "disabled";
642 };
644 i2c1: i2c@30a20000 {
645 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
646 #address-cells = <1>;
647 #size-cells = <0>;
648 reg = <0x30a20000 0x10000>;
649 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
651 status = "disabled";
652 };
654 i2c2: i2c@30a30000 {
655 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
656 #address-cells = <1>;
657 #size-cells = <0>;
658 reg = <0x30a30000 0x10000>;
659 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
661 status = "disabled";
662 };
664 i2c3: i2c@30a40000 {
665 #address-cells = <1>;
666 #size-cells = <0>;
667 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
668 reg = <0x30a40000 0x10000>;
669 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
671 status = "disabled";
672 };
674 i2c4: i2c@30a50000 {
675 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 reg = <0x30a50000 0x10000>;
679 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
681 status = "disabled";
682 };
684 uart4: serial@30a60000 {
685 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
686 reg = <0x30a60000 0x10000>;
687 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
689 <&clk IMX8MM_CLK_UART4_ROOT>;
690 clock-names = "ipg", "per";
691 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
696 usdhc1: mmc@30b40000 {
697 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
698 reg = <0x30b40000 0x10000>;
699 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
701 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
702 <&clk IMX8MM_CLK_USDHC1_ROOT>;
703 clock-names = "ipg", "ahb", "per";
704 fsl,tuning-start-tap = <20>;
705 fsl,tuning-step= <2>;
706 bus-width = <4>;
707 status = "disabled";
708 };
710 usdhc2: mmc@30b50000 {
711 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
712 reg = <0x30b50000 0x10000>;
713 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
715 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
716 <&clk IMX8MM_CLK_USDHC2_ROOT>;
717 clock-names = "ipg", "ahb", "per";
718 fsl,tuning-start-tap = <20>;
719 fsl,tuning-step= <2>;
720 bus-width = <4>;
721 status = "disabled";
722 };
724 usdhc3: mmc@30b60000 {
725 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
726 reg = <0x30b60000 0x10000>;
727 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
729 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
730 <&clk IMX8MM_CLK_USDHC3_ROOT>;
731 clock-names = "ipg", "ahb", "per";
732 fsl,tuning-start-tap = <20>;
733 fsl,tuning-step= <2>;
734 bus-width = <4>;
735 status = "disabled";
736 };
738 sdma1: dma-controller@30bd0000 {
739 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
740 reg = <0x30bd0000 0x10000>;
741 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
743 <&clk IMX8MM_CLK_AHB>;
744 clock-names = "ipg", "ahb";
745 #dma-cells = <3>;
746 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
747 };
749 fec1: ethernet@30be0000 {
750 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
751 reg = <0x30be0000 0x10000>;
752 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
756 <&clk IMX8MM_CLK_ENET1_ROOT>,
757 <&clk IMX8MM_CLK_ENET_TIMER>,
758 <&clk IMX8MM_CLK_ENET_REF>,
759 <&clk IMX8MM_CLK_ENET_PHY_REF>;
760 clock-names = "ipg", "ahb", "ptp",
761 "enet_clk_ref", "enet_out";
762 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
763 <&clk IMX8MM_CLK_ENET_TIMER>,
764 <&clk IMX8MM_CLK_ENET_REF>,
765 <&clk IMX8MM_CLK_ENET_TIMER>;
766 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
767 <&clk IMX8MM_SYS_PLL2_100M>,
768 <&clk IMX8MM_SYS_PLL2_125M>;
769 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
770 fsl,num-tx-queues = <3>;
771 fsl,num-rx-queues = <3>;
772 status = "disabled";
773 };
775 };
777 aips4: bus@32c00000 {
778 compatible = "fsl,aips-bus", "simple-bus";
779 #address-cells = <1>;
780 #size-cells = <1>;
781 ranges = <0x32c00000 0x32c00000 0x400000>;
783 usbotg1: usb@32e40000 {
784 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
785 reg = <0x32e40000 0x200>;
786 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
788 clock-names = "usb1_ctrl_root_clk";
789 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
790 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
791 fsl,usbphy = <&usbphynop1>;
792 fsl,usbmisc = <&usbmisc1 0>;
793 status = "disabled";
794 };
796 usbmisc1: usbmisc@32e40200 {
797 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
798 #index-cells = <1>;
799 reg = <0x32e40200 0x200>;
800 };
802 usbotg2: usb@32e50000 {
803 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
804 reg = <0x32e50000 0x200>;
805 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
807 clock-names = "usb1_ctrl_root_clk";
808 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
809 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
810 fsl,usbphy = <&usbphynop2>;
811 fsl,usbmisc = <&usbmisc2 0>;
812 status = "disabled";
813 };
815 usbmisc2: usbmisc@32e50200 {
816 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
817 #index-cells = <1>;
818 reg = <0x32e50200 0x200>;
819 };
821 };
823 dma_apbh: dma-controller@33000000 {
824 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
825 reg = <0x33000000 0x2000>;
826 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
830 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
831 #dma-cells = <1>;
832 dma-channels = <4>;
833 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
834 };
836 gpmi: nand-controller@33002000{
837 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
838 #address-cells = <1>;
839 #size-cells = <1>;
840 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
841 reg-names = "gpmi-nand", "bch";
842 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
843 interrupt-names = "bch";
844 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
845 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
846 clock-names = "gpmi_io", "gpmi_bch_apb";
847 dmas = <&dma_apbh 0>;
848 dma-names = "rx-tx";
849 status = "disabled";
850 };
852 gic: interrupt-controller@38800000 {
853 compatible = "arm,gic-v3";
854 reg = <0x38800000 0x10000>, /* GIC Dist */
855 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
856 #interrupt-cells = <3>;
857 interrupt-controller;
858 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
859 };
861 ddr-pmu@3d800000 {
862 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
863 reg = <0x3d800000 0x400000>;
864 interrupt-parent = <&gic>;
865 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
866 };
867 };
868 };