arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include "imx8mn.dtsi"
   7
   8 / {
   9         chosen {
  10                 stdout-path = &uart2;
  11         };
  12
  13         gpio-leds {
  14                 compatible = "gpio-leds";
  15                 pinctrl-names = "default";
  16                 pinctrl-0 = <&pinctrl_gpio_led>;
  17
  18                 status {
  19                         label = "yellow:status";
  20                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  21                         default-state = "on";
  22                 };
  23         };
  24
  25         reg_usdhc2_vmmc: regulator-usdhc2 {
  26                 compatible = "regulator-fixed";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  29                 regulator-name = "VSD_3V3";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  33                 enable-active-high;
  34         };
  35 };
  36
  37 &fec1 {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_fec1>;
  40         phy-mode = "rgmii-id";
  41         phy-handle = <&ethphy0>;
  42         fsl,magic-packet;
  43         status = "okay";
  44
  45         mdio {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48
  49                 ethphy0: ethernet-phy@0 {
  50                         compatible = "ethernet-phy-ieee802.3-c22";
  51                         reg = <0>;
  52                 };
  53         };
  54 };
  55
  56 &i2c1 {
  57         clock-frequency = <400000>;
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_i2c1>;
  60         status = "okay";
  61 };
  62
  63 &snvs_pwrkey {
  64         status = "okay";
  65 };
  66
  67 &uart2 { /* console */
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_uart2>;
  70         status = "okay";
  71 };
  72
  73 &usdhc2 {
  74         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
  75         assigned-clock-rates = <200000000>;
  76         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  77         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  78         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  79         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  80         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  81         bus-width = <4>;
  82         vmmc-supply = <&reg_usdhc2_vmmc>;
  83         status = "okay";
  84 };
  85
  86 &usdhc3 {
  87         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
  88         assigned-clock-rates = <400000000>;
  89         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  90         pinctrl-0 = <&pinctrl_usdhc3>;
  91         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  92         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  93         bus-width = <8>;
  94         non-removable;
  95         status = "okay";
  96 };
  97
  98 &wdog1 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_wdog>;
 101         fsl,ext-reset-output;
 102         status = "okay";
 103 };
 104
 105 &iomuxc {
 106         pinctrl-names = "default";
 107
 108         pinctrl_fec1: fec1grp {
 109                 fsl,pins = <
 110                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 111                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 112                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 113                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 114                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 115                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 116                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 117                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 118                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 119                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 120                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 121                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 122                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 123                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 124                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 125                 >;
 126         };
 127
 128         pinctrl_gpio_led: gpioledgrp {
 129                 fsl,pins = <
 130                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 131                 >;
 132         };
 133
 134         pinctrl_i2c1: i2c1grp {
 135                 fsl,pins = <
 136                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 137                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 138                 >;
 139         };
 140
 141         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 142                 fsl,pins = <
 143                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 144                 >;
 145         };
 146
 147         pinctrl_uart2: uart2grp {
 148                 fsl,pins = <
 149                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 150                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 151                 >;
 152         };
 153
 154         pinctrl_usdhc2_gpio: usdhc2grpgpio {
 155                 fsl,pins = <
 156                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 157                 >;
 158         };
 159
 160         pinctrl_usdhc2: usdhc2grp {
 161                 fsl,pins = <
 162                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 163                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 164                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 165                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 166                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 167                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 168                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 169                 >;
 170         };
 171
 172         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 173                 fsl,pins = <
 174                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 175                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 176                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 177                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 178                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 179                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 180                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 181                 >;
 182         };
 183
 184         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 185                 fsl,pins = <
 186                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 187                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 188                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 189                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 190                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 191                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 192                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 193                 >;
 194         };
 195
 196         pinctrl_usdhc3: usdhc3grp {
 197                 fsl,pins = <
 198                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 199                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 200                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 201                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 202                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 203                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 204                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 205                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 206                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 207                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 208                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 209                 >;
 210         };
 211
 212         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 213                 fsl,pins = <
 214                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 215                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 216                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 217                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 218                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 219                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 220                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 221                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 222                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 223                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 224                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 225                 >;
 226         };
 227
 228         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 229                 fsl,pins = <
 230                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 231                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 232                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 233                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 234                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 235                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 236                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 237                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 238                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 239                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 240                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 241                 >;
 242         };
 243
 244         pinctrl_wdog: wdoggrp {
 245                 fsl,pins = <
 246                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 247                 >;
 248         };
 249 };