arch/arm64/boot/dts/marvell/cn9130-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9130-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "Marvell Armada CN9130-DB";
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17         };
  18
  19         aliases {
  20                 gpio1 = &cp0_gpio1;
  21                 gpio2 = &cp0_gpio2;
  22                 i2c0 = &cp0_i2c0;
  23                 ethernet0 = &cp0_eth0;
  24                 ethernet1 = &cp0_eth1;
  25                 ethernet2 = &cp0_eth2;
  26                 spi1 = &cp0_spi0;
  27                 spi2 = &cp0_spi1;
  28         };
  29
  30         memory@00000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x0 0x0 0x80000000>;
  33         };
  34
  35         ap0_reg_sd_vccq: ap0_sd_vccq@0 {
  36                 compatible = "regulator-gpio";
  37                 regulator-name = "ap0_sd_vccq";
  38                 regulator-min-microvolt = <1800000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
  41                 states = <1800000 0x1 3300000 0x0>;
  42         };
  43
  44         cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "cp0-xhci0-vbus";
  47                 regulator-min-microvolt = <5000000>;
  48                 regulator-max-microvolt = <5000000>;
  49                 enable-active-high;
  50                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  51         };
  52
  53         cp0_usb3_0_phy0: cp0_usb3_phy@0 {
  54                 compatible = "usb-nop-xceiv";
  55                 vcc-supply = <&cp0_reg_usb3_vbus0>;
  56         };
  57
  58         cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "cp0-xhci1-vbus";
  61                 regulator-min-microvolt = <5000000>;
  62                 regulator-max-microvolt = <5000000>;
  63                 enable-active-high;
  64                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  65         };
  66
  67         cp0_usb3_0_phy1: cp0_usb3_phy@1 {
  68                 compatible = "usb-nop-xceiv";
  69                 vcc-supply = <&cp0_reg_usb3_vbus1>;
  70         };
  71
  72         cp0_reg_sd_vccq: cp0_sd_vccq@0 {
  73                 compatible = "regulator-gpio";
  74                 regulator-name = "cp0_sd_vccq";
  75                 regulator-min-microvolt = <1800000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
  78                 states = <1800000 0x1
  79                           3300000 0x0>;
  80         };
  81
  82         cp0_reg_sd_vcc: cp0_sd_vcc@0 {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "cp0_sd_vcc";
  85                 regulator-min-microvolt = <3300000>;
  86                 regulator-max-microvolt = <3300000>;
  87                 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
  88                 enable-active-high;
  89                 regulator-always-on;
  90         };
  91
  92         cp0_sfp_eth0: sfp-eth@0 {
  93                 compatible = "sff,sfp";
  94                 i2c-bus = <&cp0_sfpp0_i2c>;
  95                 los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
  96                 mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
  97                 tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
  98                 tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
  99                 /*
 100                  * SFP cages are unconnected on early PCBs because of an the I2C
 101                  * lanes not being connected. Prevent the port for being
 102                  * unusable by disabling the SFP node.
 103                  */
 104                 status = "disabled";
 105         };
 106 };
 107
 108 &uart0 {
 109         status = "okay";
 110 };
 111
 112 /* on-board eMMC - U9 */
 113 &ap_sdhci0 {
 114         pinctrl-names = "default";
 115         bus-width = <8>;
 116         vqmmc-supply = <&ap0_reg_sd_vccq>;
 117         status = "okay";
 118 };
 119
 120 &cp0_crypto {
 121         status = "disabled";
 122 };
 123
 124 &cp0_ethernet {
 125         status = "okay";
 126 };
 127
 128 /* SLM-1521-V2, CON9 */
 129 &cp0_eth0 {
 130         status = "disabled";
 131         phy-mode = "10gbase-kr";
 132         /* Generic PHY, providing serdes lanes */
 133         phys = <&cp0_comphy4 0>;
 134         managed = "in-band-status";
 135         sfp = <&cp0_sfp_eth0>;
 136 };
 137
 138 /* CON56 */
 139 &cp0_eth1 {
 140         status = "okay";
 141         phy = <&phy0>;
 142         phy-mode = "rgmii-id";
 143 };
 144
 145 /* CON57 */
 146 &cp0_eth2 {
 147         status = "okay";
 148         phy = <&phy1>;
 149         phy-mode = "rgmii-id";
 150 };
 151
 152 &cp0_gpio1 {
 153         status = "okay";
 154 };
 155
 156 &cp0_gpio2 {
 157         status = "okay";
 158 };
 159
 160 &cp0_i2c0 {
 161         status = "okay";
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&cp0_i2c0_pins>;
 164         clock-frequency = <100000>;
 165
 166         /* U36 */
 167         expander0: pca953x@21 {
 168                 compatible = "nxp,pca9555";
 169                 pinctrl-names = "default";
 170                 gpio-controller;
 171                 #gpio-cells = <2>;
 172                 reg = <0x21>;
 173                 status = "okay";
 174         };
 175
 176         /* U42 */
 177         eeprom0: eeprom@50 {
 178                 compatible = "atmel,24c64";
 179                 reg = <0x50>;
 180                 pagesize = <0x20>;
 181         };
 182
 183         /* U38 */
 184         eeprom1: eeprom@57 {
 185                 compatible = "atmel,24c64";
 186                 reg = <0x57>;
 187                 pagesize = <0x20>;
 188         };
 189 };
 190
 191 &cp0_i2c1 {
 192         status = "okay";
 193         clock-frequency = <100000>;
 194
 195         /* SLM-1521-V2 - U3 */
 196         i2c-mux@72 { /* verify address - depends on dpr */
 197                 compatible = "nxp,pca9544";
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 reg = <0x72>;
 201                 cp0_sfpp0_i2c: i2c@0 {
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         reg = <0>;
 205                 };
 206
 207                 i2c@1 {
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <1>;
 211                         /* U12 */
 212                         cp0_module_expander1: pca9555@21 {
 213                                 compatible = "nxp,pca9555";
 214                                 pinctrl-names = "default";
 215                                 gpio-controller;
 216                                 #gpio-cells = <2>;
 217                                 reg = <0x21>;
 218                         };
 219
 220                 };
 221         };
 222 };
 223
 224 &cp0_mdio {
 225         status = "okay";
 226
 227         phy0: ethernet-phy@0 {
 228                 reg = <0>;
 229         };
 230
 231         phy1: ethernet-phy@1 {
 232                 reg = <1>;
 233         };
 234 };
 235
 236 /* U54 */
 237 &cp0_nand_controller {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&nand_pins &nand_rb>;
 240
 241         nand@0 {
 242                 reg = <0>;
 243                 label = "main-storage";
 244                 nand-rb = <0>;
 245                 nand-ecc-mode = "hw";
 246                 nand-on-flash-bbt;
 247                 nand-ecc-strength = <8>;
 248                 nand-ecc-step-size = <512>;
 249
 250                 partitions {
 251                         compatible = "fixed-partitions";
 252                         #address-cells = <1>;
 253                         #size-cells = <1>;
 254
 255                         partition@0 {
 256                                 label = "U-Boot";
 257                                 reg = <0 0x200000>;
 258                         };
 259                         partition@200000 {
 260                                 label = "Linux";
 261                                 reg = <0x200000 0xd00000>;
 262                         };
 263                         partition@1000000 {
 264                                 label = "Filesystem";
 265                                 reg = <0x1000000 0x3f000000>;
 266                         };
 267                 };
 268         };
 269 };
 270
 271 /* SLM-1521-V2, CON6 */
 272 &cp0_pcie0 {
 273         status = "okay";
 274         num-lanes = <4>;
 275         num-viewport = <8>;
 276         /* Generic PHY, providing serdes lanes */
 277         phys = <&cp0_comphy0 0
 278                 &cp0_comphy1 0
 279                 &cp0_comphy2 0
 280                 &cp0_comphy3 0>;
 281 };
 282
 283 &cp0_sata0 {
 284         status = "okay";
 285
 286         /* SLM-1521-V2, CON2 */
 287         sata-port@1 {
 288                 status = "okay";
 289                 /* Generic PHY, providing serdes lanes */
 290                 phys = <&cp0_comphy5 1>;
 291         };
 292 };
 293
 294 /* CON 28 */
 295 &cp0_sdhci0 {
 296         status = "okay";
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&cp0_sdhci_pins
 299                      &cp0_sdhci_cd_pins>;
 300         bus-width = <4>;
 301         cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
 302         no-1-8-v;
 303         vqmmc-supply = <&cp0_reg_sd_vccq>;
 304         vmmc-supply = <&cp0_reg_sd_vcc>;
 305 };
 306
 307 /* U55 */
 308 &cp0_spi1 {
 309         status = "okay";
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&cp0_spi0_pins>;
 312         reg = <0x700680 0x50>;
 313
 314         spi-flash@0 {
 315                 #address-cells = <0x1>;
 316                 #size-cells = <0x1>;
 317                 compatible = "jedec,spi-nor";
 318                 reg = <0x0>;
 319                 /* On-board MUX does not allow higher frequencies */
 320                 spi-max-frequency = <40000000>;
 321
 322                 partitions {
 323                         compatible = "fixed-partitions";
 324                         #address-cells = <1>;
 325                         #size-cells = <1>;
 326
 327                         partition@0 {
 328                                 label = "U-Boot-0";
 329                                 reg = <0x0 0x200000>;
 330                         };
 331
 332                         partition@400000 {
 333                                 label = "Filesystem-0";
 334                                 reg = <0x200000 0xe00000>;
 335                         };
 336                 };
 337         };
 338 };
 339
 340 &cp0_syscon0 {
 341         cp0_pinctrl: pinctrl {
 342                 compatible = "marvell,cp115-standalone-pinctrl";
 343
 344                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 345                         marvell,pins = "mpp37", "mpp38";
 346                         marvell,function = "i2c0";
 347                 };
 348                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 349                         marvell,pins = "mpp35", "mpp36";
 350                         marvell,function = "i2c1";
 351                 };
 352                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 353                         marvell,pins = "mpp0", "mpp1", "mpp2",
 354                                        "mpp3", "mpp4", "mpp5",
 355                                        "mpp6", "mpp7", "mpp8",
 356                                        "mpp9", "mpp10", "mpp11";
 357                         marvell,function = "ge0";
 358                 };
 359                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 360                         marvell,pins = "mpp44", "mpp45", "mpp46",
 361                                        "mpp47", "mpp48", "mpp49",
 362                                        "mpp50", "mpp51", "mpp52",
 363                                        "mpp53", "mpp54", "mpp55";
 364                         marvell,function = "ge1";
 365                 };
 366                 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
 367                         marvell,pins = "mpp43";
 368                         marvell,function = "gpio";
 369                 };
 370                 cp0_sdhci_pins: cp0-sdhi-pins-0 {
 371                         marvell,pins = "mpp56", "mpp57", "mpp58",
 372                                        "mpp59", "mpp60", "mpp61";
 373                         marvell,function = "sdio";
 374                 };
 375                 cp0_spi0_pins: cp0-spi-pins-0 {
 376                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 377                         marvell,function = "spi1";
 378                 };
 379                 nand_pins: nand-pins {
 380                         marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
 381                                        "mpp19", "mpp20", "mpp21", "mpp22",
 382                                        "mpp23", "mpp24", "mpp25", "mpp26",
 383                                        "mpp27";
 384                         marvell,function = "dev";
 385                 };
 386                 nand_rb: nand-rb {
 387                         marvell,pins = "mpp13";
 388                         marvell,function = "nf";
 389                 };
 390         };
 391 };
 392
 393 &cp0_usb3_0 {
 394         status = "okay";
 395         usb-phy = <&cp0_usb3_0_phy0>;
 396         phy-names = "usb";
 397 };
 398
 399 &cp0_usb3_1 {
 400         status = "okay";
 401         usb-phy = <&cp0_usb3_0_phy1>;
 402         phy-names = "usb";
 403 };