| blob | 4ca2e7b44559cb00c211c1b697d7c3c344fcf1c9 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
11 / {
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 chosen { };
19 memory {
20 device_type = "memory";
21 /* We expect the bootloader to fill in the reg */
22 reg = <0 0 0 0>;
23 };
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
28 ranges;
30 mba_region: mba@91500000 {
31 reg = <0x0 0x91500000 0x0 0x200000>;
32 no-map;
33 };
35 slpi_region: slpi@90b00000 {
36 reg = <0x0 0x90b00000 0x0 0xa00000>;
37 no-map;
38 };
40 venus_region: venus@90400000 {
41 reg = <0x0 0x90400000 0x0 0x700000>;
42 no-map;
43 };
45 adsp_region: adsp@8ea00000 {
46 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
47 no-map;
48 };
50 mpss_region: mpss@88800000 {
51 reg = <0x0 0x88800000 0x0 0x6200000>;
52 no-map;
53 };
55 smem_mem: smem-mem@86000000 {
56 reg = <0x0 0x86000000 0x0 0x200000>;
57 no-map;
58 };
60 memory@85800000 {
61 reg = <0x0 0x85800000 0x0 0x800000>;
62 no-map;
63 };
65 memory@86200000 {
66 reg = <0x0 0x86200000 0x0 0x2600000>;
67 no-map;
68 };
70 rmtfs@86700000 {
71 compatible = "qcom,rmtfs-mem";
73 size = <0x0 0x200000>;
74 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
75 no-map;
77 qcom,client-id = <1>;
78 qcom,vmid = <15>;
79 };
81 zap_shader_region: gpu@8f200000 {
82 compatible = "shared-dma-pool";
83 reg = <0x0 0x90b00000 0x0 0xa00000>;
84 no-map;
85 };
86 };
88 cpus {
89 #address-cells = <2>;
90 #size-cells = <0>;
92 CPU0: cpu@0 {
93 device_type = "cpu";
94 compatible = "qcom,kryo";
95 reg = <0x0 0x0>;
96 enable-method = "psci";
97 cpu-idle-states = <&CPU_SLEEP_0>;
98 capacity-dmips-mhz = <1024>;
99 next-level-cache = <&L2_0>;
100 L2_0: l2-cache {
101 compatible = "cache";
102 cache-level = <2>;
103 };
104 };
106 CPU1: cpu@1 {
107 device_type = "cpu";
108 compatible = "qcom,kryo";
109 reg = <0x0 0x1>;
110 enable-method = "psci";
111 cpu-idle-states = <&CPU_SLEEP_0>;
112 capacity-dmips-mhz = <1024>;
113 next-level-cache = <&L2_0>;
114 };
116 CPU2: cpu@100 {
117 device_type = "cpu";
118 compatible = "qcom,kryo";
119 reg = <0x0 0x100>;
120 enable-method = "psci";
121 cpu-idle-states = <&CPU_SLEEP_0>;
122 capacity-dmips-mhz = <1024>;
123 next-level-cache = <&L2_1>;
124 L2_1: l2-cache {
125 compatible = "cache";
126 cache-level = <2>;
127 };
128 };
130 CPU3: cpu@101 {
131 device_type = "cpu";
132 compatible = "qcom,kryo";
133 reg = <0x0 0x101>;
134 enable-method = "psci";
135 cpu-idle-states = <&CPU_SLEEP_0>;
136 capacity-dmips-mhz = <1024>;
137 next-level-cache = <&L2_1>;
138 };
140 cpu-map {
141 cluster0 {
142 core0 {
143 cpu = <&CPU0>;
144 };
146 core1 {
147 cpu = <&CPU1>;
148 };
149 };
151 cluster1 {
152 core0 {
153 cpu = <&CPU2>;
154 };
156 core1 {
157 cpu = <&CPU3>;
158 };
159 };
160 };
162 idle-states {
163 entry-method = "psci";
165 CPU_SLEEP_0: cpu-sleep-0 {
166 compatible = "arm,idle-state";
167 idle-state-name = "standalone-power-collapse";
168 arm,psci-suspend-param = <0x00000004>;
169 entry-latency-us = <130>;
170 exit-latency-us = <80>;
171 min-residency-us = <300>;
172 };
173 };
174 };
176 thermal-zones {
177 cpu0-thermal {
178 polling-delay-passive = <250>;
179 polling-delay = <1000>;
181 thermal-sensors = <&tsens0 3>;
183 trips {
184 cpu0_alert0: trip-point@0 {
185 temperature = <75000>;
186 hysteresis = <2000>;
187 type = "passive";
188 };
190 cpu0_crit: cpu_crit {
191 temperature = <110000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
196 };
198 cpu1-thermal {
199 polling-delay-passive = <250>;
200 polling-delay = <1000>;
202 thermal-sensors = <&tsens0 5>;
204 trips {
205 cpu1_alert0: trip-point@0 {
206 temperature = <75000>;
207 hysteresis = <2000>;
208 type = "passive";
209 };
211 cpu1_crit: cpu_crit {
212 temperature = <110000>;
213 hysteresis = <2000>;
214 type = "critical";
215 };
216 };
217 };
219 cpu2-thermal {
220 polling-delay-passive = <250>;
221 polling-delay = <1000>;
223 thermal-sensors = <&tsens0 8>;
225 trips {
226 cpu2_alert0: trip-point@0 {
227 temperature = <75000>;
228 hysteresis = <2000>;
229 type = "passive";
230 };
232 cpu2_crit: cpu_crit {
233 temperature = <110000>;
234 hysteresis = <2000>;
235 type = "critical";
236 };
237 };
238 };
240 cpu3-thermal {
241 polling-delay-passive = <250>;
242 polling-delay = <1000>;
244 thermal-sensors = <&tsens0 10>;
246 trips {
247 cpu3_alert0: trip-point@0 {
248 temperature = <75000>;
249 hysteresis = <2000>;
250 type = "passive";
251 };
253 cpu3_crit: cpu_crit {
254 temperature = <110000>;
255 hysteresis = <2000>;
256 type = "critical";
257 };
258 };
259 };
261 gpu-thermal-top {
262 polling-delay-passive = <250>;
263 polling-delay = <1000>;
265 thermal-sensors = <&tsens1 6>;
267 trips {
268 gpu1_alert0: trip-point@0 {
269 temperature = <90000>;
270 hysteresis = <2000>;
271 type = "hot";
272 };
273 };
274 };
276 gpu-thermal-bottom {
277 polling-delay-passive = <250>;
278 polling-delay = <1000>;
280 thermal-sensors = <&tsens1 7>;
282 trips {
283 gpu2_alert0: trip-point@0 {
284 temperature = <90000>;
285 hysteresis = <2000>;
286 type = "hot";
287 };
288 };
289 };
291 m4m-thermal {
292 polling-delay-passive = <250>;
293 polling-delay = <1000>;
295 thermal-sensors = <&tsens0 1>;
297 trips {
298 m4m_alert0: trip-point@0 {
299 temperature = <90000>;
300 hysteresis = <2000>;
301 type = "hot";
302 };
303 };
304 };
306 l3-or-venus-thermal {
307 polling-delay-passive = <250>;
308 polling-delay = <1000>;
310 thermal-sensors = <&tsens0 2>;
312 trips {
313 l3_or_venus_alert0: trip-point@0 {
314 temperature = <90000>;
315 hysteresis = <2000>;
316 type = "hot";
317 };
318 };
319 };
321 cluster0-l2-thermal {
322 polling-delay-passive = <250>;
323 polling-delay = <1000>;
325 thermal-sensors = <&tsens0 7>;
327 trips {
328 cluster0_l2_alert0: trip-point@0 {
329 temperature = <90000>;
330 hysteresis = <2000>;
331 type = "hot";
332 };
333 };
334 };
336 cluster1-l2-thermal {
337 polling-delay-passive = <250>;
338 polling-delay = <1000>;
340 thermal-sensors = <&tsens0 12>;
342 trips {
343 cluster1_l2_alert0: trip-point@0 {
344 temperature = <90000>;
345 hysteresis = <2000>;
346 type = "hot";
347 };
348 };
349 };
351 camera-thermal {
352 polling-delay-passive = <250>;
353 polling-delay = <1000>;
355 thermal-sensors = <&tsens1 1>;
357 trips {
358 camera_alert0: trip-point@0 {
359 temperature = <90000>;
360 hysteresis = <2000>;
361 type = "hot";
362 };
363 };
364 };
366 q6-dsp-thermal {
367 polling-delay-passive = <250>;
368 polling-delay = <1000>;
370 thermal-sensors = <&tsens1 2>;
372 trips {
373 q6_dsp_alert0: trip-point@0 {
374 temperature = <90000>;
375 hysteresis = <2000>;
376 type = "hot";
377 };
378 };
379 };
381 mem-thermal {
382 polling-delay-passive = <250>;
383 polling-delay = <1000>;
385 thermal-sensors = <&tsens1 3>;
387 trips {
388 mem_alert0: trip-point@0 {
389 temperature = <90000>;
390 hysteresis = <2000>;
391 type = "hot";
392 };
393 };
394 };
396 modemtx-thermal {
397 polling-delay-passive = <250>;
398 polling-delay = <1000>;
400 thermal-sensors = <&tsens1 4>;
402 trips {
403 modemtx_alert0: trip-point@0 {
404 temperature = <90000>;
405 hysteresis = <2000>;
406 type = "hot";
407 };
408 };
409 };
410 };
412 timer {
413 compatible = "arm,armv8-timer";
414 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
415 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
416 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
417 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
418 };
420 clocks {
421 xo_board: xo_board {
422 compatible = "fixed-clock";
423 #clock-cells = <0>;
424 clock-frequency = <19200000>;
425 clock-output-names = "xo_board";
426 };
428 sleep_clk: sleep_clk {
429 compatible = "fixed-clock";
430 #clock-cells = <0>;
431 clock-frequency = <32764>;
432 clock-output-names = "sleep_clk";
433 };
434 };
436 psci {
437 compatible = "arm,psci-1.0";
438 method = "smc";
439 };
441 firmware {
442 scm {
443 compatible = "qcom,scm-msm8996";
445 qcom,dload-mode = <&tcsr 0x13000>;
446 };
447 };
449 tcsr_mutex: hwlock {
450 compatible = "qcom,tcsr-mutex";
451 syscon = <&tcsr_mutex_regs 0 0x1000>;
452 #hwlock-cells = <1>;
453 };
455 smem {
456 compatible = "qcom,smem";
457 memory-region = <&smem_mem>;
458 hwlocks = <&tcsr_mutex 3>;
459 };
461 rpm-glink {
462 compatible = "qcom,glink-rpm";
464 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
466 qcom,rpm-msg-ram = <&rpm_msg_ram>;
468 mboxes = <&apcs_glb 0>;
470 rpm_requests {
471 compatible = "qcom,rpm-msm8996";
472 qcom,glink-channels = "rpm_requests";
474 rpmcc: qcom,rpmcc {
475 compatible = "qcom,rpmcc-msm8996";
476 #clock-cells = <1>;
477 };
479 rpmpd: power-controller {
480 compatible = "qcom,msm8996-rpmpd";
481 #power-domain-cells = <1>;
482 operating-points-v2 = <&rpmpd_opp_table>;
484 rpmpd_opp_table: opp-table {
485 compatible = "operating-points-v2";
487 rpmpd_opp1: opp1 {
488 opp-level = <1>;
489 };
491 rpmpd_opp2: opp2 {
492 opp-level = <2>;
493 };
495 rpmpd_opp3: opp3 {
496 opp-level = <3>;
497 };
499 rpmpd_opp4: opp4 {
500 opp-level = <4>;
501 };
503 rpmpd_opp5: opp5 {
504 opp-level = <5>;
505 };
507 rpmpd_opp6: opp6 {
508 opp-level = <6>;
509 };
510 };
511 };
513 pm8994-regulators {
514 compatible = "qcom,rpm-pm8994-regulators";
516 pm8994_s1: s1 {};
517 pm8994_s2: s2 {};
518 pm8994_s3: s3 {};
519 pm8994_s4: s4 {};
520 pm8994_s5: s5 {};
521 pm8994_s6: s6 {};
522 pm8994_s7: s7 {};
523 pm8994_s8: s8 {};
524 pm8994_s9: s9 {};
525 pm8994_s10: s10 {};
526 pm8994_s11: s11 {};
527 pm8994_s12: s12 {};
529 pm8994_l1: l1 {};
530 pm8994_l2: l2 {};
531 pm8994_l3: l3 {};
532 pm8994_l4: l4 {};
533 pm8994_l5: l5 {};
534 pm8994_l6: l6 {};
535 pm8994_l7: l7 {};
536 pm8994_l8: l8 {};
537 pm8994_l9: l9 {};
538 pm8994_l10: l10 {};
539 pm8994_l11: l11 {};
540 pm8994_l12: l12 {};
541 pm8994_l13: l13 {};
542 pm8994_l14: l14 {};
543 pm8994_l15: l15 {};
544 pm8994_l16: l16 {};
545 pm8994_l17: l17 {};
546 pm8994_l18: l18 {};
547 pm8994_l19: l19 {};
548 pm8994_l20: l20 {};
549 pm8994_l21: l21 {};
550 pm8994_l22: l22 {};
551 pm8994_l23: l23 {};
552 pm8994_l24: l24 {};
553 pm8994_l25: l25 {};
554 pm8994_l26: l26 {};
555 pm8994_l27: l27 {};
556 pm8994_l28: l28 {};
557 pm8994_l29: l29 {};
558 pm8994_l30: l30 {};
559 pm8994_l31: l31 {};
560 pm8994_l32: l32 {};
561 };
563 };
564 };
566 soc: soc {
567 #address-cells = <1>;
568 #size-cells = <1>;
569 ranges = <0 0 0 0xffffffff>;
570 compatible = "simple-bus";
572 rpm_msg_ram: memory@68000 {
573 compatible = "qcom,rpm-msg-ram";
574 reg = <0x68000 0x6000>;
575 };
577 rng: rng@83000 {
578 compatible = "qcom,prng-ee";
579 reg = <0x00083000 0x1000>;
580 clocks = <&gcc GCC_PRNG_AHB_CLK>;
581 clock-names = "core";
582 };
584 tcsr_mutex_regs: syscon@740000 {
585 compatible = "syscon";
586 reg = <0x740000 0x20000>;
587 };
589 tsens0: thermal-sensor@4a9000 {
590 compatible = "qcom,msm8996-tsens";
591 reg = <0x4a9000 0x1000>, /* TM */
592 <0x4a8000 0x1000>; /* SROT */
593 #qcom,sensors = <13>;
594 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-names = "uplow";
596 #thermal-sensor-cells = <1>;
597 };
599 tsens1: thermal-sensor@4ad000 {
600 compatible = "qcom,msm8996-tsens";
601 reg = <0x4ad000 0x1000>, /* TM */
602 <0x4ac000 0x1000>; /* SROT */
603 #qcom,sensors = <8>;
604 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-names = "uplow";
606 #thermal-sensor-cells = <1>;
607 };
609 tcsr: syscon@7a0000 {
610 compatible = "qcom,tcsr-msm8996", "syscon";
611 reg = <0x7a0000 0x18000>;
612 };
614 intc: interrupt-controller@9bc0000 {
615 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
616 #interrupt-cells = <3>;
617 interrupt-controller;
618 #redistributor-regions = <1>;
619 redistributor-stride = <0x0 0x40000>;
620 reg = <0x09bc0000 0x10000>,
621 <0x09c00000 0x100000>;
622 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
623 };
625 apcs_glb: mailbox@9820000 {
626 compatible = "qcom,msm8996-apcs-hmss-global";
627 reg = <0x9820000 0x1000>;
629 #mbox-cells = <1>;
630 };
632 gcc: clock-controller@300000 {
633 compatible = "qcom,gcc-msm8996";
634 #clock-cells = <1>;
635 #reset-cells = <1>;
636 #power-domain-cells = <1>;
637 reg = <0x300000 0x90000>;
638 };
640 stm@3002000 {
641 compatible = "arm,coresight-stm", "arm,primecell";
642 reg = <0x3002000 0x1000>,
643 <0x8280000 0x180000>;
644 reg-names = "stm-base", "stm-stimulus-base";
646 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
647 clock-names = "apb_pclk", "atclk";
649 out-ports {
650 port {
651 stm_out: endpoint {
652 remote-endpoint =
653 <&funnel0_in>;
654 };
655 };
656 };
657 };
659 tpiu@3020000 {
660 compatible = "arm,coresight-tpiu", "arm,primecell";
661 reg = <0x3020000 0x1000>;
663 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
664 clock-names = "apb_pclk", "atclk";
666 in-ports {
667 port {
668 tpiu_in: endpoint {
669 remote-endpoint =
670 <&replicator_out1>;
671 };
672 };
673 };
674 };
676 funnel@3021000 {
677 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
678 reg = <0x3021000 0x1000>;
680 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
681 clock-names = "apb_pclk", "atclk";
683 in-ports {
684 #address-cells = <1>;
685 #size-cells = <0>;
687 port@7 {
688 reg = <7>;
689 funnel0_in: endpoint {
690 remote-endpoint =
691 <&stm_out>;
692 };
693 };
694 };
696 out-ports {
697 port {
698 funnel0_out: endpoint {
699 remote-endpoint =
700 <&merge_funnel_in0>;
701 };
702 };
703 };
704 };
706 funnel@3022000 {
707 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
708 reg = <0x3022000 0x1000>;
710 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
711 clock-names = "apb_pclk", "atclk";
713 in-ports {
714 #address-cells = <1>;
715 #size-cells = <0>;
717 port@6 {
718 reg = <6>;
719 funnel1_in: endpoint {
720 remote-endpoint =
721 <&apss_merge_funnel_out>;
722 };
723 };
724 };
726 out-ports {
727 port {
728 funnel1_out: endpoint {
729 remote-endpoint =
730 <&merge_funnel_in1>;
731 };
732 };
733 };
734 };
736 funnel@3023000 {
737 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
738 reg = <0x3023000 0x1000>;
740 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
741 clock-names = "apb_pclk", "atclk";
744 out-ports {
745 port {
746 funnel2_out: endpoint {
747 remote-endpoint =
748 <&merge_funnel_in2>;
749 };
750 };
751 };
752 };
754 funnel@3025000 {
755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
756 reg = <0x3025000 0x1000>;
758 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
759 clock-names = "apb_pclk", "atclk";
761 in-ports {
762 #address-cells = <1>;
763 #size-cells = <0>;
765 port@0 {
766 reg = <0>;
767 merge_funnel_in0: endpoint {
768 remote-endpoint =
769 <&funnel0_out>;
770 };
771 };
773 port@1 {
774 reg = <1>;
775 merge_funnel_in1: endpoint {
776 remote-endpoint =
777 <&funnel1_out>;
778 };
779 };
781 port@2 {
782 reg = <2>;
783 merge_funnel_in2: endpoint {
784 remote-endpoint =
785 <&funnel2_out>;
786 };
787 };
788 };
790 out-ports {
791 port {
792 merge_funnel_out: endpoint {
793 remote-endpoint =
794 <&etf_in>;
795 };
796 };
797 };
798 };
800 replicator@3026000 {
801 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
802 reg = <0x3026000 0x1000>;
804 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
805 clock-names = "apb_pclk", "atclk";
807 in-ports {
808 port {
809 replicator_in: endpoint {
810 remote-endpoint =
811 <&etf_out>;
812 };
813 };
814 };
816 out-ports {
817 #address-cells = <1>;
818 #size-cells = <0>;
820 port@0 {
821 reg = <0>;
822 replicator_out0: endpoint {
823 remote-endpoint =
824 <&etr_in>;
825 };
826 };
828 port@1 {
829 reg = <1>;
830 replicator_out1: endpoint {
831 remote-endpoint =
832 <&tpiu_in>;
833 };
834 };
835 };
836 };
838 etf@3027000 {
839 compatible = "arm,coresight-tmc", "arm,primecell";
840 reg = <0x3027000 0x1000>;
842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
843 clock-names = "apb_pclk", "atclk";
845 in-ports {
846 port {
847 etf_in: endpoint {
848 remote-endpoint =
849 <&merge_funnel_out>;
850 };
851 };
852 };
854 out-ports {
855 port {
856 etf_out: endpoint {
857 remote-endpoint =
858 <&replicator_in>;
859 };
860 };
861 };
862 };
864 etr@3028000 {
865 compatible = "arm,coresight-tmc", "arm,primecell";
866 reg = <0x3028000 0x1000>;
868 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
869 clock-names = "apb_pclk", "atclk";
870 arm,scatter-gather;
872 in-ports {
873 port {
874 etr_in: endpoint {
875 remote-endpoint =
876 <&replicator_out0>;
877 };
878 };
879 };
880 };
882 debug@3810000 {
883 compatible = "arm,coresight-cpu-debug", "arm,primecell";
884 reg = <0x3810000 0x1000>;
886 clocks = <&rpmcc RPM_QDSS_CLK>;
887 clock-names = "apb_pclk";
889 cpu = <&CPU0>;
890 };
892 etm@3840000 {
893 compatible = "arm,coresight-etm4x", "arm,primecell";
894 reg = <0x3840000 0x1000>;
896 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
897 clock-names = "apb_pclk", "atclk";
899 cpu = <&CPU0>;
901 out-ports {
902 port {
903 etm0_out: endpoint {
904 remote-endpoint =
905 <&apss_funnel0_in0>;
906 };
907 };
908 };
909 };
911 debug@3910000 {
912 compatible = "arm,coresight-cpu-debug", "arm,primecell";
913 reg = <0x3910000 0x1000>;
915 clocks = <&rpmcc RPM_QDSS_CLK>;
916 clock-names = "apb_pclk";
918 cpu = <&CPU1>;
919 };
921 etm@3940000 {
922 compatible = "arm,coresight-etm4x", "arm,primecell";
923 reg = <0x3940000 0x1000>;
925 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
926 clock-names = "apb_pclk", "atclk";
928 cpu = <&CPU1>;
930 out-ports {
931 port {
932 etm1_out: endpoint {
933 remote-endpoint =
934 <&apss_funnel0_in1>;
935 };
936 };
937 };
938 };
940 funnel@39b0000 { /* APSS Funnel 0 */
941 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
942 reg = <0x39b0000 0x1000>;
944 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
945 clock-names = "apb_pclk", "atclk";
947 in-ports {
948 #address-cells = <1>;
949 #size-cells = <0>;
951 port@0 {
952 reg = <0>;
953 apss_funnel0_in0: endpoint {
954 remote-endpoint = <&etm0_out>;
955 };
956 };
958 port@1 {
959 reg = <1>;
960 apss_funnel0_in1: endpoint {
961 remote-endpoint = <&etm1_out>;
962 };
963 };
964 };
966 out-ports {
967 port {
968 apss_funnel0_out: endpoint {
969 remote-endpoint =
970 <&apss_merge_funnel_in0>;
971 };
972 };
973 };
974 };
976 debug@3a10000 {
977 compatible = "arm,coresight-cpu-debug", "arm,primecell";
978 reg = <0x3a10000 0x1000>;
980 clocks = <&rpmcc RPM_QDSS_CLK>;
981 clock-names = "apb_pclk";
983 cpu = <&CPU2>;
984 };
986 etm@3a40000 {
987 compatible = "arm,coresight-etm4x", "arm,primecell";
988 reg = <0x3a40000 0x1000>;
990 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
991 clock-names = "apb_pclk", "atclk";
993 cpu = <&CPU2>;
995 out-ports {
996 port {
997 etm2_out: endpoint {
998 remote-endpoint =
999 <&apss_funnel1_in0>;
1000 };
1001 };
1002 };
1003 };
1005 debug@3b10000 {
1006 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1007 reg = <0x3b10000 0x1000>;
1009 clocks = <&rpmcc RPM_QDSS_CLK>;
1010 clock-names = "apb_pclk";
1012 cpu = <&CPU3>;
1013 };
1015 etm@3b40000 {
1016 compatible = "arm,coresight-etm4x", "arm,primecell";
1017 reg = <0x3b40000 0x1000>;
1019 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1020 clock-names = "apb_pclk", "atclk";
1022 cpu = <&CPU3>;
1024 out-ports {
1025 port {
1026 etm3_out: endpoint {
1027 remote-endpoint =
1028 <&apss_funnel1_in1>;
1029 };
1030 };
1031 };
1032 };
1034 funnel@3bb0000 { /* APSS Funnel 1 */
1035 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1036 reg = <0x3bb0000 0x1000>;
1038 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1039 clock-names = "apb_pclk", "atclk";
1041 in-ports {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1045 port@0 {
1046 reg = <0>;
1047 apss_funnel1_in0: endpoint {
1048 remote-endpoint = <&etm2_out>;
1049 };
1050 };
1052 port@1 {
1053 reg = <1>;
1054 apss_funnel1_in1: endpoint {
1055 remote-endpoint = <&etm3_out>;
1056 };
1057 };
1058 };
1060 out-ports {
1061 port {
1062 apss_funnel1_out: endpoint {
1063 remote-endpoint =
1064 <&apss_merge_funnel_in1>;
1065 };
1066 };
1067 };
1068 };
1070 funnel@3bc0000 {
1071 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1072 reg = <0x3bc0000 0x1000>;
1074 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1075 clock-names = "apb_pclk", "atclk";
1077 in-ports {
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1081 port@0 {
1082 reg = <0>;
1083 apss_merge_funnel_in0: endpoint {
1084 remote-endpoint =
1085 <&apss_funnel0_out>;
1086 };
1087 };
1089 port@1 {
1090 reg = <1>;
1091 apss_merge_funnel_in1: endpoint {
1092 remote-endpoint =
1093 <&apss_funnel1_out>;
1094 };
1095 };
1096 };
1098 out-ports {
1099 port {
1100 apss_merge_funnel_out: endpoint {
1101 remote-endpoint =
1102 <&funnel1_in>;
1103 };
1104 };
1105 };
1106 };
1108 kryocc: clock-controller@6400000 {
1109 compatible = "qcom,apcc-msm8996";
1110 reg = <0x6400000 0x90000>;
1111 #clock-cells = <1>;
1112 };
1114 blsp1_uart1: serial@7570000 {
1115 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1116 reg = <0x07570000 0x1000>;
1117 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1119 <&gcc GCC_BLSP1_AHB_CLK>;
1120 clock-names = "core", "iface";
1121 status = "disabled";
1122 };
1124 blsp1_spi0: spi@7575000 {
1125 compatible = "qcom,spi-qup-v2.2.1";
1126 reg = <0x07575000 0x600>;
1127 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1129 <&gcc GCC_BLSP1_AHB_CLK>;
1130 clock-names = "core", "iface";
1131 pinctrl-names = "default", "sleep";
1132 pinctrl-0 = <&blsp1_spi0_default>;
1133 pinctrl-1 = <&blsp1_spi0_sleep>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 status = "disabled";
1137 };
1139 blsp2_i2c0: i2c@75b5000 {
1140 compatible = "qcom,i2c-qup-v2.2.1";
1141 reg = <0x075b5000 0x1000>;
1142 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1144 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1145 clock-names = "iface", "core";
1146 pinctrl-names = "default", "sleep";
1147 pinctrl-0 = <&blsp2_i2c0_default>;
1148 pinctrl-1 = <&blsp2_i2c0_sleep>;
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 status = "disabled";
1152 };
1154 blsp2_uart1: serial@75b0000 {
1155 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1156 reg = <0x75b0000 0x1000>;
1157 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1159 <&gcc GCC_BLSP2_AHB_CLK>;
1160 clock-names = "core", "iface";
1161 status = "disabled";
1162 };
1164 blsp2_i2c1: i2c@75b6000 {
1165 compatible = "qcom,i2c-qup-v2.2.1";
1166 reg = <0x075b6000 0x1000>;
1167 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1169 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1170 clock-names = "iface", "core";
1171 pinctrl-names = "default", "sleep";
1172 pinctrl-0 = <&blsp2_i2c1_default>;
1173 pinctrl-1 = <&blsp2_i2c1_sleep>;
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 status = "disabled";
1177 };
1179 blsp2_uart2: serial@75b1000 {
1180 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1181 reg = <0x075b1000 0x1000>;
1182 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1184 <&gcc GCC_BLSP2_AHB_CLK>;
1185 clock-names = "core", "iface";
1186 status = "disabled";
1187 };
1189 blsp1_i2c2: i2c@7577000 {
1190 compatible = "qcom,i2c-qup-v2.2.1";
1191 reg = <0x07577000 0x1000>;
1192 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1194 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1195 clock-names = "iface", "core";
1196 pinctrl-names = "default", "sleep";
1197 pinctrl-0 = <&blsp1_i2c2_default>;
1198 pinctrl-1 = <&blsp1_i2c2_sleep>;
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 status = "disabled";
1202 };
1204 blsp2_spi5: spi@75ba000{
1205 compatible = "qcom,spi-qup-v2.2.1";
1206 reg = <0x075ba000 0x600>;
1207 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1209 <&gcc GCC_BLSP2_AHB_CLK>;
1210 clock-names = "core", "iface";
1211 pinctrl-names = "default", "sleep";
1212 pinctrl-0 = <&blsp2_spi5_default>;
1213 pinctrl-1 = <&blsp2_spi5_sleep>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 status = "disabled";
1217 };
1219 sdhc2: sdhci@74a4900 {
1220 status = "disabled";
1221 compatible = "qcom,sdhci-msm-v4";
1222 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
1223 reg-names = "hc_mem", "core_mem";
1225 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1226 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "hc_irq", "pwr_irq";
1229 clock-names = "iface", "core", "xo";
1230 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1231 <&gcc GCC_SDCC2_APPS_CLK>,
1232 <&xo_board>;
1233 bus-width = <4>;
1234 };
1236 msmgpio: pinctrl@1010000 {
1237 compatible = "qcom,msm8996-pinctrl";
1238 reg = <0x01010000 0x300000>;
1239 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1240 gpio-controller;
1241 #gpio-cells = <2>;
1242 interrupt-controller;
1243 #interrupt-cells = <2>;
1244 };
1246 timer@9840000 {
1247 #address-cells = <1>;
1248 #size-cells = <1>;
1249 ranges;
1250 compatible = "arm,armv7-timer-mem";
1251 reg = <0x09840000 0x1000>;
1252 clock-frequency = <19200000>;
1254 frame@9850000 {
1255 frame-number = <0>;
1256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1258 reg = <0x09850000 0x1000>,
1259 <0x09860000 0x1000>;
1260 };
1262 frame@9870000 {
1263 frame-number = <1>;
1264 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1265 reg = <0x09870000 0x1000>;
1266 status = "disabled";
1267 };
1269 frame@9880000 {
1270 frame-number = <2>;
1271 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1272 reg = <0x09880000 0x1000>;
1273 status = "disabled";
1274 };
1276 frame@9890000 {
1277 frame-number = <3>;
1278 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1279 reg = <0x09890000 0x1000>;
1280 status = "disabled";
1281 };
1283 frame@98a0000 {
1284 frame-number = <4>;
1285 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1286 reg = <0x098a0000 0x1000>;
1287 status = "disabled";
1288 };
1290 frame@98b0000 {
1291 frame-number = <5>;
1292 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1293 reg = <0x098b0000 0x1000>;
1294 status = "disabled";
1295 };
1297 frame@98c0000 {
1298 frame-number = <6>;
1299 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1300 reg = <0x098c0000 0x1000>;
1301 status = "disabled";
1302 };
1303 };
1305 spmi_bus: qcom,spmi@400f000 {
1306 compatible = "qcom,spmi-pmic-arb";
1307 reg = <0x400f000 0x1000>,
1308 <0x4400000 0x800000>,
1309 <0x4c00000 0x800000>,
1310 <0x5800000 0x200000>,
1311 <0x400a000 0x002100>;
1312 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1313 interrupt-names = "periph_irq";
1314 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1315 qcom,ee = <0>;
1316 qcom,channel = <0>;
1317 #address-cells = <2>;
1318 #size-cells = <0>;
1319 interrupt-controller;
1320 #interrupt-cells = <4>;
1321 };
1323 ufsphy: phy@627000 {
1324 compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
1325 reg = <0x627000 0xda8>;
1326 reg-names = "phy_mem";
1327 #phy-cells = <0>;
1329 vdda-phy-supply = <&pm8994_l28>;
1330 vdda-pll-supply = <&pm8994_l12>;
1332 vdda-phy-max-microamp = <18380>;
1333 vdda-pll-max-microamp = <9440>;
1335 vddp-ref-clk-supply = <&pm8994_l25>;
1336 vddp-ref-clk-max-microamp = <100>;
1337 vddp-ref-clk-always-on;
1339 clock-names = "ref_clk_src", "ref_clk";
1340 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
1341 <&gcc GCC_UFS_CLKREF_CLK>;
1342 resets = <&ufshc 0>;
1343 status = "disabled";
1344 };
1346 ufshc: ufshc@624000 {
1347 compatible = "qcom,ufshc";
1348 reg = <0x624000 0x2500>;
1349 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1351 phys = <&ufsphy>;
1352 phy-names = "ufsphy";
1354 vcc-supply = <&pm8994_l20>;
1355 vccq-supply = <&pm8994_l25>;
1356 vccq2-supply = <&pm8994_s4>;
1358 vcc-max-microamp = <600000>;
1359 vccq-max-microamp = <450000>;
1360 vccq2-max-microamp = <450000>;
1362 power-domains = <&gcc UFS_GDSC>;
1364 clock-names =
1365 "core_clk_src",
1366 "core_clk",
1367 "bus_clk",
1368 "bus_aggr_clk",
1369 "iface_clk",
1370 "core_clk_unipro_src",
1371 "core_clk_unipro",
1372 "core_clk_ice",
1373 "ref_clk",
1374 "tx_lane0_sync_clk",
1375 "rx_lane0_sync_clk";
1376 clocks =
1377 <&gcc UFS_AXI_CLK_SRC>,
1378 <&gcc GCC_UFS_AXI_CLK>,
1379 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1380 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1381 <&gcc GCC_UFS_AHB_CLK>,
1382 <&gcc UFS_ICE_CORE_CLK_SRC>,
1383 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1384 <&gcc GCC_UFS_ICE_CORE_CLK>,
1385 <&rpmcc RPM_SMD_LN_BB_CLK>,
1386 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1387 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1388 freq-table-hz =
1389 <100000000 200000000>,
1390 <0 0>,
1391 <0 0>,
1392 <0 0>,
1393 <0 0>,
1394 <150000000 300000000>,
1395 <0 0>,
1396 <0 0>,
1397 <0 0>,
1398 <0 0>,
1399 <0 0>;
1401 lanes-per-direction = <1>;
1402 #reset-cells = <1>;
1403 status = "disabled";
1405 ufs_variant {
1406 compatible = "qcom,ufs_variant";
1407 };
1408 };
1410 mmcc: clock-controller@8c0000 {
1411 compatible = "qcom,mmcc-msm8996";
1412 #clock-cells = <1>;
1413 #reset-cells = <1>;
1414 #power-domain-cells = <1>;
1415 reg = <0x8c0000 0x40000>;
1416 assigned-clocks = <&mmcc MMPLL9_PLL>,
1417 <&mmcc MMPLL1_PLL>,
1418 <&mmcc MMPLL3_PLL>,
1419 <&mmcc MMPLL4_PLL>,
1420 <&mmcc MMPLL5_PLL>;
1421 assigned-clock-rates = <624000000>,
1422 <810000000>,
1423 <980000000>,
1424 <960000000>,
1425 <825000000>;
1426 };
1428 qfprom@74000 {
1429 compatible = "qcom,qfprom";
1430 reg = <0x74000 0x8ff>;
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1434 qusb2p_hstx_trim: hstx_trim@24e {
1435 reg = <0x24e 0x2>;
1436 bits = <5 4>;
1437 };
1439 qusb2s_hstx_trim: hstx_trim@24f {
1440 reg = <0x24f 0x1>;
1441 bits = <1 4>;
1442 };
1444 gpu_speed_bin: gpu_speed_bin@133 {
1445 reg = <0x133 0x1>;
1446 bits = <5 3>;
1447 };
1448 };
1450 phy@34000 {
1451 compatible = "qcom,msm8996-qmp-pcie-phy";
1452 reg = <0x34000 0x488>;
1453 #clock-cells = <1>;
1454 #address-cells = <1>;
1455 #size-cells = <1>;
1456 ranges;
1458 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1459 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
1460 <&gcc GCC_PCIE_CLKREF_CLK>;
1461 clock-names = "aux", "cfg_ahb", "ref";
1463 vdda-phy-supply = <&pm8994_l28>;
1464 vdda-pll-supply = <&pm8994_l12>;
1466 resets = <&gcc GCC_PCIE_PHY_BCR>,
1467 <&gcc GCC_PCIE_PHY_COM_BCR>,
1468 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
1469 reset-names = "phy", "common", "cfg";
1470 status = "disabled";
1472 pciephy_0: lane@35000 {
1473 reg = <0x035000 0x130>,
1474 <0x035200 0x200>,
1475 <0x035400 0x1dc>;
1476 #phy-cells = <0>;
1478 clock-output-names = "pcie_0_pipe_clk_src";
1479 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1480 clock-names = "pipe0";
1481 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1482 reset-names = "lane0";
1483 };
1485 pciephy_1: lane@36000 {
1486 reg = <0x036000 0x130>,
1487 <0x036200 0x200>,
1488 <0x036400 0x1dc>;
1489 #phy-cells = <0>;
1491 clock-output-names = "pcie_1_pipe_clk_src";
1492 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1493 clock-names = "pipe1";
1494 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1495 reset-names = "lane1";
1496 };
1498 pciephy_2: lane@37000 {
1499 reg = <0x037000 0x130>,
1500 <0x037200 0x200>,
1501 <0x037400 0x1dc>;
1502 #phy-cells = <0>;
1504 clock-output-names = "pcie_2_pipe_clk_src";
1505 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1506 clock-names = "pipe2";
1507 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1508 reset-names = "lane2";
1509 };
1510 };
1512 phy@7410000 {
1513 compatible = "qcom,msm8996-qmp-usb3-phy";
1514 reg = <0x7410000 0x1c4>;
1515 #clock-cells = <1>;
1516 #address-cells = <1>;
1517 #size-cells = <1>;
1518 ranges;
1520 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1521 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1522 <&gcc GCC_USB3_CLKREF_CLK>;
1523 clock-names = "aux", "cfg_ahb", "ref";
1525 vdda-phy-supply = <&pm8994_l28>;
1526 vdda-pll-supply = <&pm8994_l12>;
1528 resets = <&gcc GCC_USB3_PHY_BCR>,
1529 <&gcc GCC_USB3PHY_PHY_BCR>;
1530 reset-names = "phy", "common";
1531 status = "disabled";
1533 ssusb_phy_0: lane@7410200 {
1534 reg = <0x7410200 0x200>,
1535 <0x7410400 0x130>,
1536 <0x7410600 0x1a8>;
1537 #phy-cells = <0>;
1539 clock-output-names = "usb3_phy_pipe_clk_src";
1540 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1541 clock-names = "pipe0";
1542 };
1543 };
1545 hsusb_phy1: phy@7411000 {
1546 compatible = "qcom,msm8996-qusb2-phy";
1547 reg = <0x7411000 0x180>;
1548 #phy-cells = <0>;
1550 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1551 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1552 clock-names = "cfg_ahb", "ref";
1554 vdda-pll-supply = <&pm8994_l12>;
1555 vdda-phy-dpdm-supply = <&pm8994_l24>;
1557 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1558 nvmem-cells = <&qusb2p_hstx_trim>;
1559 status = "disabled";
1560 };
1562 hsusb_phy2: phy@7412000 {
1563 compatible = "qcom,msm8996-qusb2-phy";
1564 reg = <0x7412000 0x180>;
1565 #phy-cells = <0>;
1567 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1568 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1569 clock-names = "cfg_ahb", "ref";
1571 vdda-pll-supply = <&pm8994_l12>;
1572 vdda-phy-dpdm-supply = <&pm8994_l24>;
1574 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1575 nvmem-cells = <&qusb2s_hstx_trim>;
1576 status = "disabled";
1577 };
1579 usb2: usb@76f8800 {
1580 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1581 reg = <0x76f8800 0x400>;
1582 #address-cells = <1>;
1583 #size-cells = <1>;
1584 ranges;
1586 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1587 <&gcc GCC_USB20_MASTER_CLK>,
1588 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1589 <&gcc GCC_USB20_SLEEP_CLK>,
1590 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1592 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1593 <&gcc GCC_USB20_MASTER_CLK>;
1594 assigned-clock-rates = <19200000>, <60000000>;
1596 power-domains = <&gcc USB30_GDSC>;
1597 status = "disabled";
1599 dwc3@7600000 {
1600 compatible = "snps,dwc3";
1601 reg = <0x7600000 0xcc00>;
1602 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1603 phys = <&hsusb_phy2>;
1604 phy-names = "usb2-phy";
1605 };
1606 };
1608 usb3: usb@6af8800 {
1609 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1610 reg = <0x6af8800 0x400>;
1611 #address-cells = <1>;
1612 #size-cells = <1>;
1613 ranges;
1615 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1616 <&gcc GCC_USB30_MASTER_CLK>,
1617 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1618 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1619 <&gcc GCC_USB30_SLEEP_CLK>,
1620 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1622 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1623 <&gcc GCC_USB30_MASTER_CLK>;
1624 assigned-clock-rates = <19200000>, <120000000>;
1626 power-domains = <&gcc USB30_GDSC>;
1627 status = "disabled";
1629 dwc3@6a00000 {
1630 compatible = "snps,dwc3";
1631 reg = <0x6a00000 0xcc00>;
1632 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1633 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1634 phy-names = "usb2-phy", "usb3-phy";
1635 };
1636 };
1638 vfe_smmu: iommu@da0000 {
1639 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1640 reg = <0xda0000 0x10000>;
1642 #global-interrupts = <1>;
1643 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1646 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1647 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1648 <&mmcc SMMU_VFE_AXI_CLK>;
1649 clock-names = "iface",
1650 "bus";
1651 #iommu-cells = <1>;
1652 };
1654 camss: camss@a00000 {
1655 compatible = "qcom,msm8996-camss";
1656 reg = <0xa34000 0x1000>,
1657 <0xa00030 0x4>,
1658 <0xa35000 0x1000>,
1659 <0xa00038 0x4>,
1660 <0xa36000 0x1000>,
1661 <0xa00040 0x4>,
1662 <0xa30000 0x100>,
1663 <0xa30400 0x100>,
1664 <0xa30800 0x100>,
1665 <0xa30c00 0x100>,
1666 <0xa31000 0x500>,
1667 <0xa00020 0x10>,
1668 <0xa10000 0x1000>,
1669 <0xa14000 0x1000>;
1670 reg-names = "csiphy0",
1671 "csiphy0_clk_mux",
1672 "csiphy1",
1673 "csiphy1_clk_mux",
1674 "csiphy2",
1675 "csiphy2_clk_mux",
1676 "csid0",
1677 "csid1",
1678 "csid2",
1679 "csid3",
1680 "ispif",
1681 "csi_clk_mux",
1682 "vfe0",
1683 "vfe1";
1684 interrupts = <GIC_SPI 78 0>,
1685 <GIC_SPI 79 0>,
1686 <GIC_SPI 80 0>,
1687 <GIC_SPI 296 0>,
1688 <GIC_SPI 297 0>,
1689 <GIC_SPI 298 0>,
1690 <GIC_SPI 299 0>,
1691 <GIC_SPI 309 0>,
1692 <GIC_SPI 314 0>,
1693 <GIC_SPI 315 0>;
1694 interrupt-names = "csiphy0",
1695 "csiphy1",
1696 "csiphy2",
1697 "csid0",
1698 "csid1",
1699 "csid2",
1700 "csid3",
1701 "ispif",
1702 "vfe0",
1703 "vfe1";
1704 power-domains = <&mmcc VFE0_GDSC>;
1705 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1706 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1707 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1708 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1709 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1710 <&mmcc CAMSS_CSI0_AHB_CLK>,
1711 <&mmcc CAMSS_CSI0_CLK>,
1712 <&mmcc CAMSS_CSI0PHY_CLK>,
1713 <&mmcc CAMSS_CSI0PIX_CLK>,
1714 <&mmcc CAMSS_CSI0RDI_CLK>,
1715 <&mmcc CAMSS_CSI1_AHB_CLK>,
1716 <&mmcc CAMSS_CSI1_CLK>,
1717 <&mmcc CAMSS_CSI1PHY_CLK>,
1718 <&mmcc CAMSS_CSI1PIX_CLK>,
1719 <&mmcc CAMSS_CSI1RDI_CLK>,
1720 <&mmcc CAMSS_CSI2_AHB_CLK>,
1721 <&mmcc CAMSS_CSI2_CLK>,
1722 <&mmcc CAMSS_CSI2PHY_CLK>,
1723 <&mmcc CAMSS_CSI2PIX_CLK>,
1724 <&mmcc CAMSS_CSI2RDI_CLK>,
1725 <&mmcc CAMSS_CSI3_AHB_CLK>,
1726 <&mmcc CAMSS_CSI3_CLK>,
1727 <&mmcc CAMSS_CSI3PHY_CLK>,
1728 <&mmcc CAMSS_CSI3PIX_CLK>,
1729 <&mmcc CAMSS_CSI3RDI_CLK>,
1730 <&mmcc CAMSS_AHB_CLK>,
1731 <&mmcc CAMSS_VFE0_CLK>,
1732 <&mmcc CAMSS_CSI_VFE0_CLK>,
1733 <&mmcc CAMSS_VFE0_AHB_CLK>,
1734 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1735 <&mmcc CAMSS_VFE1_CLK>,
1736 <&mmcc CAMSS_CSI_VFE1_CLK>,
1737 <&mmcc CAMSS_VFE1_AHB_CLK>,
1738 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1739 <&mmcc CAMSS_VFE_AHB_CLK>,
1740 <&mmcc CAMSS_VFE_AXI_CLK>;
1741 clock-names = "top_ahb",
1742 "ispif_ahb",
1743 "csiphy0_timer",
1744 "csiphy1_timer",
1745 "csiphy2_timer",
1746 "csi0_ahb",
1747 "csi0",
1748 "csi0_phy",
1749 "csi0_pix",
1750 "csi0_rdi",
1751 "csi1_ahb",
1752 "csi1",
1753 "csi1_phy",
1754 "csi1_pix",
1755 "csi1_rdi",
1756 "csi2_ahb",
1757 "csi2",
1758 "csi2_phy",
1759 "csi2_pix",
1760 "csi2_rdi",
1761 "csi3_ahb",
1762 "csi3",
1763 "csi3_phy",
1764 "csi3_pix",
1765 "csi3_rdi",
1766 "ahb",
1767 "vfe0",
1768 "csi_vfe0",
1769 "vfe0_ahb",
1770 "vfe0_stream",
1771 "vfe1",
1772 "csi_vfe1",
1773 "vfe1_ahb",
1774 "vfe1_stream",
1775 "vfe_ahb",
1776 "vfe_axi";
1777 vdda-supply = <&pm8994_l2>;
1778 iommus = <&vfe_smmu 0>,
1779 <&vfe_smmu 1>,
1780 <&vfe_smmu 2>,
1781 <&vfe_smmu 3>;
1782 status = "disabled";
1783 ports {
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1786 };
1787 };
1789 adreno_smmu: iommu@b40000 {
1790 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1791 reg = <0xb40000 0x10000>;
1793 #global-interrupts = <1>;
1794 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1797 #iommu-cells = <1>;
1799 clocks = <&mmcc GPU_AHB_CLK>,
1800 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1801 clock-names = "iface", "bus";
1803 power-domains = <&mmcc GPU_GDSC>;
1804 };
1806 mdp_smmu: iommu@d00000 {
1807 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1808 reg = <0xd00000 0x10000>;
1810 #global-interrupts = <1>;
1811 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1814 #iommu-cells = <1>;
1815 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1816 <&mmcc SMMU_MDP_AXI_CLK>;
1817 clock-names = "iface", "bus";
1819 power-domains = <&mmcc MDSS_GDSC>;
1820 };
1822 lpass_q6_smmu: iommu@1600000 {
1823 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1824 reg = <0x1600000 0x20000>;
1825 #iommu-cells = <1>;
1826 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1828 #global-interrupts = <1>;
1829 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1843 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1844 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1845 clock-names = "iface", "bus";
1846 };
1848 agnoc@0 {
1849 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1850 compatible = "simple-pm-bus";
1851 #address-cells = <1>;
1852 #size-cells = <1>;
1853 ranges;
1855 pcie0: pcie@600000 {
1856 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1857 status = "disabled";
1858 power-domains = <&gcc PCIE0_GDSC>;
1859 bus-range = <0x00 0xff>;
1860 num-lanes = <1>;
1862 reg = <0x00600000 0x2000>,
1863 <0x0c000000 0xf1d>,
1864 <0x0c000f20 0xa8>,
1865 <0x0c100000 0x100000>;
1866 reg-names = "parf", "dbi", "elbi","config";
1868 phys = <&pciephy_0>;
1869 phy-names = "pciephy";
1871 #address-cells = <3>;
1872 #size-cells = <2>;
1873 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1874 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1876 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1877 interrupt-names = "msi";
1878 #interrupt-cells = <1>;
1879 interrupt-map-mask = <0 0 0 0x7>;
1880 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1881 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1882 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1883 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1885 pinctrl-names = "default", "sleep";
1886 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1887 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1890 vdda-supply = <&pm8994_l28>;
1892 linux,pci-domain = <0>;
1894 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1895 <&gcc GCC_PCIE_0_AUX_CLK>,
1896 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1897 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1898 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1900 clock-names = "pipe",
1901 "aux",
1902 "cfg",
1903 "bus_master",
1904 "bus_slave";
1906 };
1908 pcie1: pcie@608000 {
1909 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1910 power-domains = <&gcc PCIE1_GDSC>;
1911 bus-range = <0x00 0xff>;
1912 num-lanes = <1>;
1914 status = "disabled";
1916 reg = <0x00608000 0x2000>,
1917 <0x0d000000 0xf1d>,
1918 <0x0d000f20 0xa8>,
1919 <0x0d100000 0x100000>;
1921 reg-names = "parf", "dbi", "elbi","config";
1923 phys = <&pciephy_1>;
1924 phy-names = "pciephy";
1926 #address-cells = <3>;
1927 #size-cells = <2>;
1928 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1929 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1931 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1932 interrupt-names = "msi";
1933 #interrupt-cells = <1>;
1934 interrupt-map-mask = <0 0 0 0x7>;
1935 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1936 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1937 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1938 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1940 pinctrl-names = "default", "sleep";
1941 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1942 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1945 vdda-supply = <&pm8994_l28>;
1946 linux,pci-domain = <1>;
1948 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1949 <&gcc GCC_PCIE_1_AUX_CLK>,
1950 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1951 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1952 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1954 clock-names = "pipe",
1955 "aux",
1956 "cfg",
1957 "bus_master",
1958 "bus_slave";
1959 };
1961 pcie2: pcie@610000 {
1962 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1963 power-domains = <&gcc PCIE2_GDSC>;
1964 bus-range = <0x00 0xff>;
1965 num-lanes = <1>;
1966 status = "disabled";
1967 reg = <0x00610000 0x2000>,
1968 <0x0e000000 0xf1d>,
1969 <0x0e000f20 0xa8>,
1970 <0x0e100000 0x100000>;
1972 reg-names = "parf", "dbi", "elbi","config";
1974 phys = <&pciephy_2>;
1975 phy-names = "pciephy";
1977 #address-cells = <3>;
1978 #size-cells = <2>;
1979 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1980 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1982 device_type = "pci";
1984 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "msi";
1986 #interrupt-cells = <1>;
1987 interrupt-map-mask = <0 0 0 0x7>;
1988 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1989 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1990 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1991 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1993 pinctrl-names = "default", "sleep";
1994 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1995 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1997 vdda-supply = <&pm8994_l28>;
1999 linux,pci-domain = <2>;
2000 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2001 <&gcc GCC_PCIE_2_AUX_CLK>,
2002 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2003 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2004 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2006 clock-names = "pipe",
2007 "aux",
2008 "cfg",
2009 "bus_master",
2010 "bus_slave";
2011 };
2012 };
2014 slimbam:dma@9184000
2015 {
2016 compatible = "qcom,bam-v1.7.0";
2017 qcom,controlled-remotely;
2018 reg = <0x9184000 0x32000>;
2019 num-channels = <31>;
2020 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2021 #dma-cells = <1>;
2022 qcom,ee = <1>;
2023 qcom,num-ees = <2>;
2024 };
2026 slim_msm: slim@91c0000 {
2027 compatible = "qcom,slim-ngd-v1.5.0";
2028 reg = <0x91c0000 0x2C000>;
2029 reg-names = "ctrl";
2030 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2031 dmas = <&slimbam 3>, <&slimbam 4>,
2032 <&slimbam 5>, <&slimbam 6>;
2033 dma-names = "rx", "tx", "tx2", "rx2";
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036 ngd@1 {
2037 reg = <1>;
2038 #address-cells = <1>;
2039 #size-cells = <1>;
2041 tasha_ifd: tas-ifd {
2042 compatible = "slim217,1a0";
2043 reg = <0 0>;
2044 };
2046 wcd9335: codec@1{
2047 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2048 pinctrl-names = "default";
2050 compatible = "slim217,1a0";
2051 reg = <1 0>;
2053 interrupt-parent = <&msmgpio>;
2054 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2055 <53 IRQ_TYPE_LEVEL_HIGH>;
2056 interrupt-names = "intr1", "intr2";
2057 interrupt-controller;
2058 #interrupt-cells = <1>;
2059 reset-gpios = <&msmgpio 64 0>;
2061 slim-ifc-dev = <&tasha_ifd>;
2063 vdd-buck-supply = <&pm8994_s4>;
2064 vdd-buck-sido-supply = <&pm8994_s4>;
2065 vdd-tx-supply = <&pm8994_s4>;
2066 vdd-rx-supply = <&pm8994_s4>;
2067 vdd-io-supply = <&pm8994_s4>;
2069 #sound-dai-cells = <1>;
2070 };
2071 };
2072 };
2074 gpu@b00000 {
2075 compatible = "qcom,adreno-530.2", "qcom,adreno";
2076 #stream-id-cells = <16>;
2078 reg = <0xb00000 0x3f000>;
2079 reg-names = "kgsl_3d0_reg_memory";
2081 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
2083 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
2084 <&mmcc GPU_AHB_CLK>,
2085 <&mmcc GPU_GX_RBBMTIMER_CLK>,
2086 <&gcc GCC_BIMC_GFX_CLK>,
2087 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2089 clock-names = "core",
2090 "iface",
2091 "rbbmtimer",
2092 "mem",
2093 "mem_iface";
2095 power-domains = <&mmcc GPU_GDSC>;
2096 iommus = <&adreno_smmu 0>;
2098 nvmem-cells = <&gpu_speed_bin>;
2099 nvmem-cell-names = "speed_bin";
2101 qcom,gpu-quirk-two-pass-use-wfi;
2102 qcom,gpu-quirk-fault-detect-mask;
2104 operating-points-v2 = <&gpu_opp_table>;
2106 gpu_opp_table: opp-table {
2107 compatible ="operating-points-v2";
2109 /*
2110 * 624Mhz and 560Mhz are only available on speed
2111 * bin (1 << 0). All the rest are available on
2112 * all bins of the hardware
2113 */
2114 opp-624000000 {
2115 opp-hz = /bits/ 64 <624000000>;
2116 opp-supported-hw = <0x01>;
2117 };
2118 opp-560000000 {
2119 opp-hz = /bits/ 64 <560000000>;
2120 opp-supported-hw = <0x01>;
2121 };
2122 opp-510000000 {
2123 opp-hz = /bits/ 64 <510000000>;
2124 opp-supported-hw = <0xFF>;
2125 };
2126 opp-401800000 {
2127 opp-hz = /bits/ 64 <401800000>;
2128 opp-supported-hw = <0xFF>;
2129 };
2130 opp-315000000 {
2131 opp-hz = /bits/ 64 <315000000>;
2132 opp-supported-hw = <0xFF>;
2133 };
2134 opp-214000000 {
2135 opp-hz = /bits/ 64 <214000000>;
2136 opp-supported-hw = <0xFF>;
2137 };
2138 opp-133000000 {
2139 opp-hz = /bits/ 64 <133000000>;
2140 opp-supported-hw = <0xFF>;
2141 };
2142 };
2144 zap-shader {
2145 memory-region = <&zap_shader_region>;
2146 };
2147 };
2149 mdss: mdss@900000 {
2150 compatible = "qcom,mdss";
2152 reg = <0x900000 0x1000>,
2153 <0x9b0000 0x1040>,
2154 <0x9b8000 0x1040>;
2155 reg-names = "mdss_phys",
2156 "vbif_phys",
2157 "vbif_nrt_phys";
2159 power-domains = <&mmcc MDSS_GDSC>;
2160 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2162 interrupt-controller;
2163 #interrupt-cells = <1>;
2165 clocks = <&mmcc MDSS_AHB_CLK>;
2166 clock-names = "iface";
2168 #address-cells = <1>;
2169 #size-cells = <1>;
2170 ranges;
2172 mdp: mdp@901000 {
2173 compatible = "qcom,mdp5";
2174 reg = <0x901000 0x90000>;
2175 reg-names = "mdp_phys";
2177 interrupt-parent = <&mdss>;
2178 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2180 clocks = <&mmcc MDSS_AHB_CLK>,
2181 <&mmcc MDSS_AXI_CLK>,
2182 <&mmcc MDSS_MDP_CLK>,
2183 <&mmcc SMMU_MDP_AXI_CLK>,
2184 <&mmcc MDSS_VSYNC_CLK>;
2185 clock-names = "iface",
2186 "bus",
2187 "core",
2188 "iommu",
2189 "vsync";
2191 iommus = <&mdp_smmu 0>;
2193 ports {
2194 #address-cells = <1>;
2195 #size-cells = <0>;
2197 port@0 {
2198 reg = <0>;
2199 mdp5_intf3_out: endpoint {
2200 remote-endpoint = <&hdmi_in>;
2201 };
2202 };
2203 };
2204 };
2206 hdmi: hdmi-tx@9a0000 {
2207 compatible = "qcom,hdmi-tx-8996";
2208 reg = <0x009a0000 0x50c>,
2209 <0x00070000 0x6158>,
2210 <0x009e0000 0xfff>;
2211 reg-names = "core_physical",
2212 "qfprom_physical",
2213 "hdcp_physical";
2215 interrupt-parent = <&mdss>;
2216 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
2218 clocks = <&mmcc MDSS_MDP_CLK>,
2219 <&mmcc MDSS_AHB_CLK>,
2220 <&mmcc MDSS_HDMI_CLK>,
2221 <&mmcc MDSS_HDMI_AHB_CLK>,
2222 <&mmcc MDSS_EXTPCLK_CLK>;
2223 clock-names =
2224 "mdp_core",
2225 "iface",
2226 "core",
2227 "alt_iface",
2228 "extp";
2230 phys = <&hdmi_phy>;
2231 phy-names = "hdmi_phy";
2232 #sound-dai-cells = <1>;
2234 ports {
2235 #address-cells = <1>;
2236 #size-cells = <0>;
2238 port@0 {
2239 reg = <0>;
2240 hdmi_in: endpoint {
2241 remote-endpoint = <&mdp5_intf3_out>;
2242 };
2243 };
2244 };
2245 };
2247 hdmi_phy: hdmi-phy@9a0600 {
2248 #phy-cells = <0>;
2249 compatible = "qcom,hdmi-phy-8996";
2250 reg = <0x9a0600 0x1c4>,
2251 <0x9a0a00 0x124>,
2252 <0x9a0c00 0x124>,
2253 <0x9a0e00 0x124>,
2254 <0x9a1000 0x124>,
2255 <0x9a1200 0x0c8>;
2256 reg-names = "hdmi_pll",
2257 "hdmi_tx_l0",
2258 "hdmi_tx_l1",
2259 "hdmi_tx_l2",
2260 "hdmi_tx_l3",
2261 "hdmi_phy";
2263 clocks = <&mmcc MDSS_AHB_CLK>,
2264 <&gcc GCC_HDMI_CLKREF_CLK>;
2265 clock-names = "iface",
2266 "ref";
2267 };
2268 };
2270 venus_smmu: arm,smmu-venus@d40000 {
2271 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2272 reg = <0xd40000 0x20000>;
2273 #global-interrupts = <1>;
2274 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2275 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2276 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2277 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2278 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2279 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2280 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2281 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2282 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2283 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2284 <&mmcc SMMU_VIDEO_AXI_CLK>;
2285 clock-names = "iface", "bus";
2286 #iommu-cells = <1>;
2287 status = "okay";
2288 };
2290 video-codec@c00000 {
2291 compatible = "qcom,msm8996-venus";
2292 reg = <0x00c00000 0xff000>;
2293 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2294 power-domains = <&mmcc VENUS_GDSC>;
2295 clocks = <&mmcc VIDEO_CORE_CLK>,
2296 <&mmcc VIDEO_AHB_CLK>,
2297 <&mmcc VIDEO_AXI_CLK>,
2298 <&mmcc VIDEO_MAXI_CLK>;
2299 clock-names = "core", "iface", "bus", "mbus";
2300 iommus = <&venus_smmu 0x00>,
2301 <&venus_smmu 0x01>,
2302 <&venus_smmu 0x0a>,
2303 <&venus_smmu 0x07>,
2304 <&venus_smmu 0x0e>,
2305 <&venus_smmu 0x0f>,
2306 <&venus_smmu 0x08>,
2307 <&venus_smmu 0x09>,
2308 <&venus_smmu 0x0b>,
2309 <&venus_smmu 0x0c>,
2310 <&venus_smmu 0x0d>,
2311 <&venus_smmu 0x10>,
2312 <&venus_smmu 0x11>,
2313 <&venus_smmu 0x21>,
2314 <&venus_smmu 0x28>,
2315 <&venus_smmu 0x29>,
2316 <&venus_smmu 0x2b>,
2317 <&venus_smmu 0x2c>,
2318 <&venus_smmu 0x2d>,
2319 <&venus_smmu 0x31>;
2320 memory-region = <&venus_region>;
2321 status = "okay";
2323 video-decoder {
2324 compatible = "venus-decoder";
2325 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2326 clock-names = "core";
2327 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2328 };
2330 video-encoder {
2331 compatible = "venus-encoder";
2332 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2333 clock-names = "core";
2334 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2335 };
2336 };
2337 };
2339 sound: sound {
2340 };
2342 adsp-pil {
2343 compatible = "qcom,msm8996-adsp-pil";
2345 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2346 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2347 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2348 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2349 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2350 interrupt-names = "wdog", "fatal", "ready",
2351 "handover", "stop-ack";
2353 clocks = <&xo_board>;
2354 clock-names = "xo";
2356 memory-region = <&adsp_region>;
2358 qcom,smem-states = <&adsp_smp2p_out 0>;
2359 qcom,smem-state-names = "stop";
2361 smd-edge {
2362 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2364 label = "lpass";
2365 mboxes = <&apcs_glb 8>;
2366 qcom,smd-edge = <1>;
2367 qcom,remote-pid = <2>;
2368 #address-cells = <1>;
2369 #size-cells = <0>;
2370 apr {
2371 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2372 compatible = "qcom,apr-v2";
2373 qcom,smd-channels = "apr_audio_svc";
2374 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2375 #address-cells = <1>;
2376 #size-cells = <0>;
2378 q6core {
2379 reg = <APR_SVC_ADSP_CORE>;
2380 compatible = "qcom,q6core";
2381 };
2383 q6afe: q6afe {
2384 compatible = "qcom,q6afe";
2385 reg = <APR_SVC_AFE>;
2386 q6afedai: dais {
2387 compatible = "qcom,q6afe-dais";
2388 #address-cells = <1>;
2389 #size-cells = <0>;
2390 #sound-dai-cells = <1>;
2391 hdmi@1 {
2392 reg = <1>;
2393 };
2394 };
2395 };
2397 q6asm: q6asm {
2398 compatible = "qcom,q6asm";
2399 reg = <APR_SVC_ASM>;
2400 q6asmdai: dais {
2401 compatible = "qcom,q6asm-dais";
2402 #sound-dai-cells = <1>;
2403 iommus = <&lpass_q6_smmu 1>;
2404 };
2405 };
2407 q6adm: q6adm {
2408 compatible = "qcom,q6adm";
2409 reg = <APR_SVC_ADM>;
2410 q6routing: routing {
2411 compatible = "qcom,q6adm-routing";
2412 #sound-dai-cells = <0>;
2413 };
2414 };
2415 };
2417 };
2418 };
2420 adsp-smp2p {
2421 compatible = "qcom,smp2p";
2422 qcom,smem = <443>, <429>;
2424 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
2426 mboxes = <&apcs_glb 10>;
2428 qcom,local-pid = <0>;
2429 qcom,remote-pid = <2>;
2431 adsp_smp2p_out: master-kernel {
2432 qcom,entry-name = "master-kernel";
2433 #qcom,smem-state-cells = <1>;
2434 };
2436 adsp_smp2p_in: slave-kernel {
2437 qcom,entry-name = "slave-kernel";
2439 interrupt-controller;
2440 #interrupt-cells = <2>;
2441 };
2442 };
2444 modem-smp2p {
2445 compatible = "qcom,smp2p";
2446 qcom,smem = <435>, <428>;
2448 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
2450 mboxes = <&apcs_glb 14>;
2452 qcom,local-pid = <0>;
2453 qcom,remote-pid = <1>;
2455 modem_smp2p_out: master-kernel {
2456 qcom,entry-name = "master-kernel";
2457 #qcom,smem-state-cells = <1>;
2458 };
2460 modem_smp2p_in: slave-kernel {
2461 qcom,entry-name = "slave-kernel";
2463 interrupt-controller;
2464 #interrupt-cells = <2>;
2465 };
2466 };
2468 smp2p-slpi {
2469 compatible = "qcom,smp2p";
2470 qcom,smem = <481>, <430>;
2472 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
2474 mboxes = <&apcs_glb 26>;
2476 qcom,local-pid = <0>;
2477 qcom,remote-pid = <3>;
2479 slpi_smp2p_in: slave-kernel {
2480 qcom,entry-name = "slave-kernel";
2481 interrupt-controller;
2482 #interrupt-cells = <2>;
2483 };
2485 slpi_smp2p_out: master-kernel {
2486 qcom,entry-name = "master-kernel";
2487 #qcom,smem-state-cells = <1>;
2488 };
2489 };
2491 };
2492 #include "msm8996-pins.dtsi"