arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         model = "ZynqMP ZCU104 RevA";
  18         compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  19
  20         aliases {
  21                 ethernet0 = &gem3;
  22                 i2c0 = &i2c1;
  23                 mmc0 = &sdhci1;
  24                 rtc0 = &rtc;
  25                 serial0 = &uart0;
  26                 serial1 = &uart1;
  27                 serial2 = &dcc;
  28         };
  29
  30         chosen {
  31                 bootargs = "earlycon";
  32                 stdout-path = "serial0:115200n8";
  33         };
  34
  35         memory@0 {
  36                 device_type = "memory";
  37                 reg = <0x0 0x0 0x0 0x80000000>;
  38         };
  39 };
  40
  41 &can1 {
  42         status = "okay";
  43 };
  44
  45 &dcc {
  46         status = "okay";
  47 };
  48
  49 &gem3 {
  50         status = "okay";
  51         phy-handle = <&phy0>;
  52         phy-mode = "rgmii-id";
  53         phy0: phy@c {
  54                 reg = <0xc>;
  55                 ti,rx-internal-delay = <0x8>;
  56                 ti,tx-internal-delay = <0xa>;
  57                 ti,fifo-depth = <0x1>;
  58                 ti,dp83867-rxctrl-strap-quirk;
  59         };
  60 };
  61
  62 &gpio {
  63         status = "okay";
  64 };
  65
  66 &i2c1 {
  67         status = "okay";
  68         clock-frequency = <400000>;
  69
  70         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
  71         i2c-mux@74 { /* u34 */
  72                 compatible = "nxp,pca9548";
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75                 reg = <0x74>;
  76                 i2c@0 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         reg = <0>;
  80                         /*
  81                          * IIC_EEPROM 1kB memory which uses 256B blocks
  82                          * where every block has different address.
  83                          *    0 - 256B address 0x54
  84                          * 256B - 512B address 0x55
  85                          * 512B - 768B address 0x56
  86                          * 768B - 1024B address 0x57
  87                          */
  88                         eeprom@54 { /* u23 */
  89                                 compatible = "atmel,24c08";
  90                                 reg = <0x54>;
  91                                 #address-cells = <1>;
  92                                 #size-cells = <1>;
  93                         };
  94                 };
  95
  96                 i2c@1 {
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99                         reg = <1>;
 100                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 101                                 reg = <0x6c>;
 102                         };
 103                 };
 104
 105                 i2c@2 {
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         reg = <2>;
 109                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 110                                 reg = <0x43>;
 111                         };
 112                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 113                                 reg = <0x4d>;
 114                         };
 115                 };
 116
 117                 i2c@4 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         reg = <4>;
 121                         tca6416_u97: gpio@21 {
 122                                 compatible = "ti,tca6416";
 123                                 reg = <0x21>;
 124                                 gpio-controller;
 125                                 #gpio-cells = <2>;
 126                                 /*
 127                                  * IRQ not connected
 128                                  * Lines:
 129                                  * 0 - IRPS5401_ALERT_B
 130                                  * 1 - HDMI_8T49N241_INT_ALM
 131                                  * 2 - MAX6643_OT_B
 132                                  * 3 - MAX6643_FANFAIL_B
 133                                  * 5 - IIC_MUX_RESET_B
 134                                  * 6 - GEM3_EXP_RESET_B
 135                                  * 7 - FMC_LPC_PRSNT_M2C_B
 136                                  * 4, 10 - 17 - not connected
 137                                  */
 138                         };
 139                 };
 140
 141                 i2c@5 {
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         reg = <5>;
 145                 };
 146
 147                 i2c@7 {
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         reg = <7>;
 151                 };
 152
 153                 /* 3, 6 not connected */
 154         };
 155 };
 156
 157 &rtc {
 158         status = "okay";
 159 };
 160
 161 &sata {
 162         status = "okay";
 163         /* SATA OOB timing settings */
 164         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 165         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 166         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 167         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 168         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 169         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 170         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 171         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 172 };
 173
 174 /* SD1 with level shifter */
 175 &sdhci1 {
 176         status = "okay";
 177         no-1-8-v;
 178         disable-wp;
 179 };
 180
 181 &uart0 {
 182         status = "okay";
 183 };
 184
 185 &uart1 {
 186         status = "okay";
 187 };
 188
 189 /* ULPI SMSC USB3320 */
 190 &usb0 {
 191         status = "okay";
 192 };
 193
 194 &watchdog0 {
 195         status = "okay";
 196 };