arch/arm64/kvm/hyp/sysreg-sr.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012-2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/compiler.h>
   8 #include <linux/kvm_host.h>
   9
  10 #include <asm/kprobes.h>
  11 #include <asm/kvm_asm.h>
  12 #include <asm/kvm_emulate.h>
  13 #include <asm/kvm_hyp.h>
  14
  15 /*
  16  * Non-VHE: Both host and guest must save everything.
  17  *
  18  * VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and pstate,
  19  * which are handled as part of the el2 return state) on every switch.
  20  * tpidr_el0 and tpidrro_el0 only need to be switched when going
  21  * to host userspace or a different VCPU.  EL1 registers only need to be
  22  * switched when potentially going to run a different VCPU.  The latter two
  23  * classes are handled as part of kvm_arch_vcpu_load and kvm_arch_vcpu_put.
  24  */
  25
  26 static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
  27 {
  28         ctxt->sys_regs[MDSCR_EL1]       = read_sysreg(mdscr_el1);
  29
  30         /*
  31          * The host arm64 Linux uses sp_el0 to point to 'current' and it must
  32          * therefore be saved/restored on every entry/exit to/from the guest.
  33          */
  34         ctxt->gp_regs.regs.sp           = read_sysreg(sp_el0);
  35 }
  36
  37 static void __hyp_text __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
  38 {
  39         ctxt->sys_regs[TPIDR_EL0]       = read_sysreg(tpidr_el0);
  40         ctxt->sys_regs[TPIDRRO_EL0]     = read_sysreg(tpidrro_el0);
  41 }
  42
  43 static void __hyp_text __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
  44 {
  45         ctxt->sys_regs[CSSELR_EL1]      = read_sysreg(csselr_el1);
  46         ctxt->sys_regs[SCTLR_EL1]       = read_sysreg_el1(SYS_SCTLR);
  47         ctxt->sys_regs[ACTLR_EL1]       = read_sysreg(actlr_el1);
  48         ctxt->sys_regs[CPACR_EL1]       = read_sysreg_el1(SYS_CPACR);
  49         ctxt->sys_regs[TTBR0_EL1]       = read_sysreg_el1(SYS_TTBR0);
  50         ctxt->sys_regs[TTBR1_EL1]       = read_sysreg_el1(SYS_TTBR1);
  51         ctxt->sys_regs[TCR_EL1]         = read_sysreg_el1(SYS_TCR);
  52         ctxt->sys_regs[ESR_EL1]         = read_sysreg_el1(SYS_ESR);
  53         ctxt->sys_regs[AFSR0_EL1]       = read_sysreg_el1(SYS_AFSR0);
  54         ctxt->sys_regs[AFSR1_EL1]       = read_sysreg_el1(SYS_AFSR1);
  55         ctxt->sys_regs[FAR_EL1]         = read_sysreg_el1(SYS_FAR);
  56         ctxt->sys_regs[MAIR_EL1]        = read_sysreg_el1(SYS_MAIR);
  57         ctxt->sys_regs[VBAR_EL1]        = read_sysreg_el1(SYS_VBAR);
  58         ctxt->sys_regs[CONTEXTIDR_EL1]  = read_sysreg_el1(SYS_CONTEXTIDR);
  59         ctxt->sys_regs[AMAIR_EL1]       = read_sysreg_el1(SYS_AMAIR);
  60         ctxt->sys_regs[CNTKCTL_EL1]     = read_sysreg_el1(SYS_CNTKCTL);
  61         ctxt->sys_regs[PAR_EL1]         = read_sysreg(par_el1);
  62         ctxt->sys_regs[TPIDR_EL1]       = read_sysreg(tpidr_el1);
  63
  64         ctxt->gp_regs.sp_el1            = read_sysreg(sp_el1);
  65         ctxt->gp_regs.elr_el1           = read_sysreg_el1(SYS_ELR);
  66         ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(SYS_SPSR);
  67 }
  68
  69 static void __hyp_text __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
  70 {
  71         ctxt->gp_regs.regs.pc           = read_sysreg_el2(SYS_ELR);
  72         ctxt->gp_regs.regs.pstate       = read_sysreg_el2(SYS_SPSR);
  73
  74         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
  75                 ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
  76 }
  77
  78 void __hyp_text __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt)
  79 {
  80         __sysreg_save_el1_state(ctxt);
  81         __sysreg_save_common_state(ctxt);
  82         __sysreg_save_user_state(ctxt);
  83         __sysreg_save_el2_return_state(ctxt);
  84 }
  85
  86 void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt)
  87 {
  88         __sysreg_save_common_state(ctxt);
  89 }
  90 NOKPROBE_SYMBOL(sysreg_save_host_state_vhe);
  91
  92 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
  93 {
  94         __sysreg_save_common_state(ctxt);
  95         __sysreg_save_el2_return_state(ctxt);
  96 }
  97 NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe);
  98
  99 static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
 100 {
 101         write_sysreg(ctxt->sys_regs[MDSCR_EL1],   mdscr_el1);
 102
 103         /*
 104          * The host arm64 Linux uses sp_el0 to point to 'current' and it must
 105          * therefore be saved/restored on every entry/exit to/from the guest.
 106          */
 107         write_sysreg(ctxt->gp_regs.regs.sp,       sp_el0);
 108 }
 109
 110 static void __hyp_text __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
 111 {
 112         write_sysreg(ctxt->sys_regs[TPIDR_EL0],         tpidr_el0);
 113         write_sysreg(ctxt->sys_regs[TPIDRRO_EL0],       tpidrro_el0);
 114 }
 115
 116 static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
 117 {
 118         write_sysreg(ctxt->sys_regs[MPIDR_EL1],         vmpidr_el2);
 119         write_sysreg(ctxt->sys_regs[CSSELR_EL1],        csselr_el1);
 120
 121         if (!cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
 122                 write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1],     SYS_SCTLR);
 123                 write_sysreg_el1(ctxt->sys_regs[TCR_EL1],       SYS_TCR);
 124         } else  if (!ctxt->__hyp_running_vcpu) {
 125                 /*
 126                  * Must only be done for guest registers, hence the context
 127                  * test. We're coming from the host, so SCTLR.M is already
 128                  * set. Pairs with __activate_traps_nvhe().
 129                  */
 130                 write_sysreg_el1((ctxt->sys_regs[TCR_EL1] |
 131                                   TCR_EPD1_MASK | TCR_EPD0_MASK),
 132                                  SYS_TCR);
 133                 isb();
 134         }
 135
 136         write_sysreg(ctxt->sys_regs[ACTLR_EL1],         actlr_el1);
 137         write_sysreg_el1(ctxt->sys_regs[CPACR_EL1],     SYS_CPACR);
 138         write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1],     SYS_TTBR0);
 139         write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1],     SYS_TTBR1);
 140         write_sysreg_el1(ctxt->sys_regs[ESR_EL1],       SYS_ESR);
 141         write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1],     SYS_AFSR0);
 142         write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1],     SYS_AFSR1);
 143         write_sysreg_el1(ctxt->sys_regs[FAR_EL1],       SYS_FAR);
 144         write_sysreg_el1(ctxt->sys_regs[MAIR_EL1],      SYS_MAIR);
 145         write_sysreg_el1(ctxt->sys_regs[VBAR_EL1],      SYS_VBAR);
 146         write_sysreg_el1(ctxt->sys_regs[CONTEXTIDR_EL1],SYS_CONTEXTIDR);
 147         write_sysreg_el1(ctxt->sys_regs[AMAIR_EL1],     SYS_AMAIR);
 148         write_sysreg_el1(ctxt->sys_regs[CNTKCTL_EL1],   SYS_CNTKCTL);
 149         write_sysreg(ctxt->sys_regs[PAR_EL1],           par_el1);
 150         write_sysreg(ctxt->sys_regs[TPIDR_EL1],         tpidr_el1);
 151
 152         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE) &&
 153             ctxt->__hyp_running_vcpu) {
 154                 /*
 155                  * Must only be done for host registers, hence the context
 156                  * test. Pairs with __deactivate_traps_nvhe().
 157                  */
 158                 isb();
 159                 /*
 160                  * At this stage, and thanks to the above isb(), S2 is
 161                  * deconfigured and disabled. We can now restore the host's
 162                  * S1 configuration: SCTLR, and only then TCR.
 163                  */
 164                 write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1],     SYS_SCTLR);
 165                 isb();
 166                 write_sysreg_el1(ctxt->sys_regs[TCR_EL1],       SYS_TCR);
 167         }
 168
 169         write_sysreg(ctxt->gp_regs.sp_el1,              sp_el1);
 170         write_sysreg_el1(ctxt->gp_regs.elr_el1,         SYS_ELR);
 171         write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],SYS_SPSR);
 172 }
 173
 174 static void __hyp_text
 175 __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
 176 {
 177         u64 pstate = ctxt->gp_regs.regs.pstate;
 178         u64 mode = pstate & PSR_AA32_MODE_MASK;
 179
 180         /*
 181          * Safety check to ensure we're setting the CPU up to enter the guest
 182          * in a less privileged mode.
 183          *
 184          * If we are attempting a return to EL2 or higher in AArch64 state,
 185          * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
 186          * we'll take an illegal exception state exception immediately after
 187          * the ERET to the guest.  Attempts to return to AArch32 Hyp will
 188          * result in an illegal exception return because EL2's execution state
 189          * is determined by SCR_EL3.RW.
 190          */
 191         if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
 192                 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
 193
 194         write_sysreg_el2(ctxt->gp_regs.regs.pc,         SYS_ELR);
 195         write_sysreg_el2(pstate,                        SYS_SPSR);
 196
 197         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
 198                 write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
 199 }
 200
 201 void __hyp_text __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt)
 202 {
 203         __sysreg_restore_el1_state(ctxt);
 204         __sysreg_restore_common_state(ctxt);
 205         __sysreg_restore_user_state(ctxt);
 206         __sysreg_restore_el2_return_state(ctxt);
 207 }
 208
 209 void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt)
 210 {
 211         __sysreg_restore_common_state(ctxt);
 212 }
 213 NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe);
 214
 215 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
 216 {
 217         __sysreg_restore_common_state(ctxt);
 218         __sysreg_restore_el2_return_state(ctxt);
 219 }
 220 NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
 221
 222 void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
 223 {
 224         u64 *spsr, *sysreg;
 225
 226         if (!vcpu_el1_is_32bit(vcpu))
 227                 return;
 228
 229         spsr = vcpu->arch.ctxt.gp_regs.spsr;
 230         sysreg = vcpu->arch.ctxt.sys_regs;
 231
 232         spsr[KVM_SPSR_ABT] = read_sysreg(spsr_abt);
 233         spsr[KVM_SPSR_UND] = read_sysreg(spsr_und);
 234         spsr[KVM_SPSR_IRQ] = read_sysreg(spsr_irq);
 235         spsr[KVM_SPSR_FIQ] = read_sysreg(spsr_fiq);
 236
 237         sysreg[DACR32_EL2] = read_sysreg(dacr32_el2);
 238         sysreg[IFSR32_EL2] = read_sysreg(ifsr32_el2);
 239
 240         if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
 241                 sysreg[DBGVCR32_EL2] = read_sysreg(dbgvcr32_el2);
 242 }
 243
 244 void __hyp_text __sysreg32_restore_state(struct kvm_vcpu *vcpu)
 245 {
 246         u64 *spsr, *sysreg;
 247
 248         if (!vcpu_el1_is_32bit(vcpu))
 249                 return;
 250
 251         spsr = vcpu->arch.ctxt.gp_regs.spsr;
 252         sysreg = vcpu->arch.ctxt.sys_regs;
 253
 254         write_sysreg(spsr[KVM_SPSR_ABT], spsr_abt);
 255         write_sysreg(spsr[KVM_SPSR_UND], spsr_und);
 256         write_sysreg(spsr[KVM_SPSR_IRQ], spsr_irq);
 257         write_sysreg(spsr[KVM_SPSR_FIQ], spsr_fiq);
 258
 259         write_sysreg(sysreg[DACR32_EL2], dacr32_el2);
 260         write_sysreg(sysreg[IFSR32_EL2], ifsr32_el2);
 261
 262         if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
 263                 write_sysreg(sysreg[DBGVCR32_EL2], dbgvcr32_el2);
 264 }
 265
 266 /**
 267  * kvm_vcpu_load_sysregs - Load guest system registers to the physical CPU
 268  *
 269  * @vcpu: The VCPU pointer
 270  *
 271  * Load system registers that do not affect the host's execution, for
 272  * example EL1 system registers on a VHE system where the host kernel
 273  * runs at EL2.  This function is called from KVM's vcpu_load() function
 274  * and loading system register state early avoids having to load them on
 275  * every entry to the VM.
 276  */
 277 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu)
 278 {
 279         struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
 280         struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
 281
 282         if (!has_vhe())
 283                 return;
 284
 285         __sysreg_save_user_state(host_ctxt);
 286
 287         /*
 288          * Load guest EL1 and user state
 289          *
 290          * We must restore the 32-bit state before the sysregs, thanks
 291          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 292          */
 293         __sysreg32_restore_state(vcpu);
 294         __sysreg_restore_user_state(guest_ctxt);
 295         __sysreg_restore_el1_state(guest_ctxt);
 296
 297         vcpu->arch.sysregs_loaded_on_cpu = true;
 298
 299         activate_traps_vhe_load(vcpu);
 300 }
 301
 302 /**
 303  * kvm_vcpu_put_sysregs - Restore host system registers to the physical CPU
 304  *
 305  * @vcpu: The VCPU pointer
 306  *
 307  * Save guest system registers that do not affect the host's execution, for
 308  * example EL1 system registers on a VHE system where the host kernel
 309  * runs at EL2.  This function is called from KVM's vcpu_put() function
 310  * and deferring saving system register state until we're no longer running the
 311  * VCPU avoids having to save them on every exit from the VM.
 312  */
 313 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu)
 314 {
 315         struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
 316         struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
 317
 318         if (!has_vhe())
 319                 return;
 320
 321         deactivate_traps_vhe_put();
 322
 323         __sysreg_save_el1_state(guest_ctxt);
 324         __sysreg_save_user_state(guest_ctxt);
 325         __sysreg32_save_state(vcpu);
 326
 327         /* Restore host user state */
 328         __sysreg_restore_user_state(host_ctxt);
 329
 330         vcpu->arch.sysregs_loaded_on_cpu = false;
 331 }
 332
 333 void __hyp_text __kvm_enable_ssbs(void)
 334 {
 335         u64 tmp;
 336
 337         asm volatile(
 338         "mrs    %0, sctlr_el2\n"
 339         "orr    %0, %0, %1\n"
 340         "msr    sctlr_el2, %0"
 341         : "=&r" (tmp) : "L" (SCTLR_ELx_DSSBS));
 342 }