arch/arm64/kvm/hyp/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/irqflags.h>
   8
   9 #include <asm/kvm_hyp.h>
  10 #include <asm/kvm_mmu.h>
  11 #include <asm/tlbflush.h>
  12
  13 struct tlb_inv_context {
  14         unsigned long   flags;
  15         u64             tcr;
  16         u64             sctlr;
  17 };
  18
  19 static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
  20                                                  struct tlb_inv_context *cxt)
  21 {
  22         u64 val;
  23
  24         local_irq_save(cxt->flags);
  25
  26         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
  27                 /*
  28                  * For CPUs that are affected by ARM errata 1165522 or 1530923,
  29                  * we cannot trust stage-1 to be in a correct state at that
  30                  * point. Since we do not want to force a full load of the
  31                  * vcpu state, we prevent the EL1 page-table walker to
  32                  * allocate new TLBs. This is done by setting the EPD bits
  33                  * in the TCR_EL1 register. We also need to prevent it to
  34                  * allocate IPA->PA walks, so we enable the S1 MMU...
  35                  */
  36                 val = cxt->tcr = read_sysreg_el1(SYS_TCR);
  37                 val |= TCR_EPD1_MASK | TCR_EPD0_MASK;
  38                 write_sysreg_el1(val, SYS_TCR);
  39                 val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR);
  40                 val |= SCTLR_ELx_M;
  41                 write_sysreg_el1(val, SYS_SCTLR);
  42         }
  43
  44         /*
  45          * With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
  46          * most TLB operations target EL2/EL0. In order to affect the
  47          * guest TLBs (EL1/EL0), we need to change one of these two
  48          * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so
  49          * let's flip TGE before executing the TLB operation.
  50          *
  51          * ARM erratum 1165522 requires some special handling (again),
  52          * as we need to make sure both stages of translation are in
  53          * place before clearing TGE. __load_guest_stage2() already
  54          * has an ISB in order to deal with this.
  55          */
  56         __load_guest_stage2(kvm);
  57         val = read_sysreg(hcr_el2);
  58         val &= ~HCR_TGE;
  59         write_sysreg(val, hcr_el2);
  60         isb();
  61 }
  62
  63 static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm,
  64                                                   struct tlb_inv_context *cxt)
  65 {
  66         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
  67                 u64 val;
  68
  69                 /*
  70                  * For CPUs that are affected by ARM 1319367, we need to
  71                  * avoid a host Stage-1 walk while we have the guest's
  72                  * VMID set in the VTTBR in order to invalidate TLBs.
  73                  * We're guaranteed that the S1 MMU is enabled, so we can
  74                  * simply set the EPD bits to avoid any further TLB fill.
  75                  */
  76                 val = cxt->tcr = read_sysreg_el1(SYS_TCR);
  77                 val |= TCR_EPD1_MASK | TCR_EPD0_MASK;
  78                 write_sysreg_el1(val, SYS_TCR);
  79                 isb();
  80         }
  81
  82         __load_guest_stage2(kvm);
  83         isb();
  84 }
  85
  86 static void __hyp_text __tlb_switch_to_guest(struct kvm *kvm,
  87                                              struct tlb_inv_context *cxt)
  88 {
  89         if (has_vhe())
  90                 __tlb_switch_to_guest_vhe(kvm, cxt);
  91         else
  92                 __tlb_switch_to_guest_nvhe(kvm, cxt);
  93 }
  94
  95 static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm,
  96                                                 struct tlb_inv_context *cxt)
  97 {
  98         /*
  99          * We're done with the TLB operation, let's restore the host's
 100          * view of HCR_EL2.
 101          */
 102         write_sysreg(0, vttbr_el2);
 103         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 104         isb();
 105
 106         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) {
 107                 /* Restore the registers to what they were */
 108                 write_sysreg_el1(cxt->tcr, SYS_TCR);
 109                 write_sysreg_el1(cxt->sctlr, SYS_SCTLR);
 110         }
 111
 112         local_irq_restore(cxt->flags);
 113 }
 114
 115 static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm,
 116                                                  struct tlb_inv_context *cxt)
 117 {
 118         write_sysreg(0, vttbr_el2);
 119
 120         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
 121                 /* Ensure write of the host VMID */
 122                 isb();
 123                 /* Restore the host's TCR_EL1 */
 124                 write_sysreg_el1(cxt->tcr, SYS_TCR);
 125         }
 126 }
 127
 128 static void __hyp_text __tlb_switch_to_host(struct kvm *kvm,
 129                                             struct tlb_inv_context *cxt)
 130 {
 131         if (has_vhe())
 132                 __tlb_switch_to_host_vhe(kvm, cxt);
 133         else
 134                 __tlb_switch_to_host_nvhe(kvm, cxt);
 135 }
 136
 137 void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
 138 {
 139         struct tlb_inv_context cxt;
 140
 141         dsb(ishst);
 142
 143         /* Switch to requested VMID */
 144         kvm = kern_hyp_va(kvm);
 145         __tlb_switch_to_guest(kvm, &cxt);
 146
 147         /*
 148          * We could do so much better if we had the VA as well.
 149          * Instead, we invalidate Stage-2 for this IPA, and the
 150          * whole of Stage-1. Weep...
 151          */
 152         ipa >>= 12;
 153         __tlbi(ipas2e1is, ipa);
 154
 155         /*
 156          * We have to ensure completion of the invalidation at Stage-2,
 157          * since a table walk on another CPU could refill a TLB with a
 158          * complete (S1 + S2) walk based on the old Stage-2 mapping if
 159          * the Stage-1 invalidation happened first.
 160          */
 161         dsb(ish);
 162         __tlbi(vmalle1is);
 163         dsb(ish);
 164         isb();
 165
 166         /*
 167          * If the host is running at EL1 and we have a VPIPT I-cache,
 168          * then we must perform I-cache maintenance at EL2 in order for
 169          * it to have an effect on the guest. Since the guest cannot hit
 170          * I-cache lines allocated with a different VMID, we don't need
 171          * to worry about junk out of guest reset (we nuke the I-cache on
 172          * VMID rollover), but we do need to be careful when remapping
 173          * executable pages for the same guest. This can happen when KSM
 174          * takes a CoW fault on an executable page, copies the page into
 175          * a page that was previously mapped in the guest and then needs
 176          * to invalidate the guest view of the I-cache for that page
 177          * from EL1. To solve this, we invalidate the entire I-cache when
 178          * unmapping a page from a guest if we have a VPIPT I-cache but
 179          * the host is running at EL1. As above, we could do better if
 180          * we had the VA.
 181          *
 182          * The moral of this story is: if you have a VPIPT I-cache, then
 183          * you should be running with VHE enabled.
 184          */
 185         if (!has_vhe() && icache_is_vpipt())
 186                 __flush_icache_all();
 187
 188         __tlb_switch_to_host(kvm, &cxt);
 189 }
 190
 191 void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
 192 {
 193         struct tlb_inv_context cxt;
 194
 195         dsb(ishst);
 196
 197         /* Switch to requested VMID */
 198         kvm = kern_hyp_va(kvm);
 199         __tlb_switch_to_guest(kvm, &cxt);
 200
 201         __tlbi(vmalls12e1is);
 202         dsb(ish);
 203         isb();
 204
 205         __tlb_switch_to_host(kvm, &cxt);
 206 }
 207
 208 void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
 209 {
 210         struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
 211         struct tlb_inv_context cxt;
 212
 213         /* Switch to requested VMID */
 214         __tlb_switch_to_guest(kvm, &cxt);
 215
 216         __tlbi(vmalle1);
 217         dsb(nsh);
 218         isb();
 219
 220         __tlb_switch_to_host(kvm, &cxt);
 221 }
 222
 223 void __hyp_text __kvm_flush_vm_context(void)
 224 {
 225         dsb(ishst);
 226         __tlbi(alle1is);
 227
 228         /*
 229          * VIPT and PIPT caches are not affected by VMID, so no maintenance
 230          * is necessary across a VMID rollover.
 231          *
 232          * VPIPT caches constrain lookup and maintenance to the active VMID,
 233          * so we need to invalidate lines with a stale VMID to avoid an ABA
 234          * race after multiple rollovers.
 235          *
 236          */
 237         if (icache_is_vpipt())
 238                 asm volatile("ic ialluis");
 239
 240         dsb(ish);
 241 }