arch/c6x/include/asm/irq.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  Port on Texas Instruments TMS320C6x architecture
   4  *
   5  *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
   6  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
   7  *
   8  *  Large parts taken directly from powerpc.
   9  */
  10 #ifndef _ASM_C6X_IRQ_H
  11 #define _ASM_C6X_IRQ_H
  12
  13 #include <linux/irqdomain.h>
  14 #include <linux/threads.h>
  15 #include <linux/list.h>
  16 #include <linux/radix-tree.h>
  17 #include <asm/percpu.h>
  18
  19 #define irq_canonicalize(irq)  (irq)
  20
  21 /*
  22  * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
  23  * are reserved. The remaining 12 vectors are used to route SoC interrupts.
  24  * These interrupt vectors are prioritized with IRQ 4 having the highest
  25  * priority and IRQ 15 having the lowest.
  26  *
  27  * The C64x+ megamodule provides a PIC which combines SoC IRQ sources into a
  28  * single core IRQ vector. There are four combined sources, each of which
  29  * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
  30  * can each route a single SoC interrupt directly.
  31  */
  32 #define NR_PRIORITY_IRQS 16
  33
  34 /* Total number of virq in the platform */
  35 #define NR_IRQS         256
  36
  37 /* This number is used when no interrupt has been assigned */
  38 #define NO_IRQ          0
  39
  40 extern void __init init_pic_c64xplus(void);
  41
  42 extern void init_IRQ(void);
  43
  44 struct pt_regs;
  45
  46 extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
  47
  48 extern unsigned long irq_err_count;
  49
  50 #endif /* _ASM_C6X_IRQ_H */