?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / arch / mips / dec / setup.c
blob61a0bf13e308379b034aac3cf4d54f2fc42c8911
1 /*
2 * System-specific setup, especially interrupts.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
10 */
11 #include <linux/console.h>
12 #include <linux/export.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/irq.h>
17 #include <linux/irqnr.h>
18 #include <linux/param.h>
19 #include <linux/percpu-defs.h>
20 #include <linux/sched.h>
21 #include <linux/spinlock.h>
22 #include <linux/types.h>
23 #include <linux/pm.h>
24
25 #include <asm/bootinfo.h>
26 #include <asm/cpu.h>
27 #include <asm/cpu-features.h>
28 #include <asm/cpu-type.h>
29 #include <asm/irq.h>
30 #include <asm/irq_cpu.h>
31 #include <asm/mipsregs.h>
32 #include <asm/reboot.h>
33 #include <asm/time.h>
34 #include <asm/traps.h>
35 #include <asm/wbflush.h>
36
37 #include <asm/dec/interrupts.h>
38 #include <asm/dec/ioasic.h>
39 #include <asm/dec/ioasic_addrs.h>
40 #include <asm/dec/ioasic_ints.h>
41 #include <asm/dec/kn01.h>
42 #include <asm/dec/kn02.h>
43 #include <asm/dec/kn02ba.h>
44 #include <asm/dec/kn02ca.h>
45 #include <asm/dec/kn03.h>
46 #include <asm/dec/kn230.h>
47 #include <asm/dec/system.h>
48
49
50 extern void dec_machine_restart(char *command);
51 extern void dec_machine_halt(void);
52 extern void dec_machine_power_off(void);
53 extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
54
55 unsigned long dec_kn_slot_base, dec_kn_slot_size;
56
57 EXPORT_SYMBOL(dec_kn_slot_base);
58 EXPORT_SYMBOL(dec_kn_slot_size);
59
60 int dec_tc_bus;
61
62 DEFINE_SPINLOCK(ioasic_ssr_lock);
63 EXPORT_SYMBOL(ioasic_ssr_lock);
64
65 volatile u32 *ioasic_base;
66
67 EXPORT_SYMBOL(ioasic_base);
68
69 /*
70 * IRQ routing and priority tables. Priorites are set as follows:
71 *
72 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
73 *
74 * MEMORY CPU CPU CPU ASIC CPU CPU
75 * RTC CPU CPU CPU ASIC CPU CPU
76 * DMA - - - ASIC ASIC ASIC
77 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
78 * SERIAL1 - - - ASIC - ASIC
79 * SCSI CPU CPU CSR ASIC ASIC ASIC
80 * ETHERNET CPU * CSR ASIC ASIC ASIC
81 * other - - - ASIC - -
82 * TC2 - - CSR CPU ASIC ASIC
83 * TC1 - - CSR CPU ASIC ASIC
84 * TC0 - - CSR CPU ASIC ASIC
85 * other - CPU - CPU ASIC ASIC
86 * other - - - - CPU CPU
87 *
88 * * -- shared with SCSI
89 */
90
91 int dec_interrupt[DEC_NR_INTS] = {
92 [0 ... DEC_NR_INTS - 1] = -1
93 };
94
95 EXPORT_SYMBOL(dec_interrupt);
96
97 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
98 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
99 };
100 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
101 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
102 };
103 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
104 int *fpu_kstat_irq;
105
106 static struct irqaction ioirq = {
107 .handler = no_action,
108 .name = "cascade",
109 .flags = IRQF_NO_THREAD,
110 };
111 static struct irqaction fpuirq = {
112 .handler = no_action,
113 .name = "fpu",
114 .flags = IRQF_NO_THREAD,
115 };
116
117 static struct irqaction busirq = {
118 .name = "bus error",
119 .flags = IRQF_NO_THREAD,
120 };
121
122 static struct irqaction haltirq = {
123 .handler = dec_intr_halt,
124 .name = "halt",
125 .flags = IRQF_NO_THREAD,
126 };
127
128
129 /*
130 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
131 */
132 static void __init dec_be_init(void)
133 {
134 switch (mips_machtype) {
135 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
136 board_be_handler = dec_kn01_be_handler;
137 busirq.handler = dec_kn01_be_interrupt;
138 busirq.flags |= IRQF_SHARED;
139 dec_kn01_be_init();
140 break;
141 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
142 case MACH_DS5000_XX: /* DS5000/xx Maxine */
143 board_be_handler = dec_kn02xa_be_handler;
144 busirq.handler = dec_kn02xa_be_interrupt;
145 dec_kn02xa_be_init();
146 break;
147 case MACH_DS5000_200: /* DS5000/200 3max */
148 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
149 case MACH_DS5900: /* DS5900 bigmax */
150 board_be_handler = dec_ecc_be_handler;
151 busirq.handler = dec_ecc_be_interrupt;
152 dec_ecc_be_init();
153 break;
154 }
155 }
156
157 void __init plat_mem_setup(void)
158 {
159 board_be_init = dec_be_init;
160
161 wbflush_setup();
162
163 _machine_restart = dec_machine_restart;
164 _machine_halt = dec_machine_halt;
165 pm_power_off = dec_machine_power_off;
166
167 ioport_resource.start = ~0UL;
168 ioport_resource.end = 0UL;
169 }
170
171 /*
172 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
173 * or DS3100 (aka Pmax).
174 */
175 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
176 [DEC_IRQ_CASCADE] = -1,
177 [DEC_IRQ_AB_RECV] = -1,
178 [DEC_IRQ_AB_XMIT] = -1,
179 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
180 [DEC_IRQ_ASC] = -1,
181 [DEC_IRQ_FLOPPY] = -1,
182 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
183 [DEC_IRQ_HALT] = -1,
184 [DEC_IRQ_ISDN] = -1,
185 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
186 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
187 [DEC_IRQ_PSU] = -1,
188 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
189 [DEC_IRQ_SCC0] = -1,
190 [DEC_IRQ_SCC1] = -1,
191 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
192 [DEC_IRQ_TC0] = -1,
193 [DEC_IRQ_TC1] = -1,
194 [DEC_IRQ_TC2] = -1,
195 [DEC_IRQ_TIMER] = -1,
196 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
197 [DEC_IRQ_ASC_MERR] = -1,
198 [DEC_IRQ_ASC_ERR] = -1,
199 [DEC_IRQ_ASC_DMA] = -1,
200 [DEC_IRQ_FLOPPY_ERR] = -1,
201 [DEC_IRQ_ISDN_ERR] = -1,
202 [DEC_IRQ_ISDN_RXDMA] = -1,
203 [DEC_IRQ_ISDN_TXDMA] = -1,
204 [DEC_IRQ_LANCE_MERR] = -1,
205 [DEC_IRQ_SCC0A_RXERR] = -1,
206 [DEC_IRQ_SCC0A_RXDMA] = -1,
207 [DEC_IRQ_SCC0A_TXERR] = -1,
208 [DEC_IRQ_SCC0A_TXDMA] = -1,
209 [DEC_IRQ_AB_RXERR] = -1,
210 [DEC_IRQ_AB_RXDMA] = -1,
211 [DEC_IRQ_AB_TXERR] = -1,
212 [DEC_IRQ_AB_TXDMA] = -1,
213 [DEC_IRQ_SCC1A_RXERR] = -1,
214 [DEC_IRQ_SCC1A_RXDMA] = -1,
215 [DEC_IRQ_SCC1A_TXERR] = -1,
216 [DEC_IRQ_SCC1A_TXDMA] = -1,
217 };
218
219 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
220 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
221 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
222 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
223 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
224 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
225 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
226 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
227 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
228 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
229 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
230 { { .i = DEC_CPU_IRQ_ALL },
231 { .p = cpu_all_int } },
232 };
233
234 static void __init dec_init_kn01(void)
235 {
236 /* IRQ routing. */
237 memcpy(&dec_interrupt, &kn01_interrupt,
238 sizeof(kn01_interrupt));
239
240 /* CPU IRQ priorities. */
241 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
242 sizeof(kn01_cpu_mask_nr_tbl));
243
244 mips_cpu_irq_init();
245
246 } /* dec_init_kn01 */
247
248
249 /*
250 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
251 */
252 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
253 [DEC_IRQ_CASCADE] = -1,
254 [DEC_IRQ_AB_RECV] = -1,
255 [DEC_IRQ_AB_XMIT] = -1,
256 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
257 [DEC_IRQ_ASC] = -1,
258 [DEC_IRQ_FLOPPY] = -1,
259 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
260 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
261 [DEC_IRQ_ISDN] = -1,
262 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
263 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
264 [DEC_IRQ_PSU] = -1,
265 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
266 [DEC_IRQ_SCC0] = -1,
267 [DEC_IRQ_SCC1] = -1,
268 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
269 [DEC_IRQ_TC0] = -1,
270 [DEC_IRQ_TC1] = -1,
271 [DEC_IRQ_TC2] = -1,
272 [DEC_IRQ_TIMER] = -1,
273 [DEC_IRQ_VIDEO] = -1,
274 [DEC_IRQ_ASC_MERR] = -1,
275 [DEC_IRQ_ASC_ERR] = -1,
276 [DEC_IRQ_ASC_DMA] = -1,
277 [DEC_IRQ_FLOPPY_ERR] = -1,
278 [DEC_IRQ_ISDN_ERR] = -1,
279 [DEC_IRQ_ISDN_RXDMA] = -1,
280 [DEC_IRQ_ISDN_TXDMA] = -1,
281 [DEC_IRQ_LANCE_MERR] = -1,
282 [DEC_IRQ_SCC0A_RXERR] = -1,
283 [DEC_IRQ_SCC0A_RXDMA] = -1,
284 [DEC_IRQ_SCC0A_TXERR] = -1,
285 [DEC_IRQ_SCC0A_TXDMA] = -1,
286 [DEC_IRQ_AB_RXERR] = -1,
287 [DEC_IRQ_AB_RXDMA] = -1,
288 [DEC_IRQ_AB_TXERR] = -1,
289 [DEC_IRQ_AB_TXDMA] = -1,
290 [DEC_IRQ_SCC1A_RXERR] = -1,
291 [DEC_IRQ_SCC1A_RXDMA] = -1,
292 [DEC_IRQ_SCC1A_TXERR] = -1,
293 [DEC_IRQ_SCC1A_TXDMA] = -1,
294 };
295
296 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
297 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
298 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
299 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
300 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
301 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
302 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
303 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
304 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
305 { { .i = DEC_CPU_IRQ_ALL },
306 { .p = cpu_all_int } },
307 };
308
309 static void __init dec_init_kn230(void)
310 {
311 /* IRQ routing. */
312 memcpy(&dec_interrupt, &kn230_interrupt,
313 sizeof(kn230_interrupt));
314
315 /* CPU IRQ priorities. */
316 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
317 sizeof(kn230_cpu_mask_nr_tbl));
318
319 mips_cpu_irq_init();
320
321 } /* dec_init_kn230 */
322
323
324 /*
325 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
326 */
327 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
328 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
329 [DEC_IRQ_AB_RECV] = -1,
330 [DEC_IRQ_AB_XMIT] = -1,
331 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
332 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
333 [DEC_IRQ_FLOPPY] = -1,
334 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
335 [DEC_IRQ_HALT] = -1,
336 [DEC_IRQ_ISDN] = -1,
337 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
338 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
339 [DEC_IRQ_PSU] = -1,
340 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
341 [DEC_IRQ_SCC0] = -1,
342 [DEC_IRQ_SCC1] = -1,
343 [DEC_IRQ_SII] = -1,
344 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
345 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
346 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
347 [DEC_IRQ_TIMER] = -1,
348 [DEC_IRQ_VIDEO] = -1,
349 [DEC_IRQ_ASC_MERR] = -1,
350 [DEC_IRQ_ASC_ERR] = -1,
351 [DEC_IRQ_ASC_DMA] = -1,
352 [DEC_IRQ_FLOPPY_ERR] = -1,
353 [DEC_IRQ_ISDN_ERR] = -1,
354 [DEC_IRQ_ISDN_RXDMA] = -1,
355 [DEC_IRQ_ISDN_TXDMA] = -1,
356 [DEC_IRQ_LANCE_MERR] = -1,
357 [DEC_IRQ_SCC0A_RXERR] = -1,
358 [DEC_IRQ_SCC0A_RXDMA] = -1,
359 [DEC_IRQ_SCC0A_TXERR] = -1,
360 [DEC_IRQ_SCC0A_TXDMA] = -1,
361 [DEC_IRQ_AB_RXERR] = -1,
362 [DEC_IRQ_AB_RXDMA] = -1,
363 [DEC_IRQ_AB_TXERR] = -1,
364 [DEC_IRQ_AB_TXDMA] = -1,
365 [DEC_IRQ_SCC1A_RXERR] = -1,
366 [DEC_IRQ_SCC1A_RXDMA] = -1,
367 [DEC_IRQ_SCC1A_TXERR] = -1,
368 [DEC_IRQ_SCC1A_TXDMA] = -1,
369 };
370
371 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
372 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
373 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
374 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
375 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
376 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
377 { .p = kn02_io_int } },
378 { { .i = DEC_CPU_IRQ_ALL },
379 { .p = cpu_all_int } },
380 };
381
382 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
383 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
384 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
385 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
386 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
387 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
388 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
389 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
390 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
391 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
392 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
393 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
394 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
395 { { .i = KN02_IRQ_ALL },
396 { .p = kn02_all_int } },
397 };
398
399 static void __init dec_init_kn02(void)
400 {
401 /* IRQ routing. */
402 memcpy(&dec_interrupt, &kn02_interrupt,
403 sizeof(kn02_interrupt));
404
405 /* CPU IRQ priorities. */
406 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
407 sizeof(kn02_cpu_mask_nr_tbl));
408
409 /* KN02 CSR IRQ priorities. */
410 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
411 sizeof(kn02_asic_mask_nr_tbl));
412
413 mips_cpu_irq_init();
414 init_kn02_irqs(KN02_IRQ_BASE);
415
416 } /* dec_init_kn02 */
417
418
419 /*
420 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
421 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
422 * DS5000/150, aka 4min.
423 */
424 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
425 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
426 [DEC_IRQ_AB_RECV] = -1,
427 [DEC_IRQ_AB_XMIT] = -1,
428 [DEC_IRQ_DZ11] = -1,
429 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
430 [DEC_IRQ_FLOPPY] = -1,
431 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
432 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
433 [DEC_IRQ_ISDN] = -1,
434 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
435 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
436 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
437 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
438 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
439 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
440 [DEC_IRQ_SII] = -1,
441 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
442 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
443 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
444 [DEC_IRQ_TIMER] = -1,
445 [DEC_IRQ_VIDEO] = -1,
446 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
447 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
448 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
449 [DEC_IRQ_FLOPPY_ERR] = -1,
450 [DEC_IRQ_ISDN_ERR] = -1,
451 [DEC_IRQ_ISDN_RXDMA] = -1,
452 [DEC_IRQ_ISDN_TXDMA] = -1,
453 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
454 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
455 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
456 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
457 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
458 [DEC_IRQ_AB_RXERR] = -1,
459 [DEC_IRQ_AB_RXDMA] = -1,
460 [DEC_IRQ_AB_TXERR] = -1,
461 [DEC_IRQ_AB_TXDMA] = -1,
462 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
463 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
464 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
465 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
466 };
467
468 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
469 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
470 { .p = kn02xa_io_int } },
471 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
472 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
473 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
474 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
475 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
476 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
477 { { .i = DEC_CPU_IRQ_ALL },
478 { .p = cpu_all_int } },
479 };
480
481 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
482 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
483 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
484 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
485 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
486 { { .i = IO_IRQ_DMA },
487 { .p = asic_dma_int } },
488 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
489 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
490 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
491 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
492 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
493 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
494 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
495 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
496 { { .i = IO_IRQ_ALL },
497 { .p = asic_all_int } },
498 };
499
500 static void __init dec_init_kn02ba(void)
501 {
502 /* IRQ routing. */
503 memcpy(&dec_interrupt, &kn02ba_interrupt,
504 sizeof(kn02ba_interrupt));
505
506 /* CPU IRQ priorities. */
507 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
508 sizeof(kn02ba_cpu_mask_nr_tbl));
509
510 /* I/O ASIC IRQ priorities. */
511 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
512 sizeof(kn02ba_asic_mask_nr_tbl));
513
514 mips_cpu_irq_init();
515 init_ioasic_irqs(IO_IRQ_BASE);
516
517 } /* dec_init_kn02ba */
518
519
520 /*
521 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
522 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
523 * DS5000/50, aka 4MAXine.
524 */
525 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
526 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
527 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
528 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
529 [DEC_IRQ_DZ11] = -1,
530 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
531 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
532 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
533 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
534 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
535 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
536 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
537 [DEC_IRQ_PSU] = -1,
538 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
539 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
540 [DEC_IRQ_SCC1] = -1,
541 [DEC_IRQ_SII] = -1,
542 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
543 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
544 [DEC_IRQ_TC2] = -1,
545 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
546 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
547 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
548 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
549 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
550 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
551 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
552 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
553 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
554 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
555 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
556 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
557 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
558 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
559 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
560 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
561 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
562 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
563 [DEC_IRQ_SCC1A_RXERR] = -1,
564 [DEC_IRQ_SCC1A_RXDMA] = -1,
565 [DEC_IRQ_SCC1A_TXERR] = -1,
566 [DEC_IRQ_SCC1A_TXDMA] = -1,
567 };
568
569 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
570 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
571 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
572 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
573 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
574 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
575 { .p = kn02xa_io_int } },
576 { { .i = DEC_CPU_IRQ_ALL },
577 { .p = cpu_all_int } },
578 };
579
580 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
581 { { .i = IO_IRQ_DMA },
582 { .p = asic_dma_int } },
583 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
584 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
585 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
586 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
587 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
588 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
589 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
590 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
591 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
592 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
593 { { .i = IO_IRQ_ALL },
594 { .p = asic_all_int } },
595 };
596
597 static void __init dec_init_kn02ca(void)
598 {
599 /* IRQ routing. */
600 memcpy(&dec_interrupt, &kn02ca_interrupt,
601 sizeof(kn02ca_interrupt));
602
603 /* CPU IRQ priorities. */
604 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
605 sizeof(kn02ca_cpu_mask_nr_tbl));
606
607 /* I/O ASIC IRQ priorities. */
608 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
609 sizeof(kn02ca_asic_mask_nr_tbl));
610
611 mips_cpu_irq_init();
612 init_ioasic_irqs(IO_IRQ_BASE);
613
614 } /* dec_init_kn02ca */
615
616
617 /*
618 * Machine-specific initialisation for KN03, aka DS5000/240,
619 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
620 * DS5000/260, aka 4max+ and DS5900/260.
621 */
622 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
623 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
624 [DEC_IRQ_AB_RECV] = -1,
625 [DEC_IRQ_AB_XMIT] = -1,
626 [DEC_IRQ_DZ11] = -1,
627 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
628 [DEC_IRQ_FLOPPY] = -1,
629 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
630 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
631 [DEC_IRQ_ISDN] = -1,
632 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
633 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
634 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
635 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
636 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
637 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
638 [DEC_IRQ_SII] = -1,
639 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
640 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
641 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
642 [DEC_IRQ_TIMER] = -1,
643 [DEC_IRQ_VIDEO] = -1,
644 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
645 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
646 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
647 [DEC_IRQ_FLOPPY_ERR] = -1,
648 [DEC_IRQ_ISDN_ERR] = -1,
649 [DEC_IRQ_ISDN_RXDMA] = -1,
650 [DEC_IRQ_ISDN_TXDMA] = -1,
651 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
652 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
653 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
654 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
655 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
656 [DEC_IRQ_AB_RXERR] = -1,
657 [DEC_IRQ_AB_RXDMA] = -1,
658 [DEC_IRQ_AB_TXERR] = -1,
659 [DEC_IRQ_AB_TXDMA] = -1,
660 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
661 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
662 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
663 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
664 };
665
666 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
667 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
668 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
669 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
670 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
671 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
672 { .p = kn03_io_int } },
673 { { .i = DEC_CPU_IRQ_ALL },
674 { .p = cpu_all_int } },
675 };
676
677 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
678 { { .i = IO_IRQ_DMA },
679 { .p = asic_dma_int } },
680 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
681 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
682 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
683 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
684 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
685 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
686 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
687 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
688 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
689 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
690 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
691 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
692 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
693 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
694 { { .i = IO_IRQ_ALL },
695 { .p = asic_all_int } },
696 };
697
698 static void __init dec_init_kn03(void)
699 {
700 /* IRQ routing. */
701 memcpy(&dec_interrupt, &kn03_interrupt,
702 sizeof(kn03_interrupt));
703
704 /* CPU IRQ priorities. */
705 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
706 sizeof(kn03_cpu_mask_nr_tbl));
707
708 /* I/O ASIC IRQ priorities. */
709 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
710 sizeof(kn03_asic_mask_nr_tbl));
711
712 mips_cpu_irq_init();
713 init_ioasic_irqs(IO_IRQ_BASE);
714
715 } /* dec_init_kn03 */
716
717
718 void __init arch_init_irq(void)
719 {
720 switch (mips_machtype) {
721 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
722 dec_init_kn01();
723 break;
724 case MACH_DS5100: /* DS5100 MIPSmate */
725 dec_init_kn230();
726 break;
727 case MACH_DS5000_200: /* DS5000/200 3max */
728 dec_init_kn02();
729 break;
730 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
731 dec_init_kn02ba();
732 break;
733 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
734 case MACH_DS5900: /* DS5900 bigmax */
735 dec_init_kn03();
736 break;
737 case MACH_DS5000_XX: /* Personal DS5000/xx */
738 dec_init_kn02ca();
739 break;
740 case MACH_DS5800: /* DS5800 Isis */
741 panic("Don't know how to set this up!");
742 break;
743 case MACH_DS5400: /* DS5400 MIPSfair */
744 panic("Don't know how to set this up!");
745 break;
746 case MACH_DS5500: /* DS5500 MIPSfair-2 */
747 panic("Don't know how to set this up!");
748 break;
749 }
750
751 /* Free the FPU interrupt if the exception is present. */
752 if (!cpu_has_nofpuex) {
753 cpu_fpu_mask = 0;
754 dec_interrupt[DEC_IRQ_FPU] = -1;
755 }
756 /* Free the halt interrupt unused on R4k systems. */
757 if (current_cpu_type() == CPU_R4000SC ||
758 current_cpu_type() == CPU_R4400SC)
759 dec_interrupt[DEC_IRQ_HALT] = -1;
760
761 /* Register board interrupts: FPU and cascade. */
762 if (dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
763 struct irq_desc *desc_fpu;
764 int irq_fpu;
765
766 irq_fpu = dec_interrupt[DEC_IRQ_FPU];
767 setup_irq(irq_fpu, &fpuirq);
768 desc_fpu = irq_to_desc(irq_fpu);
769 fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
770 }
771 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
772 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
773
774 /* Register the bus error interrupt. */
775 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
776 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
777
778 /* Register the HALT interrupt. */
779 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
780 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
781 }
782
783 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
784 {
785 do_IRQ(irq);
786 return 0;
787 }
Linux with added FPC-III support