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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / arch / mips / include / asm / io.h
blobcf1f2a4a241898317d1c622a9af115e914bad4f4
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #define ARCH_HAS_IOREMAP_WC
16
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/irqflags.h>
21
22 #include <asm/addrspace.h>
23 #include <asm/barrier.h>
24 #include <asm/bug.h>
25 #include <asm/byteorder.h>
26 #include <asm/cpu.h>
27 #include <asm/cpu-features.h>
28 #include <asm-generic/iomap.h>
29 #include <asm/page.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/processor.h>
32 #include <asm/string.h>
33
34 #include <ioremap.h>
35 #include <mangle-port.h>
36
37 /*
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
41 * execute in place.
42 */
43 # define __raw_ioswabb(a, x) (x)
44 # define __raw_ioswabw(a, x) (x)
45 # define __raw_ioswabl(a, x) (x)
46 # define __raw_ioswabq(a, x) (x)
47 # define ____raw_ioswabq(a, x) (x)
48
49 # define __relaxed_ioswabb ioswabb
50 # define __relaxed_ioswabw ioswabw
51 # define __relaxed_ioswabl ioswabl
52 # define __relaxed_ioswabq ioswabq
53
54 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
55
56 #define IO_SPACE_LIMIT 0xffff
57
58 /*
59 * On MIPS I/O ports are memory mapped, so we access them using normal
60 * load/store instructions. mips_io_port_base is the virtual address to
61 * which all ports are being mapped. For sake of efficiency some code
62 * assumes that this is an address that can be loaded with a single lui
63 * instruction, so the lower 16 bits must be zero. Should be true on
64 * on any sane architecture; generic code does not use this assumption.
65 */
66 extern unsigned long mips_io_port_base;
67
68 static inline void set_io_port_base(unsigned long base)
69 {
70 mips_io_port_base = base;
71 }
72
73 /*
74 * Provide the necessary definitions for generic iomap. We make use of
75 * mips_io_port_base for iomap(), but we don't reserve any low addresses for
76 * use with I/O ports.
77 */
78
79 #define HAVE_ARCH_PIO_SIZE
80 #define PIO_OFFSET mips_io_port_base
81 #define PIO_MASK IO_SPACE_LIMIT
82 #define PIO_RESERVED 0x0UL
83
84 /*
85 * Enforce in-order execution of data I/O. In the MIPS architecture
86 * these are equivalent to corresponding platform-specific memory
87 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
88 * with sync additionally defined.
89 */
90 #define iobarrier_rw() mb()
91 #define iobarrier_r() rmb()
92 #define iobarrier_w() wmb()
93 #define iobarrier_sync() iob()
94
95 /*
96 * virt_to_phys - map virtual addresses to physical
97 * @address: address to remap
98 *
99 * The returned physical address is the physical (CPU) mapping for
100 * the memory address given. It is only valid to use this function on
101 * addresses directly mapped or allocated via kmalloc.
102 *
103 * This function does not give bus mappings for DMA transfers. In
104 * almost all conceivable cases a device driver should not be using
105 * this function
106 */
107 static inline unsigned long virt_to_phys(volatile const void *address)
108 {
109 return __pa(address);
110 }
111
112 /*
113 * phys_to_virt - map physical address to virtual
114 * @address: address to remap
115 *
116 * The returned virtual address is a current CPU mapping for
117 * the memory address given. It is only valid to use this function on
118 * addresses that have a kernel mapping
119 *
120 * This function does not handle bus mappings for DMA transfers. In
121 * almost all conceivable cases a device driver should not be using
122 * this function
123 */
124 static inline void * phys_to_virt(unsigned long address)
125 {
126 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
127 }
128
129 /*
130 * ISA I/O bus memory addresses are 1:1 with the physical address.
131 */
132 static inline unsigned long isa_virt_to_bus(volatile void *address)
133 {
134 return virt_to_phys(address);
135 }
136
137 static inline void *isa_bus_to_virt(unsigned long address)
138 {
139 return phys_to_virt(address);
140 }
141
142 /*
143 * However PCI ones are not necessarily 1:1 and therefore these interfaces
144 * are forbidden in portable PCI drivers.
145 *
146 * Allow them for x86 for legacy drivers, though.
147 */
148 #define virt_to_bus virt_to_phys
149 #define bus_to_virt phys_to_virt
150
151 /*
152 * Change "struct page" to physical address.
153 */
154 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
155
156 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
157 extern void __iounmap(const volatile void __iomem *addr);
158
159 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
160 unsigned long flags)
161 {
162 void __iomem *addr = plat_ioremap(offset, size, flags);
163
164 if (addr)
165 return addr;
166
167 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
168
169 if (cpu_has_64bit_addresses) {
170 u64 base = UNCAC_BASE;
171
172 /*
173 * R10000 supports a 2 bit uncached attribute therefore
174 * UNCAC_BASE may not equal IO_BASE.
175 */
176 if (flags == _CACHE_UNCACHED)
177 base = (u64) IO_BASE;
178 return (void __iomem *) (unsigned long) (base + offset);
179 } else if (__builtin_constant_p(offset) &&
180 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
181 phys_addr_t phys_addr, last_addr;
182
183 phys_addr = fixup_bigphys_addr(offset, size);
184
185 /* Don't allow wraparound or zero size. */
186 last_addr = phys_addr + size - 1;
187 if (!size || last_addr < phys_addr)
188 return NULL;
189
190 /*
191 * Map uncached objects in the low 512MB of address
192 * space using KSEG1.
193 */
194 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
195 flags == _CACHE_UNCACHED)
196 return (void __iomem *)
197 (unsigned long)CKSEG1ADDR(phys_addr);
198 }
199
200 return __ioremap(offset, size, flags);
201
202 #undef __IS_LOW512
203 }
204
205 /*
206 * ioremap_prot - map bus memory into CPU space
207 * @offset: bus address of the memory
208 * @size: size of the resource to map
209
210 * ioremap_prot gives the caller control over cache coherency attributes (CCA)
211 */
212 static inline void __iomem *ioremap_prot(phys_addr_t offset,
213 unsigned long size, unsigned long prot_val) {
214 return __ioremap_mode(offset, size, prot_val & _CACHE_MASK);
215 }
216
217 /*
218 * ioremap - map bus memory into CPU space
219 * @offset: bus address of the memory
220 * @size: size of the resource to map
221 *
222 * ioremap performs a platform specific sequence of operations to
223 * make bus memory CPU accessible via the readb/readw/readl/writeb/
224 * writew/writel functions and the other mmio helpers. The returned
225 * address is not guaranteed to be usable directly as a virtual
226 * address.
227 */
228 #define ioremap(offset, size) \
229 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
230 #define ioremap_uc ioremap
231
232 /*
233 * ioremap_cache - map bus memory into CPU space
234 * @offset: bus address of the memory
235 * @size: size of the resource to map
236 *
237 * ioremap_cache performs a platform specific sequence of operations to
238 * make bus memory CPU accessible via the readb/readw/readl/writeb/
239 * writew/writel functions and the other mmio helpers. The returned
240 * address is not guaranteed to be usable directly as a virtual
241 * address.
242 *
243 * This version of ioremap ensures that the memory is marked cachable by
244 * the CPU. Also enables full write-combining. Useful for some
245 * memory-like regions on I/O busses.
246 */
247 #define ioremap_cache(offset, size) \
248 __ioremap_mode((offset), (size), _page_cachable_default)
249
250 /*
251 * ioremap_wc - map bus memory into CPU space
252 * @offset: bus address of the memory
253 * @size: size of the resource to map
254 *
255 * ioremap_wc performs a platform specific sequence of operations to
256 * make bus memory CPU accessible via the readb/readw/readl/writeb/
257 * writew/writel functions and the other mmio helpers. The returned
258 * address is not guaranteed to be usable directly as a virtual
259 * address.
260 *
261 * This version of ioremap ensures that the memory is marked uncachable
262 * but accelerated by means of write-combining feature. It is specifically
263 * useful for PCIe prefetchable windows, which may vastly improve a
264 * communications performance. If it was determined on boot stage, what
265 * CPU CCA doesn't support UCA, the method shall fall-back to the
266 * _CACHE_UNCACHED option (see cpu_probe() method).
267 */
268 #define ioremap_wc(offset, size) \
269 __ioremap_mode((offset), (size), boot_cpu_data.writecombine)
270
271 static inline void iounmap(const volatile void __iomem *addr)
272 {
273 if (plat_iounmap(addr))
274 return;
275
276 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
277
278 if (cpu_has_64bit_addresses ||
279 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
280 return;
281
282 __iounmap(addr);
283
284 #undef __IS_KSEG1
285 }
286
287 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
288 #define war_io_reorder_wmb() wmb()
289 #else
290 #define war_io_reorder_wmb() barrier()
291 #endif
292
293 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
294 \
295 static inline void pfx##write##bwlq(type val, \
296 volatile void __iomem *mem) \
297 { \
298 volatile type *__mem; \
299 type __val; \
300 \
301 if (barrier) \
302 iobarrier_rw(); \
303 else \
304 war_io_reorder_wmb(); \
305 \
306 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
307 \
308 __val = pfx##ioswab##bwlq(__mem, val); \
309 \
310 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
311 *__mem = __val; \
312 else if (cpu_has_64bits) { \
313 unsigned long __flags; \
314 type __tmp; \
315 \
316 if (irq) \
317 local_irq_save(__flags); \
318 __asm__ __volatile__( \
319 ".set push" "\t\t# __writeq""\n\t" \
320 ".set arch=r4000" "\n\t" \
321 "dsll32 %L0, %L0, 0" "\n\t" \
322 "dsrl32 %L0, %L0, 0" "\n\t" \
323 "dsll32 %M0, %M0, 0" "\n\t" \
324 "or %L0, %L0, %M0" "\n\t" \
325 "sd %L0, %2" "\n\t" \
326 ".set pop" "\n" \
327 : "=r" (__tmp) \
328 : "0" (__val), "m" (*__mem)); \
329 if (irq) \
330 local_irq_restore(__flags); \
331 } else \
332 BUG(); \
333 } \
334 \
335 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
336 { \
337 volatile type *__mem; \
338 type __val; \
339 \
340 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
341 \
342 if (barrier) \
343 iobarrier_rw(); \
344 \
345 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
346 __val = *__mem; \
347 else if (cpu_has_64bits) { \
348 unsigned long __flags; \
349 \
350 if (irq) \
351 local_irq_save(__flags); \
352 __asm__ __volatile__( \
353 ".set push" "\t\t# __readq" "\n\t" \
354 ".set arch=r4000" "\n\t" \
355 "ld %L0, %1" "\n\t" \
356 "dsra32 %M0, %L0, 0" "\n\t" \
357 "sll %L0, %L0, 0" "\n\t" \
358 ".set pop" "\n" \
359 : "=r" (__val) \
360 : "m" (*__mem)); \
361 if (irq) \
362 local_irq_restore(__flags); \
363 } else { \
364 __val = 0; \
365 BUG(); \
366 } \
367 \
368 /* prevent prefetching of coherent DMA data prematurely */ \
369 if (!relax) \
370 rmb(); \
371 return pfx##ioswab##bwlq(__mem, __val); \
372 }
373
374 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
375 \
376 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
377 { \
378 volatile type *__addr; \
379 type __val; \
380 \
381 if (barrier) \
382 iobarrier_rw(); \
383 else \
384 war_io_reorder_wmb(); \
385 \
386 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
387 \
388 __val = pfx##ioswab##bwlq(__addr, val); \
389 \
390 /* Really, we want this to be atomic */ \
391 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
392 \
393 *__addr = __val; \
394 } \
395 \
396 static inline type pfx##in##bwlq##p(unsigned long port) \
397 { \
398 volatile type *__addr; \
399 type __val; \
400 \
401 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
402 \
403 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
404 \
405 if (barrier) \
406 iobarrier_rw(); \
407 \
408 __val = *__addr; \
409 \
410 /* prevent prefetching of coherent DMA data prematurely */ \
411 if (!relax) \
412 rmb(); \
413 return pfx##ioswab##bwlq(__addr, __val); \
414 }
415
416 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
417 \
418 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
419
420 #define BUILDIO_MEM(bwlq, type) \
421 \
422 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
423 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
424 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
425 __BUILD_MEMORY_PFX(, bwlq, type, 0)
426
427 BUILDIO_MEM(b, u8)
428 BUILDIO_MEM(w, u16)
429 BUILDIO_MEM(l, u32)
430 #ifdef CONFIG_64BIT
431 BUILDIO_MEM(q, u64)
432 #else
433 __BUILD_MEMORY_PFX(__raw_, q, u64, 0)
434 __BUILD_MEMORY_PFX(__mem_, q, u64, 0)
435 #endif
436
437 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
438 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
439 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
440
441 #define BUILDIO_IOPORT(bwlq, type) \
442 __BUILD_IOPORT_PFX(, bwlq, type) \
443 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
444
445 BUILDIO_IOPORT(b, u8)
446 BUILDIO_IOPORT(w, u16)
447 BUILDIO_IOPORT(l, u32)
448 #ifdef CONFIG_64BIT
449 BUILDIO_IOPORT(q, u64)
450 #endif
451
452 #define __BUILDIO(bwlq, type) \
453 \
454 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
455
456 __BUILDIO(q, u64)
457
458 #define readb_relaxed __relaxed_readb
459 #define readw_relaxed __relaxed_readw
460 #define readl_relaxed __relaxed_readl
461 #ifdef CONFIG_64BIT
462 #define readq_relaxed __relaxed_readq
463 #endif
464
465 #define writeb_relaxed __relaxed_writeb
466 #define writew_relaxed __relaxed_writew
467 #define writel_relaxed __relaxed_writel
468 #ifdef CONFIG_64BIT
469 #define writeq_relaxed __relaxed_writeq
470 #endif
471
472 #define readb_be(addr) \
473 __raw_readb((__force unsigned *)(addr))
474 #define readw_be(addr) \
475 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
476 #define readl_be(addr) \
477 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
478 #define readq_be(addr) \
479 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
480
481 #define writeb_be(val, addr) \
482 __raw_writeb((val), (__force unsigned *)(addr))
483 #define writew_be(val, addr) \
484 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
485 #define writel_be(val, addr) \
486 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
487 #define writeq_be(val, addr) \
488 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
489
490 /*
491 * Some code tests for these symbols
492 */
493 #ifdef CONFIG_64BIT
494 #define readq readq
495 #define writeq writeq
496 #endif
497
498 #define __BUILD_MEMORY_STRING(bwlq, type) \
499 \
500 static inline void writes##bwlq(volatile void __iomem *mem, \
501 const void *addr, unsigned int count) \
502 { \
503 const volatile type *__addr = addr; \
504 \
505 while (count--) { \
506 __mem_write##bwlq(*__addr, mem); \
507 __addr++; \
508 } \
509 } \
510 \
511 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
512 unsigned int count) \
513 { \
514 volatile type *__addr = addr; \
515 \
516 while (count--) { \
517 *__addr = __mem_read##bwlq(mem); \
518 __addr++; \
519 } \
520 }
521
522 #define __BUILD_IOPORT_STRING(bwlq, type) \
523 \
524 static inline void outs##bwlq(unsigned long port, const void *addr, \
525 unsigned int count) \
526 { \
527 const volatile type *__addr = addr; \
528 \
529 while (count--) { \
530 __mem_out##bwlq(*__addr, port); \
531 __addr++; \
532 } \
533 } \
534 \
535 static inline void ins##bwlq(unsigned long port, void *addr, \
536 unsigned int count) \
537 { \
538 volatile type *__addr = addr; \
539 \
540 while (count--) { \
541 *__addr = __mem_in##bwlq(port); \
542 __addr++; \
543 } \
544 }
545
546 #define BUILDSTRING(bwlq, type) \
547 \
548 __BUILD_MEMORY_STRING(bwlq, type) \
549 __BUILD_IOPORT_STRING(bwlq, type)
550
551 BUILDSTRING(b, u8)
552 BUILDSTRING(w, u16)
553 BUILDSTRING(l, u32)
554 #ifdef CONFIG_64BIT
555 BUILDSTRING(q, u64)
556 #endif
557
558 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
559 {
560 memset((void __force *) addr, val, count);
561 }
562 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
563 {
564 memcpy(dst, (void __force *) src, count);
565 }
566 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
567 {
568 memcpy((void __force *) dst, src, count);
569 }
570
571 /*
572 * The caches on some architectures aren't dma-coherent and have need to
573 * handle this in software. There are three types of operations that
574 * can be applied to dma buffers.
575 *
576 * - dma_cache_wback_inv(start, size) makes caches and coherent by
577 * writing the content of the caches back to memory, if necessary.
578 * The function also invalidates the affected part of the caches as
579 * necessary before DMA transfers from outside to memory.
580 * - dma_cache_wback(start, size) makes caches and coherent by
581 * writing the content of the caches back to memory, if necessary.
582 * The function also invalidates the affected part of the caches as
583 * necessary before DMA transfers from outside to memory.
584 * - dma_cache_inv(start, size) invalidates the affected parts of the
585 * caches. Dirty lines of the caches may be written back or simply
586 * be discarded. This operation is necessary before dma operations
587 * to the memory.
588 *
589 * This API used to be exported; it now is for arch code internal use only.
590 */
591 #ifdef CONFIG_DMA_NONCOHERENT
592
593 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
594 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
595 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
596
597 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
598 #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
599 #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
600
601 #else /* Sane hardware */
602
603 #define dma_cache_wback_inv(start,size) \
604 do { (void) (start); (void) (size); } while (0)
605 #define dma_cache_wback(start,size) \
606 do { (void) (start); (void) (size); } while (0)
607 #define dma_cache_inv(start,size) \
608 do { (void) (start); (void) (size); } while (0)
609
610 #endif /* CONFIG_DMA_NONCOHERENT */
611
612 /*
613 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
614 * Avoid interrupt mucking, just adjust the address for 4-byte access.
615 * Assume the addresses are 8-byte aligned.
616 */
617 #ifdef __MIPSEB__
618 #define __CSR_32_ADJUST 4
619 #else
620 #define __CSR_32_ADJUST 0
621 #endif
622
623 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
624 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
625
626 /*
627 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
628 * access
629 */
630 #define xlate_dev_mem_ptr(p) __va(p)
631
632 /*
633 * Convert a virtual cached pointer to an uncached pointer
634 */
635 #define xlate_dev_kmem_ptr(p) p
636
637 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
638
639 #endif /* _ASM_IO_H */
Linux with added FPC-III support