1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 IRQ definitions
7 #ifndef __ASM_MACH_JZ4740_IRQ_H__
8 #define __ASM_MACH_JZ4740_IRQ_H__
10 #define MIPS_CPU_IRQ_BASE 0
11 #define JZ4740_IRQ_BASE 8
13 #ifdef CONFIG_MACH_JZ4740
14 # define NR_INTC_IRQS 32
16 # define NR_INTC_IRQS 64
19 /* 1st-level interrupts */
20 #define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
21 #define JZ4740_IRQ_I2C JZ4740_IRQ(1)
22 #define JZ4740_IRQ_UHC JZ4740_IRQ(3)
23 #define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
24 #define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
25 #define JZ4740_IRQ_SADC JZ4740_IRQ(12)
26 #define JZ4740_IRQ_MSC JZ4740_IRQ(14)
27 #define JZ4740_IRQ_RTC JZ4740_IRQ(15)
28 #define JZ4740_IRQ_SSI JZ4740_IRQ(16)
29 #define JZ4740_IRQ_CIM JZ4740_IRQ(17)
30 #define JZ4740_IRQ_AIC JZ4740_IRQ(18)
31 #define JZ4740_IRQ_ETH JZ4740_IRQ(19)
32 #define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
33 #define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
34 #define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
35 #define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
36 #define JZ4740_IRQ_UDC JZ4740_IRQ(24)
37 #define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
38 #define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
39 #define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
40 #define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
41 #define JZ4740_IRQ_IPU JZ4740_IRQ(29)
42 #define JZ4740_IRQ_LCD JZ4740_IRQ(30)
44 #define JZ4780_IRQ_TCU2 JZ4740_IRQ(25)
46 /* 2nd-level interrupts */
47 #define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
49 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
50 #define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
52 #define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
54 #define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)