arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /******************************************************************
   3  * Copyright (c) 2000-2007 PMC-Sierra INC.
   4  *
   5  * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
   6  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
   7  * SOFTWARE.
   8  */
   9 #ifndef MSP_USB_H_
  10 #define MSP_USB_H_
  11
  12 #define NUM_USB_DEVS   1
  13
  14 /* Register spaces for USB host 0 */
  15 #define MSP_USB0_MAB_START      (MSP_USB0_BASE + 0x0)
  16 #define MSP_USB0_MAB_END        (MSP_USB0_BASE + 0x17)
  17 #define MSP_USB0_ID_START       (MSP_USB0_BASE + 0x40000)
  18 #define MSP_USB0_ID_END         (MSP_USB0_BASE + 0x4008f)
  19 #define MSP_USB0_HS_START       (MSP_USB0_BASE + 0x40100)
  20 #define MSP_USB0_HS_END         (MSP_USB0_BASE + 0x401FF)
  21
  22 /* Register spaces for USB host 1 */
  23 #define MSP_USB1_MAB_START      (MSP_USB1_BASE + 0x0)
  24 #define MSP_USB1_MAB_END        (MSP_USB1_BASE + 0x17)
  25 #define MSP_USB1_ID_START       (MSP_USB1_BASE + 0x40000)
  26 #define MSP_USB1_ID_END         (MSP_USB1_BASE + 0x4008f)
  27 #define MSP_USB1_HS_START       (MSP_USB1_BASE + 0x40100)
  28 #define MSP_USB1_HS_END         (MSP_USB1_BASE + 0x401ff)
  29
  30 /* USB Identification registers */
  31 struct msp_usbid_regs {
  32         u32 id;         /* 0x0: Identification register */
  33         u32 hwgen;      /* 0x4: General HW params */
  34         u32 hwhost;     /* 0x8: Host HW params */
  35         u32 hwdev;      /* 0xc: Device HW params */
  36         u32 hwtxbuf;    /* 0x10: Tx buffer HW params */
  37         u32 hwrxbuf;    /* 0x14: Rx buffer HW params */
  38         u32 reserved[26];
  39         u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
  40         u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
  41         u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
  42         u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
  43 };
  44
  45 /* MSBus to AMBA registers */
  46 struct msp_mab_regs {
  47         u32 isr;        /* 0x0: Interrupt status */
  48         u32 imr;        /* 0x4: Interrupt mask */
  49         u32 thcr0;      /* 0x8: Transaction header capture 0 */
  50         u32 thcr1;      /* 0xc: Transaction header capture 1 */
  51         u32 int_stat;   /* 0x10: Interrupt status summary */
  52         u32 phy_cfg;    /* 0x14: USB phy config */
  53 };
  54
  55 /* EHCI registers */
  56 struct msp_usbhs_regs {
  57         u32 hciver;     /* 0x0: Version and offset to operational regs */
  58         u32 hcsparams;  /* 0x4: Host control structural parameters */
  59         u32 hccparams;  /* 0x8: Host control capability parameters */
  60         u32 reserved0[5];
  61         u32 dciver;     /* 0x20: Device interface version */
  62         u32 dccparams;  /* 0x24: Device control capability parameters */
  63         u32 reserved1[6];
  64         u32 cmd;        /* 0x40: USB command */
  65         u32 sts;        /* 0x44: USB status */
  66         u32 int_ena;    /* 0x48: USB interrupt enable */
  67         u32 frindex;    /* 0x4c: Frame index */
  68         u32 reserved3;
  69         union {
  70                 struct {
  71                         u32 flb_addr; /* 0x54: Frame list base address */
  72                         u32 next_async_addr; /* 0x58: next asynchronous addr */
  73                         u32 ttctrl; /* 0x5c: embedded transaction translator
  74                                                         async buffer status */
  75                         u32 burst_size; /* 0x60: Controller burst size */
  76                         u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
  77                         u32 reserved0[4];
  78                         u32 endpt_nak; /* 0x78: Endpoint NAK */
  79                         u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
  80                         u32 cfg_flag; /* 0x80: Config flag */
  81                         u32 port_sc1; /* 0x84: Port status & control 1 */
  82                         u32 reserved1[7];
  83                         u32 otgsc;      /* 0xa4: OTG status & control */
  84                         u32 mode;       /* 0xa8: USB controller mode */
  85                 } host;
  86
  87                 struct {
  88                         u32 dev_addr; /* 0x54: Device address */
  89                         u32 endpt_list_addr; /* 0x58: Endpoint list address */
  90                         u32 reserved0[7];
  91                         u32 endpt_nak;  /* 0x74 */
  92                         u32 endpt_nak_ctrl; /* 0x78 */
  93                         u32 cfg_flag; /* 0x80 */
  94                         u32 port_sc1; /* 0x84: Port status & control 1 */
  95                         u32 reserved[7];
  96                         u32 otgsc;      /* 0xa4: OTG status & control */
  97                         u32 mode;       /* 0xa8: USB controller mode */
  98                         u32 endpt_setup_stat; /* 0xac */
  99                         u32 endpt_prime; /* 0xb0 */
 100                         u32 endpt_flush; /* 0xb4 */
 101                         u32 endpt_stat; /* 0xb8 */
 102                         u32 endpt_complete; /* 0xbc */
 103                         u32 endpt_ctrl0; /* 0xc0 */
 104                         u32 endpt_ctrl1; /* 0xc4 */
 105                         u32 endpt_ctrl2; /* 0xc8 */
 106                         u32 endpt_ctrl3; /* 0xcc */
 107                 } device;
 108         } u;
 109 };
 110 /*
 111  * Container for the more-generic platform_device.
 112  * This exists mainly as a way to map the non-standard register
 113  * spaces and make them accessible to the USB ISR.
 114  */
 115 struct mspusb_device {
 116         struct msp_mab_regs   __iomem *mab_regs;
 117         struct msp_usbid_regs __iomem *usbid_regs;
 118         struct msp_usbhs_regs __iomem *usbhs_regs;
 119         struct platform_device dev;
 120 };
 121
 122 #define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
 123 #define TO_HOST_ID(x) ((x) & 0x3)
 124 #endif /*MSP_USB_H_*/