arch/mips/include/asm/mach-pnx833x/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  gpio.h: GPIO Support for PNX833X.
   4  *
   5  *  Copyright 2008 NXP Semiconductors
   6  *        Chris Steel <chris.steel@nxp.com>
   7  *    Daniel Laird <daniel.j.laird@nxp.com>
   8  */
   9 #ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
  10 #define __ASM_MIPS_MACH_PNX833X_GPIO_H
  11
  12 /* BIG FAT WARNING: races danger!
  13    No protections exist here. Current users are only early init code,
  14    when locking is not needed because no concurrency yet exists there,
  15    and GPIO IRQ dispatcher, which does locking.
  16    However, if many uses will ever happen, proper locking will be needed
  17    - including locking between different uses
  18 */
  19
  20 #include <asm/mach-pnx833x/pnx833x.h>
  21
  22 #define SET_REG_BIT(reg, bit)           do { (reg |= (1 << (bit))); } while (0)
  23 #define CLEAR_REG_BIT(reg, bit)         do { (reg &= ~(1 << (bit))); } while (0)
  24
  25 /* Initialize GPIO to a known state */
  26 static inline void pnx833x_gpio_init(void)
  27 {
  28         PNX833X_PIO_DIR = 0;
  29         PNX833X_PIO_DIR2 = 0;
  30         PNX833X_PIO_SEL = 0;
  31         PNX833X_PIO_SEL2 = 0;
  32         PNX833X_PIO_INT_EDGE = 0;
  33         PNX833X_PIO_INT_HI = 0;
  34         PNX833X_PIO_INT_LO = 0;
  35
  36         /* clear any GPIO interrupt requests */
  37         PNX833X_PIO_INT_CLEAR = 0xffff;
  38         PNX833X_PIO_INT_CLEAR = 0;
  39         PNX833X_PIO_INT_ENABLE = 0;
  40 }
  41
  42 /* Select GPIO direction for a pin */
  43 static inline void pnx833x_gpio_select_input(unsigned int pin)
  44 {
  45         if (pin < 32)
  46                 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
  47         else
  48                 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  49 }
  50 static inline void pnx833x_gpio_select_output(unsigned int pin)
  51 {
  52         if (pin < 32)
  53                 SET_REG_BIT(PNX833X_PIO_DIR, pin);
  54         else
  55                 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  56 }
  57
  58 /* Select GPIO or alternate function for a pin */
  59 static inline void pnx833x_gpio_select_function_io(unsigned int pin)
  60 {
  61         if (pin < 32)
  62                 CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
  63         else
  64                 CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  65 }
  66 static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
  67 {
  68         if (pin < 32)
  69                 SET_REG_BIT(PNX833X_PIO_SEL, pin);
  70         else
  71                 SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  72 }
  73
  74 /* Read GPIO pin */
  75 static inline int pnx833x_gpio_read(unsigned int pin)
  76 {
  77         if (pin < 32)
  78                 return (PNX833X_PIO_IN >> pin) & 1;
  79         else
  80                 return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
  81 }
  82
  83 /* Write GPIO pin */
  84 static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
  85 {
  86         if (pin < 32) {
  87                 if (val)
  88                         SET_REG_BIT(PNX833X_PIO_OUT, pin);
  89                 else
  90                         CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
  91         } else {
  92                 if (val)
  93                         SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  94                 else
  95                         CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  96         }
  97 }
  98
  99 /* Configure GPIO interrupt */
 100 #define GPIO_INT_NONE           0
 101 #define GPIO_INT_LEVEL_LOW      1
 102 #define GPIO_INT_LEVEL_HIGH     2
 103 #define GPIO_INT_EDGE_RISING    3
 104 #define GPIO_INT_EDGE_FALLING   4
 105 #define GPIO_INT_EDGE_BOTH      5
 106 static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
 107 {
 108         switch (when) {
 109         case GPIO_INT_LEVEL_LOW:
 110                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 111                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 112                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 113                 break;
 114         case GPIO_INT_LEVEL_HIGH:
 115                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 116                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 117                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 118                 break;
 119         case GPIO_INT_EDGE_RISING:
 120                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 121                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 122                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 123                 break;
 124         case GPIO_INT_EDGE_FALLING:
 125                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 126                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 127                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 128                 break;
 129         case GPIO_INT_EDGE_BOTH:
 130                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 131                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 132                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 133                 break;
 134         default:
 135                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 136                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 137                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 138                 break;
 139         }
 140 }
 141
 142 /* Enable/disable GPIO interrupt */
 143 static inline void pnx833x_gpio_enable_irq(unsigned int pin)
 144 {
 145         SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
 146 }
 147 static inline void pnx833x_gpio_disable_irq(unsigned int pin)
 148 {
 149         CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
 150 }
 151
 152 /* Clear GPIO interrupt request */
 153 static inline void pnx833x_gpio_clear_irq(unsigned int pin)
 154 {
 155         SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
 156         CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
 157 }
 158
 159 #endif