arch/mips/include/asm/mach-pnx833x/irq.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  irq.h: IRQ mappings for PNX833X.
   4  *
   5  *  Copyright 2008 NXP Semiconductors
   6  *        Chris Steel <chris.steel@nxp.com>
   7  *    Daniel Laird <daniel.j.laird@nxp.com>
   8  */
   9
  10 #ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
  11 #define __ASM_MIPS_MACH_PNX833X_IRQ_H
  12 /*
  13  * The "IRQ numbers" are completely virtual.
  14  *
  15  * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
  16  * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
  17  * numbers 49..64 for (virtual) GPIO interrupts.
  18  *
  19  * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
  20  * connected to PIC, which uses core hardware interrupt 2, and also
  21  * a timer interrupt through hardware interrupt 5.
  22  * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
  23  * numbers 65..80 for (virtual) GPIO interrupts.
  24  *
  25  */
  26 #if defined(CONFIG_SOC_PNX8335)
  27         #define PNX833X_PIC_NUM_IRQ                     58
  28 #else
  29         #define PNX833X_PIC_NUM_IRQ                     37
  30 #endif
  31
  32 #define MIPS_CPU_NUM_IRQ                                8
  33 #define PNX833X_GPIO_NUM_IRQ                    16
  34
  35 #define MIPS_CPU_IRQ_BASE                               0
  36 #define PNX833X_PIC_IRQ_BASE                    (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
  37 #define PNX833X_GPIO_IRQ_BASE                   (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
  38 #define NR_IRQS                                                 (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
  39
  40 #endif