arch/mips/include/asm/mach-ralink/mt7620.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *
   4  * Parts of this file are based on Ralink's 2.6.21 BSP
   5  *
   6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   7  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2013 John Crispin <john@phrozen.org>
   9  */
  10
  11 #ifndef _MT7620_REGS_H_
  12 #define _MT7620_REGS_H_
  13
  14 #define MT7620_SYSC_BASE                0x10000000
  15
  16 #define SYSC_REG_CHIP_NAME0             0x00
  17 #define SYSC_REG_CHIP_NAME1             0x04
  18 #define SYSC_REG_EFUSE_CFG              0x08
  19 #define SYSC_REG_CHIP_REV               0x0c
  20 #define SYSC_REG_SYSTEM_CONFIG0         0x10
  21 #define SYSC_REG_SYSTEM_CONFIG1         0x14
  22 #define SYSC_REG_CLKCFG0                0x2c
  23 #define SYSC_REG_CPU_SYS_CLKCFG         0x3c
  24 #define SYSC_REG_CPLL_CONFIG0           0x54
  25 #define SYSC_REG_CPLL_CONFIG1           0x58
  26
  27 #define MT7620_CHIP_NAME0               0x3637544d
  28 #define MT7620_CHIP_NAME1               0x20203032
  29 #define MT7628_CHIP_NAME1               0x20203832
  30
  31 #define SYSCFG0_XTAL_FREQ_SEL           BIT(6)
  32
  33 #define CHIP_REV_PKG_MASK               0x1
  34 #define CHIP_REV_PKG_SHIFT              16
  35 #define CHIP_REV_VER_MASK               0xf
  36 #define CHIP_REV_VER_SHIFT              8
  37 #define CHIP_REV_ECO_MASK               0xf
  38
  39 #define CLKCFG0_PERI_CLK_SEL            BIT(4)
  40
  41 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT  16
  42 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK   0xf
  43 #define CPU_SYS_CLKCFG_OCP_RATIO_1      0       /* 1:1   (Reserved) */
  44 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5    1       /* 1:1.5 (Reserved) */
  45 #define CPU_SYS_CLKCFG_OCP_RATIO_2      2       /* 1:2   */
  46 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5    3       /* 1:2.5 (Reserved) */
  47 #define CPU_SYS_CLKCFG_OCP_RATIO_3      4       /* 1:3   */
  48 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5    5       /* 1:3.5 (Reserved) */
  49 #define CPU_SYS_CLKCFG_OCP_RATIO_4      6       /* 1:4   */
  50 #define CPU_SYS_CLKCFG_OCP_RATIO_5      7       /* 1:5   */
  51 #define CPU_SYS_CLKCFG_OCP_RATIO_10     8       /* 1:10  */
  52 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT   8
  53 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK    0x1f
  54 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT  0
  55 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK   0x1f
  56
  57 #define CPLL_CFG0_SW_CFG                BIT(31)
  58 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT  16
  59 #define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
  60 #define CPLL_CFG0_LC_CURFCK             BIT(15)
  61 #define CPLL_CFG0_BYPASS_REF_CLK        BIT(14)
  62 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT   10
  63 #define CPLL_CFG0_PLL_DIV_RATIO_MASK    0x3
  64
  65 #define CPLL_CFG1_CPU_AUX1              BIT(25)
  66 #define CPLL_CFG1_CPU_AUX0              BIT(24)
  67
  68 #define SYSCFG0_DRAM_TYPE_MASK          0x3
  69 #define SYSCFG0_DRAM_TYPE_SHIFT         4
  70 #define SYSCFG0_DRAM_TYPE_SDRAM         0
  71 #define SYSCFG0_DRAM_TYPE_DDR1          1
  72 #define SYSCFG0_DRAM_TYPE_DDR2          2
  73 #define SYSCFG0_DRAM_TYPE_UNKNOWN       3
  74
  75 #define SYSCFG0_DRAM_TYPE_DDR2_MT7628   0
  76 #define SYSCFG0_DRAM_TYPE_DDR1_MT7628   1
  77
  78 #define MT7620_DRAM_BASE                0x0
  79 #define MT7620_SDRAM_SIZE_MIN           2
  80 #define MT7620_SDRAM_SIZE_MAX           64
  81 #define MT7620_DDR1_SIZE_MIN            32
  82 #define MT7620_DDR1_SIZE_MAX            128
  83 #define MT7620_DDR2_SIZE_MIN            32
  84 #define MT7620_DDR2_SIZE_MAX            256
  85
  86 #define MT7620_GPIO_MODE_UART0_SHIFT    2
  87 #define MT7620_GPIO_MODE_UART0_MASK     0x7
  88 #define MT7620_GPIO_MODE_UART0(x)       ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
  89 #define MT7620_GPIO_MODE_UARTF          0x0
  90 #define MT7620_GPIO_MODE_PCM_UARTF      0x1
  91 #define MT7620_GPIO_MODE_PCM_I2S        0x2
  92 #define MT7620_GPIO_MODE_I2S_UARTF      0x3
  93 #define MT7620_GPIO_MODE_PCM_GPIO       0x4
  94 #define MT7620_GPIO_MODE_GPIO_UARTF     0x5
  95 #define MT7620_GPIO_MODE_GPIO_I2S       0x6
  96 #define MT7620_GPIO_MODE_GPIO           0x7
  97
  98 #define MT7620_GPIO_MODE_NAND           0
  99 #define MT7620_GPIO_MODE_SD             1
 100 #define MT7620_GPIO_MODE_ND_SD_GPIO     2
 101 #define MT7620_GPIO_MODE_ND_SD_MASK     0x3
 102 #define MT7620_GPIO_MODE_ND_SD_SHIFT    18
 103
 104 #define MT7620_GPIO_MODE_PCIE_RST       0
 105 #define MT7620_GPIO_MODE_PCIE_REF       1
 106 #define MT7620_GPIO_MODE_PCIE_GPIO      2
 107 #define MT7620_GPIO_MODE_PCIE_MASK      0x3
 108 #define MT7620_GPIO_MODE_PCIE_SHIFT     16
 109
 110 #define MT7620_GPIO_MODE_WDT_RST        0
 111 #define MT7620_GPIO_MODE_WDT_REF        1
 112 #define MT7620_GPIO_MODE_WDT_GPIO       2
 113 #define MT7620_GPIO_MODE_WDT_MASK       0x3
 114 #define MT7620_GPIO_MODE_WDT_SHIFT      21
 115
 116 #define MT7620_GPIO_MODE_MDIO           0
 117 #define MT7620_GPIO_MODE_MDIO_REFCLK    1
 118 #define MT7620_GPIO_MODE_MDIO_GPIO      2
 119 #define MT7620_GPIO_MODE_MDIO_MASK      0x3
 120 #define MT7620_GPIO_MODE_MDIO_SHIFT     7
 121
 122 #define MT7620_GPIO_MODE_I2C            0
 123 #define MT7620_GPIO_MODE_UART1          5
 124 #define MT7620_GPIO_MODE_RGMII1         9
 125 #define MT7620_GPIO_MODE_RGMII2         10
 126 #define MT7620_GPIO_MODE_SPI            11
 127 #define MT7620_GPIO_MODE_SPI_REF_CLK    12
 128 #define MT7620_GPIO_MODE_WLED           13
 129 #define MT7620_GPIO_MODE_JTAG           15
 130 #define MT7620_GPIO_MODE_EPHY           15
 131 #define MT7620_GPIO_MODE_PA             20
 132
 133 static inline int mt7620_get_eco(void)
 134 {
 135         return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
 136 }
 137
 138 #endif