arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (C) 2003-2018 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PCSXX_DEFS_H__
  29 #define __CVMX_PCSXX_DEFS_H__
  30
  31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
  32 {
  33         switch (cvmx_get_octeon_family()) {
  34         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  35         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  36         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  37                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
  38         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  39         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  40                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
  41         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  42                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
  43         }
  44         return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
  45 }
  46
  47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
  48 {
  49         switch (cvmx_get_octeon_family()) {
  50         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  51         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  52         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  53                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
  54         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  55         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  56                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
  57         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  58                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
  59         }
  60         return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
  61 }
  62
  63 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
  64 {
  65         switch (cvmx_get_octeon_family()) {
  66         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  67         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  68         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  69                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
  70         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  71         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  72                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
  73         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  74                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
  75         }
  76         return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
  77 }
  78
  79 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
  80 {
  81         switch (cvmx_get_octeon_family()) {
  82         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  83         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  84         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  85                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
  86         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  87         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  88                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
  89         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  90                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
  91         }
  92         return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
  93 }
  94
  95 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
  96 {
  97         switch (cvmx_get_octeon_family()) {
  98         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  99         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 100         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 101                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
 102         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 103         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 104                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
 105         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 106                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
 107         }
 108         return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
 109 }
 110
 111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
 112 {
 113         switch (cvmx_get_octeon_family()) {
 114         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 115         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 116         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 117                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
 118         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 119         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 120                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
 121         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 122                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
 123         }
 124         return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
 125 }
 126
 127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
 128 {
 129         switch (cvmx_get_octeon_family()) {
 130         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 131         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 132         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 133                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
 134         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 135         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 136                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
 137         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 138                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
 139         }
 140         return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
 141 }
 142
 143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
 144 {
 145         switch (cvmx_get_octeon_family()) {
 146         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 147         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 148         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 149                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
 150         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 151         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 152                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
 153         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 154                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
 155         }
 156         return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
 157 }
 158
 159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
 160 {
 161         switch (cvmx_get_octeon_family()) {
 162         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 163         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 164         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 165                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
 166         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 167         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 168                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
 169         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 170                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
 171         }
 172         return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
 173 }
 174
 175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
 176 {
 177         switch (cvmx_get_octeon_family()) {
 178         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 179         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 180         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 181                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
 182         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 183         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 184                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
 185         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 186                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
 187         }
 188         return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
 189 }
 190
 191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
 192 {
 193         switch (cvmx_get_octeon_family()) {
 194         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 195         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 196         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 197                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
 198         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 199         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 200                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
 201         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 202                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
 203         }
 204         return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
 205 }
 206
 207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
 208 {
 209         switch (cvmx_get_octeon_family()) {
 210         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 211         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 212         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 213                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
 214         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 215         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 216                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
 217         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 218                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
 219         }
 220         return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
 221 }
 222
 223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
 224 {
 225         switch (cvmx_get_octeon_family()) {
 226         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 227         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 228         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 229                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
 230         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 231         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 232                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
 233         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 234                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
 235         }
 236         return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
 237 }
 238
 239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
 240 {
 241         switch (cvmx_get_octeon_family()) {
 242         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 243         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 244         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 245                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
 246         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 247         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 248                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
 249         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 250                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
 251         }
 252         return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
 253 }
 254
 255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
 256 {
 257         switch (cvmx_get_octeon_family()) {
 258         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 259         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 260         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 261                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
 262         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 263         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 264                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
 265         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 266                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
 267         }
 268         return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
 269 }
 270
 271 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
 272
 273 union cvmx_pcsxx_10gbx_status_reg {
 274         uint64_t u64;
 275         struct cvmx_pcsxx_10gbx_status_reg_s {
 276 #ifdef __BIG_ENDIAN_BITFIELD
 277                 uint64_t reserved_13_63:51;
 278                 uint64_t alignd:1;
 279                 uint64_t pattst:1;
 280                 uint64_t reserved_4_10:7;
 281                 uint64_t l3sync:1;
 282                 uint64_t l2sync:1;
 283                 uint64_t l1sync:1;
 284                 uint64_t l0sync:1;
 285 #else
 286                 uint64_t l0sync:1;
 287                 uint64_t l1sync:1;
 288                 uint64_t l2sync:1;
 289                 uint64_t l3sync:1;
 290                 uint64_t reserved_4_10:7;
 291                 uint64_t pattst:1;
 292                 uint64_t alignd:1;
 293                 uint64_t reserved_13_63:51;
 294 #endif
 295         } s;
 296 };
 297
 298 union cvmx_pcsxx_bist_status_reg {
 299         uint64_t u64;
 300         struct cvmx_pcsxx_bist_status_reg_s {
 301 #ifdef __BIG_ENDIAN_BITFIELD
 302                 uint64_t reserved_1_63:63;
 303                 uint64_t bist_status:1;
 304 #else
 305                 uint64_t bist_status:1;
 306                 uint64_t reserved_1_63:63;
 307 #endif
 308         } s;
 309 };
 310
 311 union cvmx_pcsxx_bit_lock_status_reg {
 312         uint64_t u64;
 313         struct cvmx_pcsxx_bit_lock_status_reg_s {
 314 #ifdef __BIG_ENDIAN_BITFIELD
 315                 uint64_t reserved_4_63:60;
 316                 uint64_t bitlck3:1;
 317                 uint64_t bitlck2:1;
 318                 uint64_t bitlck1:1;
 319                 uint64_t bitlck0:1;
 320 #else
 321                 uint64_t bitlck0:1;
 322                 uint64_t bitlck1:1;
 323                 uint64_t bitlck2:1;
 324                 uint64_t bitlck3:1;
 325                 uint64_t reserved_4_63:60;
 326 #endif
 327         } s;
 328 };
 329
 330 union cvmx_pcsxx_control1_reg {
 331         uint64_t u64;
 332         struct cvmx_pcsxx_control1_reg_s {
 333 #ifdef __BIG_ENDIAN_BITFIELD
 334                 uint64_t reserved_16_63:48;
 335                 uint64_t reset:1;
 336                 uint64_t loopbck1:1;
 337                 uint64_t spdsel1:1;
 338                 uint64_t reserved_12_12:1;
 339                 uint64_t lo_pwr:1;
 340                 uint64_t reserved_7_10:4;
 341                 uint64_t spdsel0:1;
 342                 uint64_t spd:4;
 343                 uint64_t reserved_0_1:2;
 344 #else
 345                 uint64_t reserved_0_1:2;
 346                 uint64_t spd:4;
 347                 uint64_t spdsel0:1;
 348                 uint64_t reserved_7_10:4;
 349                 uint64_t lo_pwr:1;
 350                 uint64_t reserved_12_12:1;
 351                 uint64_t spdsel1:1;
 352                 uint64_t loopbck1:1;
 353                 uint64_t reset:1;
 354                 uint64_t reserved_16_63:48;
 355 #endif
 356         } s;
 357 };
 358
 359 union cvmx_pcsxx_control2_reg {
 360         uint64_t u64;
 361         struct cvmx_pcsxx_control2_reg_s {
 362 #ifdef __BIG_ENDIAN_BITFIELD
 363                 uint64_t reserved_2_63:62;
 364                 uint64_t type:2;
 365 #else
 366                 uint64_t type:2;
 367                 uint64_t reserved_2_63:62;
 368 #endif
 369         } s;
 370 };
 371
 372 union cvmx_pcsxx_int_en_reg {
 373         uint64_t u64;
 374         struct cvmx_pcsxx_int_en_reg_s {
 375 #ifdef __BIG_ENDIAN_BITFIELD
 376                 uint64_t reserved_7_63:57;
 377                 uint64_t dbg_sync_en:1;
 378                 uint64_t algnlos_en:1;
 379                 uint64_t synlos_en:1;
 380                 uint64_t bitlckls_en:1;
 381                 uint64_t rxsynbad_en:1;
 382                 uint64_t rxbad_en:1;
 383                 uint64_t txflt_en:1;
 384 #else
 385                 uint64_t txflt_en:1;
 386                 uint64_t rxbad_en:1;
 387                 uint64_t rxsynbad_en:1;
 388                 uint64_t bitlckls_en:1;
 389                 uint64_t synlos_en:1;
 390                 uint64_t algnlos_en:1;
 391                 uint64_t dbg_sync_en:1;
 392                 uint64_t reserved_7_63:57;
 393 #endif
 394         } s;
 395         struct cvmx_pcsxx_int_en_reg_cn52xx {
 396 #ifdef __BIG_ENDIAN_BITFIELD
 397                 uint64_t reserved_6_63:58;
 398                 uint64_t algnlos_en:1;
 399                 uint64_t synlos_en:1;
 400                 uint64_t bitlckls_en:1;
 401                 uint64_t rxsynbad_en:1;
 402                 uint64_t rxbad_en:1;
 403                 uint64_t txflt_en:1;
 404 #else
 405                 uint64_t txflt_en:1;
 406                 uint64_t rxbad_en:1;
 407                 uint64_t rxsynbad_en:1;
 408                 uint64_t bitlckls_en:1;
 409                 uint64_t synlos_en:1;
 410                 uint64_t algnlos_en:1;
 411                 uint64_t reserved_6_63:58;
 412 #endif
 413         } cn52xx;
 414 };
 415
 416 union cvmx_pcsxx_int_reg {
 417         uint64_t u64;
 418         struct cvmx_pcsxx_int_reg_s {
 419 #ifdef __BIG_ENDIAN_BITFIELD
 420                 uint64_t reserved_7_63:57;
 421                 uint64_t dbg_sync:1;
 422                 uint64_t algnlos:1;
 423                 uint64_t synlos:1;
 424                 uint64_t bitlckls:1;
 425                 uint64_t rxsynbad:1;
 426                 uint64_t rxbad:1;
 427                 uint64_t txflt:1;
 428 #else
 429                 uint64_t txflt:1;
 430                 uint64_t rxbad:1;
 431                 uint64_t rxsynbad:1;
 432                 uint64_t bitlckls:1;
 433                 uint64_t synlos:1;
 434                 uint64_t algnlos:1;
 435                 uint64_t dbg_sync:1;
 436                 uint64_t reserved_7_63:57;
 437 #endif
 438         } s;
 439         struct cvmx_pcsxx_int_reg_cn52xx {
 440 #ifdef __BIG_ENDIAN_BITFIELD
 441                 uint64_t reserved_6_63:58;
 442                 uint64_t algnlos:1;
 443                 uint64_t synlos:1;
 444                 uint64_t bitlckls:1;
 445                 uint64_t rxsynbad:1;
 446                 uint64_t rxbad:1;
 447                 uint64_t txflt:1;
 448 #else
 449                 uint64_t txflt:1;
 450                 uint64_t rxbad:1;
 451                 uint64_t rxsynbad:1;
 452                 uint64_t bitlckls:1;
 453                 uint64_t synlos:1;
 454                 uint64_t algnlos:1;
 455                 uint64_t reserved_6_63:58;
 456 #endif
 457         } cn52xx;
 458 };
 459
 460 union cvmx_pcsxx_log_anl_reg {
 461         uint64_t u64;
 462         struct cvmx_pcsxx_log_anl_reg_s {
 463 #ifdef __BIG_ENDIAN_BITFIELD
 464                 uint64_t reserved_7_63:57;
 465                 uint64_t enc_mode:1;
 466                 uint64_t drop_ln:2;
 467                 uint64_t lafifovfl:1;
 468                 uint64_t la_en:1;
 469                 uint64_t pkt_sz:2;
 470 #else
 471                 uint64_t pkt_sz:2;
 472                 uint64_t la_en:1;
 473                 uint64_t lafifovfl:1;
 474                 uint64_t drop_ln:2;
 475                 uint64_t enc_mode:1;
 476                 uint64_t reserved_7_63:57;
 477 #endif
 478         } s;
 479 };
 480
 481 union cvmx_pcsxx_misc_ctl_reg {
 482         uint64_t u64;
 483         struct cvmx_pcsxx_misc_ctl_reg_s {
 484 #ifdef __BIG_ENDIAN_BITFIELD
 485                 uint64_t reserved_4_63:60;
 486                 uint64_t tx_swap:1;
 487                 uint64_t rx_swap:1;
 488                 uint64_t xaui:1;
 489                 uint64_t gmxeno:1;
 490 #else
 491                 uint64_t gmxeno:1;
 492                 uint64_t xaui:1;
 493                 uint64_t rx_swap:1;
 494                 uint64_t tx_swap:1;
 495                 uint64_t reserved_4_63:60;
 496 #endif
 497         } s;
 498 };
 499
 500 union cvmx_pcsxx_rx_sync_states_reg {
 501         uint64_t u64;
 502         struct cvmx_pcsxx_rx_sync_states_reg_s {
 503 #ifdef __BIG_ENDIAN_BITFIELD
 504                 uint64_t reserved_16_63:48;
 505                 uint64_t sync3st:4;
 506                 uint64_t sync2st:4;
 507                 uint64_t sync1st:4;
 508                 uint64_t sync0st:4;
 509 #else
 510                 uint64_t sync0st:4;
 511                 uint64_t sync1st:4;
 512                 uint64_t sync2st:4;
 513                 uint64_t sync3st:4;
 514                 uint64_t reserved_16_63:48;
 515 #endif
 516         } s;
 517 };
 518
 519 union cvmx_pcsxx_spd_abil_reg {
 520         uint64_t u64;
 521         struct cvmx_pcsxx_spd_abil_reg_s {
 522 #ifdef __BIG_ENDIAN_BITFIELD
 523                 uint64_t reserved_2_63:62;
 524                 uint64_t tenpasst:1;
 525                 uint64_t tengb:1;
 526 #else
 527                 uint64_t tengb:1;
 528                 uint64_t tenpasst:1;
 529                 uint64_t reserved_2_63:62;
 530 #endif
 531         } s;
 532 };
 533
 534 union cvmx_pcsxx_status1_reg {
 535         uint64_t u64;
 536         struct cvmx_pcsxx_status1_reg_s {
 537 #ifdef __BIG_ENDIAN_BITFIELD
 538                 uint64_t reserved_8_63:56;
 539                 uint64_t flt:1;
 540                 uint64_t reserved_3_6:4;
 541                 uint64_t rcv_lnk:1;
 542                 uint64_t lpable:1;
 543                 uint64_t reserved_0_0:1;
 544 #else
 545                 uint64_t reserved_0_0:1;
 546                 uint64_t lpable:1;
 547                 uint64_t rcv_lnk:1;
 548                 uint64_t reserved_3_6:4;
 549                 uint64_t flt:1;
 550                 uint64_t reserved_8_63:56;
 551 #endif
 552         } s;
 553 };
 554
 555 union cvmx_pcsxx_status2_reg {
 556         uint64_t u64;
 557         struct cvmx_pcsxx_status2_reg_s {
 558 #ifdef __BIG_ENDIAN_BITFIELD
 559                 uint64_t reserved_16_63:48;
 560                 uint64_t dev:2;
 561                 uint64_t reserved_12_13:2;
 562                 uint64_t xmtflt:1;
 563                 uint64_t rcvflt:1;
 564                 uint64_t reserved_3_9:7;
 565                 uint64_t tengb_w:1;
 566                 uint64_t tengb_x:1;
 567                 uint64_t tengb_r:1;
 568 #else
 569                 uint64_t tengb_r:1;
 570                 uint64_t tengb_x:1;
 571                 uint64_t tengb_w:1;
 572                 uint64_t reserved_3_9:7;
 573                 uint64_t rcvflt:1;
 574                 uint64_t xmtflt:1;
 575                 uint64_t reserved_12_13:2;
 576                 uint64_t dev:2;
 577                 uint64_t reserved_16_63:48;
 578 #endif
 579         } s;
 580 };
 581
 582 union cvmx_pcsxx_tx_rx_polarity_reg {
 583         uint64_t u64;
 584         struct cvmx_pcsxx_tx_rx_polarity_reg_s {
 585 #ifdef __BIG_ENDIAN_BITFIELD
 586                 uint64_t reserved_10_63:54;
 587                 uint64_t xor_rxplrt:4;
 588                 uint64_t xor_txplrt:4;
 589                 uint64_t rxplrt:1;
 590                 uint64_t txplrt:1;
 591 #else
 592                 uint64_t txplrt:1;
 593                 uint64_t rxplrt:1;
 594                 uint64_t xor_txplrt:4;
 595                 uint64_t xor_rxplrt:4;
 596                 uint64_t reserved_10_63:54;
 597 #endif
 598         } s;
 599         struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
 600 #ifdef __BIG_ENDIAN_BITFIELD
 601                 uint64_t reserved_2_63:62;
 602                 uint64_t rxplrt:1;
 603                 uint64_t txplrt:1;
 604 #else
 605                 uint64_t txplrt:1;
 606                 uint64_t rxplrt:1;
 607                 uint64_t reserved_2_63:62;
 608 #endif
 609         } cn52xxp1;
 610 };
 611
 612 union cvmx_pcsxx_tx_rx_states_reg {
 613         uint64_t u64;
 614         struct cvmx_pcsxx_tx_rx_states_reg_s {
 615 #ifdef __BIG_ENDIAN_BITFIELD
 616                 uint64_t reserved_14_63:50;
 617                 uint64_t term_err:1;
 618                 uint64_t syn3bad:1;
 619                 uint64_t syn2bad:1;
 620                 uint64_t syn1bad:1;
 621                 uint64_t syn0bad:1;
 622                 uint64_t rxbad:1;
 623                 uint64_t algn_st:3;
 624                 uint64_t rx_st:2;
 625                 uint64_t tx_st:3;
 626 #else
 627                 uint64_t tx_st:3;
 628                 uint64_t rx_st:2;
 629                 uint64_t algn_st:3;
 630                 uint64_t rxbad:1;
 631                 uint64_t syn0bad:1;
 632                 uint64_t syn1bad:1;
 633                 uint64_t syn2bad:1;
 634                 uint64_t syn3bad:1;
 635                 uint64_t term_err:1;
 636                 uint64_t reserved_14_63:50;
 637 #endif
 638         } s;
 639         struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
 640 #ifdef __BIG_ENDIAN_BITFIELD
 641                 uint64_t reserved_13_63:51;
 642                 uint64_t syn3bad:1;
 643                 uint64_t syn2bad:1;
 644                 uint64_t syn1bad:1;
 645                 uint64_t syn0bad:1;
 646                 uint64_t rxbad:1;
 647                 uint64_t algn_st:3;
 648                 uint64_t rx_st:2;
 649                 uint64_t tx_st:3;
 650 #else
 651                 uint64_t tx_st:3;
 652                 uint64_t rx_st:2;
 653                 uint64_t algn_st:3;
 654                 uint64_t rxbad:1;
 655                 uint64_t syn0bad:1;
 656                 uint64_t syn1bad:1;
 657                 uint64_t syn2bad:1;
 658                 uint64_t syn3bad:1;
 659                 uint64_t reserved_13_63:51;
 660 #endif
 661         } cn52xxp1;
 662 };
 663
 664 #endif