arch/mips/include/asm/octeon/cvmx-stxx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (C) 2003-2018 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_STXX_DEFS_H__
  29 #define __CVMX_STXX_DEFS_H__
  30
  31 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
  32 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
  33 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
  34 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
  35 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
  36 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
  37 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
  38 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
  39 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
  40 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
  41 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
  42 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
  43 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
  44 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
  45 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
  46 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
  47
  48 void __cvmx_interrupt_stxx_int_msk_enable(int index);
  49
  50 union cvmx_stxx_arb_ctl {
  51         uint64_t u64;
  52         struct cvmx_stxx_arb_ctl_s {
  53 #ifdef __BIG_ENDIAN_BITFIELD
  54                 uint64_t reserved_6_63:58;
  55                 uint64_t mintrn:1;
  56                 uint64_t reserved_4_4:1;
  57                 uint64_t igntpa:1;
  58                 uint64_t reserved_0_2:3;
  59 #else
  60                 uint64_t reserved_0_2:3;
  61                 uint64_t igntpa:1;
  62                 uint64_t reserved_4_4:1;
  63                 uint64_t mintrn:1;
  64                 uint64_t reserved_6_63:58;
  65 #endif
  66         } s;
  67 };
  68
  69 union cvmx_stxx_bckprs_cnt {
  70         uint64_t u64;
  71         struct cvmx_stxx_bckprs_cnt_s {
  72 #ifdef __BIG_ENDIAN_BITFIELD
  73                 uint64_t reserved_32_63:32;
  74                 uint64_t cnt:32;
  75 #else
  76                 uint64_t cnt:32;
  77                 uint64_t reserved_32_63:32;
  78 #endif
  79         } s;
  80 };
  81
  82 union cvmx_stxx_com_ctl {
  83         uint64_t u64;
  84         struct cvmx_stxx_com_ctl_s {
  85 #ifdef __BIG_ENDIAN_BITFIELD
  86                 uint64_t reserved_4_63:60;
  87                 uint64_t st_en:1;
  88                 uint64_t reserved_1_2:2;
  89                 uint64_t inf_en:1;
  90 #else
  91                 uint64_t inf_en:1;
  92                 uint64_t reserved_1_2:2;
  93                 uint64_t st_en:1;
  94                 uint64_t reserved_4_63:60;
  95 #endif
  96         } s;
  97 };
  98
  99 union cvmx_stxx_dip_cnt {
 100         uint64_t u64;
 101         struct cvmx_stxx_dip_cnt_s {
 102 #ifdef __BIG_ENDIAN_BITFIELD
 103                 uint64_t reserved_8_63:56;
 104                 uint64_t frmmax:4;
 105                 uint64_t dipmax:4;
 106 #else
 107                 uint64_t dipmax:4;
 108                 uint64_t frmmax:4;
 109                 uint64_t reserved_8_63:56;
 110 #endif
 111         } s;
 112 };
 113
 114 union cvmx_stxx_ign_cal {
 115         uint64_t u64;
 116         struct cvmx_stxx_ign_cal_s {
 117 #ifdef __BIG_ENDIAN_BITFIELD
 118                 uint64_t reserved_16_63:48;
 119                 uint64_t igntpa:16;
 120 #else
 121                 uint64_t igntpa:16;
 122                 uint64_t reserved_16_63:48;
 123 #endif
 124         } s;
 125 };
 126
 127 union cvmx_stxx_int_msk {
 128         uint64_t u64;
 129         struct cvmx_stxx_int_msk_s {
 130 #ifdef __BIG_ENDIAN_BITFIELD
 131                 uint64_t reserved_8_63:56;
 132                 uint64_t frmerr:1;
 133                 uint64_t unxfrm:1;
 134                 uint64_t nosync:1;
 135                 uint64_t diperr:1;
 136                 uint64_t datovr:1;
 137                 uint64_t ovrbst:1;
 138                 uint64_t calpar1:1;
 139                 uint64_t calpar0:1;
 140 #else
 141                 uint64_t calpar0:1;
 142                 uint64_t calpar1:1;
 143                 uint64_t ovrbst:1;
 144                 uint64_t datovr:1;
 145                 uint64_t diperr:1;
 146                 uint64_t nosync:1;
 147                 uint64_t unxfrm:1;
 148                 uint64_t frmerr:1;
 149                 uint64_t reserved_8_63:56;
 150 #endif
 151         } s;
 152 };
 153
 154 union cvmx_stxx_int_reg {
 155         uint64_t u64;
 156         struct cvmx_stxx_int_reg_s {
 157 #ifdef __BIG_ENDIAN_BITFIELD
 158                 uint64_t reserved_9_63:55;
 159                 uint64_t syncerr:1;
 160                 uint64_t frmerr:1;
 161                 uint64_t unxfrm:1;
 162                 uint64_t nosync:1;
 163                 uint64_t diperr:1;
 164                 uint64_t datovr:1;
 165                 uint64_t ovrbst:1;
 166                 uint64_t calpar1:1;
 167                 uint64_t calpar0:1;
 168 #else
 169                 uint64_t calpar0:1;
 170                 uint64_t calpar1:1;
 171                 uint64_t ovrbst:1;
 172                 uint64_t datovr:1;
 173                 uint64_t diperr:1;
 174                 uint64_t nosync:1;
 175                 uint64_t unxfrm:1;
 176                 uint64_t frmerr:1;
 177                 uint64_t syncerr:1;
 178                 uint64_t reserved_9_63:55;
 179 #endif
 180         } s;
 181 };
 182
 183 union cvmx_stxx_int_sync {
 184         uint64_t u64;
 185         struct cvmx_stxx_int_sync_s {
 186 #ifdef __BIG_ENDIAN_BITFIELD
 187                 uint64_t reserved_8_63:56;
 188                 uint64_t frmerr:1;
 189                 uint64_t unxfrm:1;
 190                 uint64_t nosync:1;
 191                 uint64_t diperr:1;
 192                 uint64_t datovr:1;
 193                 uint64_t ovrbst:1;
 194                 uint64_t calpar1:1;
 195                 uint64_t calpar0:1;
 196 #else
 197                 uint64_t calpar0:1;
 198                 uint64_t calpar1:1;
 199                 uint64_t ovrbst:1;
 200                 uint64_t datovr:1;
 201                 uint64_t diperr:1;
 202                 uint64_t nosync:1;
 203                 uint64_t unxfrm:1;
 204                 uint64_t frmerr:1;
 205                 uint64_t reserved_8_63:56;
 206 #endif
 207         } s;
 208 };
 209
 210 union cvmx_stxx_min_bst {
 211         uint64_t u64;
 212         struct cvmx_stxx_min_bst_s {
 213 #ifdef __BIG_ENDIAN_BITFIELD
 214                 uint64_t reserved_9_63:55;
 215                 uint64_t minb:9;
 216 #else
 217                 uint64_t minb:9;
 218                 uint64_t reserved_9_63:55;
 219 #endif
 220         } s;
 221 };
 222
 223 union cvmx_stxx_spi4_calx {
 224         uint64_t u64;
 225         struct cvmx_stxx_spi4_calx_s {
 226 #ifdef __BIG_ENDIAN_BITFIELD
 227                 uint64_t reserved_17_63:47;
 228                 uint64_t oddpar:1;
 229                 uint64_t prt3:4;
 230                 uint64_t prt2:4;
 231                 uint64_t prt1:4;
 232                 uint64_t prt0:4;
 233 #else
 234                 uint64_t prt0:4;
 235                 uint64_t prt1:4;
 236                 uint64_t prt2:4;
 237                 uint64_t prt3:4;
 238                 uint64_t oddpar:1;
 239                 uint64_t reserved_17_63:47;
 240 #endif
 241         } s;
 242 };
 243
 244 union cvmx_stxx_spi4_dat {
 245         uint64_t u64;
 246         struct cvmx_stxx_spi4_dat_s {
 247 #ifdef __BIG_ENDIAN_BITFIELD
 248                 uint64_t reserved_32_63:32;
 249                 uint64_t alpha:16;
 250                 uint64_t max_t:16;
 251 #else
 252                 uint64_t max_t:16;
 253                 uint64_t alpha:16;
 254                 uint64_t reserved_32_63:32;
 255 #endif
 256         } s;
 257 };
 258
 259 union cvmx_stxx_spi4_stat {
 260         uint64_t u64;
 261         struct cvmx_stxx_spi4_stat_s {
 262 #ifdef __BIG_ENDIAN_BITFIELD
 263                 uint64_t reserved_16_63:48;
 264                 uint64_t m:8;
 265                 uint64_t reserved_7_7:1;
 266                 uint64_t len:7;
 267 #else
 268                 uint64_t len:7;
 269                 uint64_t reserved_7_7:1;
 270                 uint64_t m:8;
 271                 uint64_t reserved_16_63:48;
 272 #endif
 273         } s;
 274 };
 275
 276 union cvmx_stxx_stat_bytes_hi {
 277         uint64_t u64;
 278         struct cvmx_stxx_stat_bytes_hi_s {
 279 #ifdef __BIG_ENDIAN_BITFIELD
 280                 uint64_t reserved_32_63:32;
 281                 uint64_t cnt:32;
 282 #else
 283                 uint64_t cnt:32;
 284                 uint64_t reserved_32_63:32;
 285 #endif
 286         } s;
 287 };
 288
 289 union cvmx_stxx_stat_bytes_lo {
 290         uint64_t u64;
 291         struct cvmx_stxx_stat_bytes_lo_s {
 292 #ifdef __BIG_ENDIAN_BITFIELD
 293                 uint64_t reserved_32_63:32;
 294                 uint64_t cnt:32;
 295 #else
 296                 uint64_t cnt:32;
 297                 uint64_t reserved_32_63:32;
 298 #endif
 299         } s;
 300 };
 301
 302 union cvmx_stxx_stat_ctl {
 303         uint64_t u64;
 304         struct cvmx_stxx_stat_ctl_s {
 305 #ifdef __BIG_ENDIAN_BITFIELD
 306                 uint64_t reserved_5_63:59;
 307                 uint64_t clr:1;
 308                 uint64_t bckprs:4;
 309 #else
 310                 uint64_t bckprs:4;
 311                 uint64_t clr:1;
 312                 uint64_t reserved_5_63:59;
 313 #endif
 314         } s;
 315 };
 316
 317 union cvmx_stxx_stat_pkt_xmt {
 318         uint64_t u64;
 319         struct cvmx_stxx_stat_pkt_xmt_s {
 320 #ifdef __BIG_ENDIAN_BITFIELD
 321                 uint64_t reserved_32_63:32;
 322                 uint64_t cnt:32;
 323 #else
 324                 uint64_t cnt:32;
 325                 uint64_t reserved_32_63:32;
 326 #endif
 327         } s;
 328 };
 329
 330 #endif