arch/mips/include/asm/vr41xx/vr41xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * include/asm-mips/vr41xx/vr41xx.h
   4  *
   5  * Include file for NEC VR4100 series.
   6  *
   7  * Copyright (C) 1999 Michael Klar
   8  * Copyright (C) 2001, 2002 Paul Mundt
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  * Copyright (C) 2002 TimeSys Corp.
  11  * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
  12  */
  13 #ifndef __NEC_VR41XX_H
  14 #define __NEC_VR41XX_H
  15
  16 #include <linux/interrupt.h>
  17
  18 /*
  19  * CPU Revision
  20  */
  21 /* VR4122 0x00000c70-0x00000c72 */
  22 #define PRID_VR4122_REV1_0      0x00000c70
  23 #define PRID_VR4122_REV2_0      0x00000c70
  24 #define PRID_VR4122_REV2_1      0x00000c70
  25 #define PRID_VR4122_REV3_0      0x00000c71
  26 #define PRID_VR4122_REV3_1      0x00000c72
  27
  28 /* VR4181A 0x00000c73-0x00000c7f */
  29 #define PRID_VR4181A_REV1_0     0x00000c73
  30 #define PRID_VR4181A_REV1_1     0x00000c74
  31
  32 /* VR4131 0x00000c80-0x00000c83 */
  33 #define PRID_VR4131_REV1_2      0x00000c80
  34 #define PRID_VR4131_REV2_0      0x00000c81
  35 #define PRID_VR4131_REV2_1      0x00000c82
  36 #define PRID_VR4131_REV2_2      0x00000c83
  37
  38 /* VR4133 0x00000c84- */
  39 #define PRID_VR4133             0x00000c84
  40
  41 /*
  42  * Bus Control Uint
  43  */
  44 extern unsigned long vr41xx_calculate_clock_frequency(void);
  45 extern unsigned long vr41xx_get_vtclock_frequency(void);
  46 extern unsigned long vr41xx_get_tclock_frequency(void);
  47
  48 /*
  49  * Clock Mask Unit
  50  */
  51 typedef enum {
  52         PIU_CLOCK,
  53         SIU_CLOCK,
  54         AIU_CLOCK,
  55         KIU_CLOCK,
  56         FIR_CLOCK,
  57         DSIU_CLOCK,
  58         CSI_CLOCK,
  59         PCIU_CLOCK,
  60         HSP_CLOCK,
  61         PCI_CLOCK,
  62         CEU_CLOCK,
  63         ETHER0_CLOCK,
  64         ETHER1_CLOCK
  65 } vr41xx_clock_t;
  66
  67 extern void vr41xx_supply_clock(vr41xx_clock_t clock);
  68 extern void vr41xx_mask_clock(vr41xx_clock_t clock);
  69
  70 /*
  71  * Interrupt Control Unit
  72  */
  73 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
  74 extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
  75
  76 #define PIUINT_COMMAND          0x0040
  77 #define PIUINT_DATA             0x0020
  78 #define PIUINT_PAGE1            0x0010
  79 #define PIUINT_PAGE0            0x0008
  80 #define PIUINT_DATALOST         0x0004
  81 #define PIUINT_STATUSCHANGE     0x0001
  82
  83 extern void vr41xx_enable_piuint(uint16_t mask);
  84 extern void vr41xx_disable_piuint(uint16_t mask);
  85
  86 #define AIUINT_INPUT_DMAEND     0x0800
  87 #define AIUINT_INPUT_DMAHALT    0x0400
  88 #define AIUINT_INPUT_DATALOST   0x0200
  89 #define AIUINT_INPUT_DATA       0x0100
  90 #define AIUINT_OUTPUT_DMAEND    0x0008
  91 #define AIUINT_OUTPUT_DMAHALT   0x0004
  92 #define AIUINT_OUTPUT_NODATA    0x0002
  93
  94 extern void vr41xx_enable_aiuint(uint16_t mask);
  95 extern void vr41xx_disable_aiuint(uint16_t mask);
  96
  97 #define KIUINT_DATALOST         0x0004
  98 #define KIUINT_DATAREADY        0x0002
  99 #define KIUINT_SCAN             0x0001
 100
 101 extern void vr41xx_enable_kiuint(uint16_t mask);
 102 extern void vr41xx_disable_kiuint(uint16_t mask);
 103
 104 #define DSIUINT_CTS             0x0800
 105 #define DSIUINT_RXERR           0x0400
 106 #define DSIUINT_RX              0x0200
 107 #define DSIUINT_TX              0x0100
 108 #define DSIUINT_ALL             0x0f00
 109
 110 extern void vr41xx_enable_dsiuint(uint16_t mask);
 111 extern void vr41xx_disable_dsiuint(uint16_t mask);
 112
 113 #define FIRINT_UNIT             0x0010
 114 #define FIRINT_RX_DMAEND        0x0008
 115 #define FIRINT_RX_DMAHALT       0x0004
 116 #define FIRINT_TX_DMAEND        0x0002
 117 #define FIRINT_TX_DMAHALT       0x0001
 118
 119 extern void vr41xx_enable_firint(uint16_t mask);
 120 extern void vr41xx_disable_firint(uint16_t mask);
 121
 122 extern void vr41xx_enable_pciint(void);
 123 extern void vr41xx_disable_pciint(void);
 124
 125 extern void vr41xx_enable_scuint(void);
 126 extern void vr41xx_disable_scuint(void);
 127
 128 #define CSIINT_TX_DMAEND        0x0040
 129 #define CSIINT_TX_DMAHALT       0x0020
 130 #define CSIINT_TX_DATA          0x0010
 131 #define CSIINT_TX_FIFOEMPTY     0x0008
 132 #define CSIINT_RX_DMAEND        0x0004
 133 #define CSIINT_RX_DMAHALT       0x0002
 134 #define CSIINT_RX_FIFOEMPTY     0x0001
 135
 136 extern void vr41xx_enable_csiint(uint16_t mask);
 137 extern void vr41xx_disable_csiint(uint16_t mask);
 138
 139 extern void vr41xx_enable_bcuint(void);
 140 extern void vr41xx_disable_bcuint(void);
 141
 142 #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
 143 extern void vr41xx_siu_setup(void);
 144 #else
 145 static inline void vr41xx_siu_setup(void) {}
 146 #endif
 147
 148 #endif /* __NEC_VR41XX_H */