arch/mips/pci/pci-bcm1480ht.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2001,2002,2005 Broadcom Corporation
   4  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   5  */
   6
   7 /*
   8  * BCM1480/1455-specific HT support (looking like PCI)
   9  *
  10  * This module provides the glue between Linux's PCI subsystem
  11  * and the hardware.  We basically provide glue for accessing
  12  * configuration space, and set up the translation for I/O
  13  * space accesses.
  14  *
  15  * To access configuration space, we use ioremap.  In the 32-bit
  16  * kernel, this consumes either 4 or 8 page table pages, and 16MB of
  17  * kernel mapped memory.  Hopefully neither of these should be a huge
  18  * problem.
  19  *
  20  */
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/mm.h>
  26 #include <linux/console.h>
  27 #include <linux/tty.h>
  28
  29 #include <asm/sibyte/bcm1480_regs.h>
  30 #include <asm/sibyte/bcm1480_scd.h>
  31 #include <asm/sibyte/board.h>
  32 #include <asm/io.h>
  33
  34 /*
  35  * Macros for calculating offsets into config space given a device
  36  * structure or dev/fun/reg
  37  */
  38 #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
  39 #define CFGADDR(bus, devfn, where)   CFGOFFSET((bus)->number, (devfn), where)
  40
  41 static void *ht_cfg_space;
  42
  43 #define PCI_BUS_ENABLED 1
  44 #define PCI_DEVICE_MODE 2
  45
  46 static int bcm1480ht_bus_status;
  47
  48 #define PCI_BRIDGE_DEVICE  0
  49 #define HT_BRIDGE_DEVICE   1
  50
  51 /*
  52  * HT's level-sensitive interrupts require EOI, which is generated
  53  * through a 4MB memory-mapped region
  54  */
  55 unsigned long ht_eoi_space;
  56
  57 /*
  58  * Read/write 32-bit values in config space.
  59  */
  60 static inline u32 READCFG32(u32 addr)
  61 {
  62         return *(u32 *)(ht_cfg_space + (addr&~3));
  63 }
  64
  65 static inline void WRITECFG32(u32 addr, u32 data)
  66 {
  67         *(u32 *)(ht_cfg_space + (addr & ~3)) = data;
  68 }
  69
  70 /*
  71  * Some checks before doing config cycles:
  72  * In PCI Device Mode, hide everything on bus 0 except the LDT host
  73  * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
  74  */
  75 static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
  76 {
  77         u32 devno;
  78
  79         if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
  80                 return 0;
  81
  82         if (bus->number == 0) {
  83                 devno = PCI_SLOT(devfn);
  84                 if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
  85                         return 0;
  86         }
  87         return 1;
  88 }
  89
  90 /*
  91  * Read/write access functions for various sizes of values
  92  * in config space.  Return all 1's for disallowed accesses
  93  * for a kludgy but adequate simulation of master aborts.
  94  */
  95
  96 static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  97                                   int where, int size, u32 * val)
  98 {
  99         u32 data = 0;
 100
 101         if ((size == 2) && (where & 1))
 102                 return PCIBIOS_BAD_REGISTER_NUMBER;
 103         else if ((size == 4) && (where & 3))
 104                 return PCIBIOS_BAD_REGISTER_NUMBER;
 105
 106         if (bcm1480ht_can_access(bus, devfn))
 107                 data = READCFG32(CFGADDR(bus, devfn, where));
 108         else
 109                 data = 0xFFFFFFFF;
 110
 111         if (size == 1)
 112                 *val = (data >> ((where & 3) << 3)) & 0xff;
 113         else if (size == 2)
 114                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 115         else
 116                 *val = data;
 117
 118         return PCIBIOS_SUCCESSFUL;
 119 }
 120
 121 static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 122                                    int where, int size, u32 val)
 123 {
 124         u32 cfgaddr = CFGADDR(bus, devfn, where);
 125         u32 data = 0;
 126
 127         if ((size == 2) && (where & 1))
 128                 return PCIBIOS_BAD_REGISTER_NUMBER;
 129         else if ((size == 4) && (where & 3))
 130                 return PCIBIOS_BAD_REGISTER_NUMBER;
 131
 132         if (!bcm1480ht_can_access(bus, devfn))
 133                 return PCIBIOS_BAD_REGISTER_NUMBER;
 134
 135         data = READCFG32(cfgaddr);
 136
 137         if (size == 1)
 138                 data = (data & ~(0xff << ((where & 3) << 3))) |
 139                     (val << ((where & 3) << 3));
 140         else if (size == 2)
 141                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 142                     (val << ((where & 3) << 3));
 143         else
 144                 data = val;
 145
 146         WRITECFG32(cfgaddr, data);
 147
 148         return PCIBIOS_SUCCESSFUL;
 149 }
 150
 151 static int bcm1480ht_pcibios_get_busno(void)
 152 {
 153         return 0;
 154 }
 155
 156 struct pci_ops bcm1480ht_pci_ops = {
 157         .read   = bcm1480ht_pcibios_read,
 158         .write  = bcm1480ht_pcibios_write,
 159 };
 160
 161 static struct resource bcm1480ht_mem_resource = {
 162         .name   = "BCM1480 HT MEM",
 163         .start  = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES,
 164         .end    = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL,
 165         .flags  = IORESOURCE_MEM,
 166 };
 167
 168 static struct resource bcm1480ht_io_resource = {
 169         .name   = "BCM1480 HT I/O",
 170         .start  = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
 171         .end    = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
 172         .flags  = IORESOURCE_IO,
 173 };
 174
 175 struct pci_controller bcm1480ht_controller = {
 176         .pci_ops        = &bcm1480ht_pci_ops,
 177         .mem_resource   = &bcm1480ht_mem_resource,
 178         .io_resource    = &bcm1480ht_io_resource,
 179         .index          = 1,
 180         .get_busno      = bcm1480ht_pcibios_get_busno,
 181         .io_offset      = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
 182 };
 183
 184 static int __init bcm1480ht_pcibios_init(void)
 185 {
 186         ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
 187
 188         /* CFE doesn't always init all HT paths, so we always scan */
 189         bcm1480ht_bus_status |= PCI_BUS_ENABLED;
 190
 191         ht_eoi_space = (unsigned long)
 192                 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
 193                         4 * 1024 * 1024);
 194         bcm1480ht_controller.io_map_base = (unsigned long)
 195                 ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
 196         bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
 197
 198         register_pci_controller(&bcm1480ht_controller);
 199
 200         return 0;
 201 }
 202
 203 arch_initcall(bcm1480ht_pcibios_init);