1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * board.c: STB225 board support.
5 * Copyright 2008 NXP Semiconductors
6 * Chris Steel <chris.steel@nxp.com>
7 * Daniel Laird <daniel.j.laird@nxp.com>
9 * Based on software written by:
10 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
12 #include <linux/init.h>
13 #include <asm/bootinfo.h>
18 /* endianess twiddlers */
19 #define PNX8335_DEBUG0 0x4400
20 #define PNX8335_DEBUG1 0x4404
21 #define PNX8335_DEBUG2 0x4408
22 #define PNX8335_DEBUG3 0x440c
23 #define PNX8335_DEBUG4 0x4410
24 #define PNX8335_DEBUG5 0x4414
25 #define PNX8335_DEBUG6 0x4418
26 #define PNX8335_DEBUG7 0x441c
29 char **prom_argv
, **prom_envp
;
31 extern void prom_init_cmdline(void);
32 extern char *prom_getenv(char *envname
);
34 const char *get_system_type(void)
39 static inline unsigned long env_or_default(char *env
, unsigned long dfl
)
41 char *str
= prom_getenv(env
);
42 return str
? simple_strtol(str
, 0, 0) : dfl
;
45 void __init
prom_init(void)
47 unsigned long memsize
;
50 prom_argv
= (char **)fw_arg1
;
51 prom_envp
= (char **)fw_arg2
;
55 memsize
= env_or_default("memsize", 0x02000000);
56 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
59 void __init
pnx833x_board_setup(void)
61 pnx833x_gpio_select_function_alt(4);
62 pnx833x_gpio_select_output(4);
63 pnx833x_gpio_select_function_alt(5);
64 pnx833x_gpio_select_input(5);
65 pnx833x_gpio_select_function_alt(6);
66 pnx833x_gpio_select_input(6);
67 pnx833x_gpio_select_function_alt(7);
68 pnx833x_gpio_select_output(7);
70 pnx833x_gpio_select_function_alt(25);
71 pnx833x_gpio_select_function_alt(26);
73 pnx833x_gpio_select_function_alt(27);
74 pnx833x_gpio_select_function_alt(28);
75 pnx833x_gpio_select_function_alt(29);
76 pnx833x_gpio_select_function_alt(30);
77 pnx833x_gpio_select_function_alt(31);
78 pnx833x_gpio_select_function_alt(32);
79 pnx833x_gpio_select_function_alt(33);
81 #if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
82 /* Setup MIU for NAND access on CS0...
84 * (it seems that we must also configure CS1 for reliable operation,
85 * otherwise the first read ID command will fail if it's read as 4 bytes
86 * but pass if it's read as 1 word.)
89 /* Setup MIU CS0 & CS1 timing */
92 PNX833X_MIU_SEL0_TIMING
= 0x50003081;
93 PNX833X_MIU_SEL1_TIMING
= 0x50003081;
95 /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
96 pnx833x_gpio_select_function_alt(0);
98 /* Setup GPIO 04 to input NAND read/busy signal */
99 pnx833x_gpio_select_function_io(4);
100 pnx833x_gpio_select_input(4);
102 /* Setup GPIO 05 to disable NAND write protect */
103 pnx833x_gpio_select_function_io(5);
104 pnx833x_gpio_select_output(5);
105 pnx833x_gpio_write(1, 5);
107 #elif IS_ENABLED(CONFIG_MTD_CFI)
109 /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
111 /* Setup MIU CS0 & CS1 timing */
112 PNX833X_MIU_SEL0
= 1;
113 PNX833X_MIU_SEL1
= 1;
114 PNX833X_MIU_SEL0_TIMING
= 0x6A08D082;
115 PNX833X_MIU_SEL1_TIMING
= 0x6A08D082;
117 /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
118 pnx833x_gpio_select_function_alt(0);