arch/powerpc/boot/dts/fsl/mpc8572ds.dtsi

   1 /*
   2  * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &board_lbc {
  36         nor@0,0 {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "cfi-flash";
  40                 reg = <0x0 0x0 0x8000000>;
  41                 bank-width = <2>;
  42                 device-width = <1>;
  43
  44                 partition@0 {
  45                         reg = <0x0 0x03000000>;
  46                         label = "ramdisk-nor";
  47                 };
  48
  49                 partition@3000000 {
  50                         reg = <0x03000000 0x00e00000>;
  51                         label = "diagnostic-nor";
  52                         read-only;
  53                 };
  54
  55                 partition@3e00000 {
  56                         reg = <0x03e00000 0x00200000>;
  57                         label = "dink-nor";
  58                         read-only;
  59                 };
  60
  61                 partition@4000000 {
  62                         reg = <0x04000000 0x00400000>;
  63                         label = "kernel-nor";
  64                 };
  65
  66                 partition@4400000 {
  67                         reg = <0x04400000 0x03b00000>;
  68                         label = "fs-nor";
  69                 };
  70
  71                 partition@7f00000 {
  72                         reg = <0x07f00000 0x00060000>;
  73                         label = "dtb-nor";
  74                 };
  75
  76                 partition@7f60000 {
  77                         reg = <0x07f60000 0x00020000>;
  78                         label = "env-nor";
  79                         read-only;
  80                 };
  81
  82                 partition@7f80000 {
  83                         reg = <0x07f80000 0x00080000>;
  84                         label = "u-boot-nor";
  85                         read-only;
  86                 };
  87         };
  88
  89         nand@2,0 {
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 compatible = "fsl,mpc8572-fcm-nand",
  93                              "fsl,elbc-fcm-nand";
  94                 reg = <0x2 0x0 0x40000>;
  95
  96                 partition@0 {
  97                         reg = <0x0 0x02000000>;
  98                         label = "u-boot-nand";
  99                         read-only;
 100                 };
 101
 102                 partition@2000000 {
 103                         reg = <0x02000000 0x10000000>;
 104                         label = "fs-nand";
 105                 };
 106
 107                 partition@12000000 {
 108                         reg = <0x12000000 0x08000000>;
 109                         label = "ramdisk-nand";
 110                 };
 111
 112                 partition@1a000000 {
 113                         reg = <0x1a000000 0x04000000>;
 114                         label = "kernel-nand";
 115                 };
 116
 117                 partition@1e000000 {
 118                         reg = <0x1e000000 0x01000000>;
 119                         label = "dtb-nand";
 120                 };
 121
 122                 partition@1f000000 {
 123                         reg = <0x1f000000 0x21000000>;
 124                         label = "empty-nand";
 125                 };
 126         };
 127
 128         nand@4,0 {
 129                 compatible = "fsl,mpc8572-fcm-nand",
 130                              "fsl,elbc-fcm-nand";
 131                 reg = <0x4 0x0 0x40000>;
 132         };
 133
 134         nand@5,0 {
 135                 compatible = "fsl,mpc8572-fcm-nand",
 136                              "fsl,elbc-fcm-nand";
 137                 reg = <0x5 0x0 0x40000>;
 138         };
 139
 140         nand@6,0 {
 141                 compatible = "fsl,mpc8572-fcm-nand",
 142                              "fsl,elbc-fcm-nand";
 143                 reg = <0x6 0x0 0x40000>;
 144         };
 145 };
 146
 147 &board_soc {
 148         enet0: ethernet@24000 {
 149                 tbi-handle = <&tbi0>;
 150                 phy-handle = <&phy0>;
 151                 phy-connection-type = "rgmii-id";
 152         };
 153
 154         mdio@24520 {
 155                 phy0: ethernet-phy@0 {
 156                         interrupts = <10 1 0 0>;
 157                         reg = <0x0>;
 158                 };
 159                 phy1: ethernet-phy@1 {
 160                         interrupts = <10 1 0 0>;
 161                         reg = <0x1>;
 162                 };
 163                 phy2: ethernet-phy@2 {
 164                         interrupts = <10 1 0 0>;
 165                         reg = <0x2>;
 166                 };
 167                 phy3: ethernet-phy@3 {
 168                         interrupts = <10 1 0 0>;
 169                         reg = <0x3>;
 170                 };
 171
 172                 sgmii_phy0: sgmii-phy@0 {
 173                         interrupts = <6 1 0 0>;
 174                         reg = <0x1c>;
 175                 };
 176                 sgmii_phy1: sgmii-phy@1 {
 177                         interrupts = <6 1 0 0>;
 178                         reg = <0x1d>;
 179                 };
 180                 sgmii_phy2: sgmii-phy@2 {
 181                         interrupts = <7 1 0 0>;
 182                         reg = <0x1e>;
 183                 };
 184                 sgmii_phy3: sgmii-phy@3 {
 185                         interrupts = <7 1 0 0>;
 186                         reg = <0x1f>;
 187                 };
 188
 189                 tbi0: tbi-phy@11 {
 190                         reg = <0x11>;
 191                         device_type = "tbi-phy";
 192                 };
 193         };
 194
 195         ptp_clock@24e00 {
 196                 fsl,tclk-period = <5>;
 197                 fsl,tmr-prsc = <200>;
 198                 fsl,tmr-add = <0xAAAAAAAB>;
 199                 fsl,tmr-fiper1 = <0x3B9AC9FB>;
 200                 fsl,tmr-fiper2 = <0x3B9AC9FB>;
 201                 fsl,max-adj = <499999999>;
 202         };
 203
 204         enet1: ethernet@25000 {
 205                 tbi-handle = <&tbi1>;
 206                 phy-handle = <&phy1>;
 207                 phy-connection-type = "rgmii-id";
 208
 209         };
 210
 211         mdio@25520 {
 212                 tbi1: tbi-phy@11 {
 213                         reg = <0x11>;
 214                         device_type = "tbi-phy";
 215                 };
 216         };
 217
 218         enet2: ethernet@26000 {
 219                 tbi-handle = <&tbi2>;
 220                 phy-handle = <&phy2>;
 221                 phy-connection-type = "rgmii-id";
 222
 223         };
 224         mdio@26520 {
 225                 tbi2: tbi-phy@11 {
 226                         reg = <0x11>;
 227                         device_type = "tbi-phy";
 228                 };
 229         };
 230
 231         enet3: ethernet@27000 {
 232                 tbi-handle = <&tbi3>;
 233                 phy-handle = <&phy3>;
 234                 phy-connection-type = "rgmii-id";
 235         };
 236
 237         mdio@27520 {
 238                 tbi3: tbi-phy@11 {
 239                         reg = <0x11>;
 240                         device_type = "tbi-phy";
 241                 };
 242         };
 243 };
 244
 245 &board_pci0 {
 246         pcie@0 {
 247                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 248                 interrupt-map = <
 249                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 250                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 251                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 252                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 253                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 254
 255                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 256                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 257                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 258                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 259                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 260
 261                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 262                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 263                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 264                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 265                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 266
 267                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 268                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 269                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 270                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 271                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 272
 273                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 274                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 275                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 276                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 277                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 278
 279                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 280                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 281                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 282                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 283                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 284
 285                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 286                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 287                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 288                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 289                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 290
 291                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 292                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 293                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 294                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
 295                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 296
 297                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 298                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 299                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 300                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 301                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 302
 303                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 304                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 305                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 306                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 307                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 308
 309                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 310                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 311                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 312                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 313                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 314
 315                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 316                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 317                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 318                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 319                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 320
 321                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 322                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 323                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 324                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 325                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 326
 327                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 328                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 329                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 330                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 331                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 332
 333                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 334                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 335                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 336                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 337                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 338
 339                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 340                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 341                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
 342                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 343                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
 344
 345                         // IDSEL 0x1c  USB
 346                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 347                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 348                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 349                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 350
 351                         // IDSEL 0x1d  Audio
 352                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 353
 354                         // IDSEL 0x1e Legacy
 355                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 356                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 357
 358                         // IDSEL 0x1f IDE/SATA
 359                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 360                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 361                         >;
 362
 363
 364                 uli1575@0 {
 365                         reg = <0x0 0x0 0x0 0x0 0x0>;
 366                         #size-cells = <2>;
 367                         #address-cells = <3>;
 368                         ranges = <0x2000000 0x0 0x80000000
 369                                   0x2000000 0x0 0x80000000
 370                                   0x0 0x20000000
 371
 372                                   0x1000000 0x0 0x0
 373                                   0x1000000 0x0 0x0
 374                                   0x0 0x10000>;
 375                         isa@1e {
 376                                 device_type = "isa";
 377                                 #interrupt-cells = <2>;
 378                                 #size-cells = <1>;
 379                                 #address-cells = <2>;
 380                                 reg = <0xf000 0x0 0x0 0x0 0x0>;
 381                                 ranges = <0x1 0x0 0x1000000 0x0 0x0
 382                                           0x1000>;
 383                                 interrupt-parent = <&i8259>;
 384
 385                                 i8259: interrupt-controller@20 {
 386                                         reg = <0x1 0x20 0x2
 387                                                0x1 0xa0 0x2
 388                                                0x1 0x4d0 0x2>;
 389                                         interrupt-controller;
 390                                         device_type = "interrupt-controller";
 391                                         #address-cells = <0>;
 392                                         #interrupt-cells = <2>;
 393                                         compatible = "chrp,iic";
 394                                         interrupts = <9 2 0 0>;
 395                                         interrupt-parent = <&mpic>;
 396                                 };
 397
 398                                 i8042@60 {
 399                                         #size-cells = <0>;
 400                                         #address-cells = <1>;
 401                                         reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 402                                         interrupts = <1 3 12 3>;
 403                                         interrupt-parent =
 404                                                 <&i8259>;
 405
 406                                         keyboard@0 {
 407                                                 reg = <0x0>;
 408                                                 compatible = "pnpPNP,303";
 409                                         };
 410
 411                                         mouse@1 {
 412                                                 reg = <0x1>;
 413                                                 compatible = "pnpPNP,f03";
 414                                         };
 415                                 };
 416
 417                                 rtc@70 {
 418                                         compatible = "pnpPNP,b00";
 419                                         reg = <0x1 0x70 0x2>;
 420                                 };
 421
 422                                 gpio@400 {
 423                                         reg = <0x1 0x400 0x80>;
 424                                 };
 425                         };
 426                 };
 427         };
 428 };